,2014.3" TimingSummary"PB_RTimingSummaryp 2012.4)Timing analysis from Implemented netlist. <> ҏ6<ҏ6%ͣ>&+,fr 2014.3Zmin_maxbslackh p}IIqreport_timing_summary -max_paths 10 -file ngFEC_top_timing_summary_routed.rpt -pb ngFEC_top_timing_summary_routed.pb -rpx ngFEC_top_timing_summary_routed.rpx -warn_on_violationW -1Cmin_max (08@HX`hpx"  ReportTiming Summary Report  Design ngFEC_top ^ PartVDevice=xcku115 Package=flva2104 Speed=-1 (PRODUCTION 1.26 12-04-2018) Temperature=C T VersionIVivado v2020.2 (64-bit) SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 DateSat Mar 13 04:52:50 2021  Commandreport_timing_summary -max_paths 10 -file ngFEC_top_timing_summary_routed.rpt -pb ngFEC_top_timing_summary_routed.pb -rpx ngFEC_top_timing_summary_routed.rpx -warn_on_violation*. 9 DRPclk3@I@!(0:#@ > GBT_refclk0Ë>@n t@!(0:Ë>? Q gtwiz_userclk_rx_srcclk_out[0]y @"^@!(0:y@ S gtwiz_userclk_rx_srcclk_out[0]_1y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_10y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_11y @"^@!(0:y@ S gtwiz_userclk_rx_srcclk_out[0]_2y @"^@!(0:y@ S gtwiz_userclk_rx_srcclk_out[0]_3y @"^@!(0:y@ S gtwiz_userclk_rx_srcclk_out[0]_4y @"^@!(0:y@ S gtwiz_userclk_rx_srcclk_out[0]_5y @"^@!( 0:y@ S gtwiz_userclk_rx_srcclk_out[0]_6y @"^@!( 0:y@ S gtwiz_userclk_rx_srcclk_out[0]_7y @"^@!( 0:y@ S gtwiz_userclk_rx_srcclk_out[0]_8y @"^@!( 0:y@ S gtwiz_userclk_rx_srcclk_out[0]_9y @"^@!( 0:y@ E qpll0outclk_out[0]Ë>?n @!(0:Ë>? H qpll0outrefclk_out[0]Ë>@n t@!(0:Ë>? E txoutclk_out[0]_49Ë>@n t@!(0:Ë>? > GBT_refclk1Ë>@n t@!(0:Ë>? T !gtwiz_userclk_rx_srcclk_out[0]_12y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_13y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_14y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_15y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_16y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_17y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_18y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_19y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_20y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_21y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_22y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_23y @"^@!(0:y@ > GBT_refclk2Ë>@n t@!(0:Ë>? T !gtwiz_userclk_rx_srcclk_out[0]_24y @"^@!(0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_25y @"^@!( 0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_26y @"^@!(!0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_27y @"^@!("0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_28y @"^@!(#0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_29y @"^@!($0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_30y @"^@!(%0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_31y @"^@!(&0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_32y @"^@!('0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_33y @"^@!((0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_34y @"^@!()0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_35y @"^@!(*0:y@ > GBT_refclk3Ë>@n t@!(+0:Ë>? T !gtwiz_userclk_rx_srcclk_out[0]_36y @"^@!(,0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_37y @"^@!(-0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_38y @"^@!(.0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_39y @"^@!(/0:y@ T !gtwiz_userclk_rx_srcclk_out[0]_40y @"^@!(00:y@ T !gtwiz_userclk_rx_srcclk_out[0]_41y @"^@!(10:y@ T !gtwiz_userclk_rx_srcclk_out[0]_42y @"^@!(20:y@ T !gtwiz_userclk_rx_srcclk_out[0]_43y @"^@!(30:y@ T !gtwiz_userclk_rx_srcclk_out[0]_44y @"^@!(40:y@ T !gtwiz_userclk_rx_srcclk_out[0]_45y @"^@!(50:y@ T !gtwiz_userclk_rx_srcclk_out[0]_46y @"^@!(60:y@ T !gtwiz_userclk_rx_srcclk_out[0]_47y @"^@!(70:y@ @ TTC_rx_refclkË>@n t@!(80:Ë>? E qpll1outclk_out[0]Ë>?n @!(90:Ë>? D rxoutclk_out[0]_1Ë>@n t@!(:0:Ë>? H qpll1outrefclk_out[0]Ë>@n t@!(;0:Ë>? ? TTC_rxusrclkË>@n t@!(<0:Ë>? @ fabric_clk_inË>8@n D@!(=0:Ë>(@ ; CLKFBOUTË>8@n D@!(>0:Ë>@yuȶ2@ A fabric_clk_dcmË>8@n D@!(?0:Ë>(@ A tx_wordclk_dcmy @"^@!(@0:y@ 9 clk125@@_@!(A0:@ 9 clk250@@o@!(B0:? = fabric_clkË>8@n D@!(C0:Ë>(@ : ipb_clk?@@?@!(D0:/@ < refclk125@@_@!(E0:@ = DRPclk_dcm3@I@!(F0:#@ = clk125_dcm@@_@!(G0:@ = clk250_dcm@@o@!(H0:? > clk62_5_dcm/@@O@!(I0:@ > ipb_clk_dcm?@@?@!(J0:/@ < rx_rcvclkË>@n t@!(K0:Ë>? = tx_wordclkM @F^@!(L0:M@2 checkTimingRpx" no_clockH" constant_clockH" pulse_width_clockH"$ unconstrained_internal_endpointsH"/ no_input_delayPorts with no input delay(H"1 no_output_delayPorts with no output delay(H" multiple_clockH" generated_clocksH" loopsH" partial_input_delayH" partial_output_delayH" latch_loopsH0 : checking no_clock checking constant_clock checking pulse_width_clock )checking unconstrained_internal_endpoints checking no_input_delay checking no_output_delay checking multiple_clock checking generated_clocks checking loops checking partial_input_delay checking partial_output_delay checking latch_loopsJ checking no_clock3 / There are 0 register/latch pins with no clock./V checking constant_clock9 5 There are 0 register/latch pins with constant_clock.5a checking pulse_width_clockA = There are 0 register/latch pins which need pulse_width check= )checking unconstrained_internal_endpointsA = There are 0 pins that are not constrained for maximum delay.=W S There are 0 pins that are not constrained for maximum delay due to constant clock.S checking no_input_delayC ? There are 35 input ports with no input delay specified. (HIGH)?V R There are 0 input ports with no input delay but user has a false path constraint.R# checking no_output_delay> : There are 28 ports with no output delay specified. (HIGH):P L There are 0 ports with no output delay but user has a false path constraintLk g There are 0 ports with no output delay but with a timing clock defined on it or propagating through itgW checking multiple_clock: 6 There are 0 register/latch pins with multiple clocks.6j checking generated_clocksK G There are 0 generated clocks that are not connected to a clock source.GG checking loops3 / There are 0 combinational loops in the design./b checking partial_input_delay@ < There are 0 input ports with partial input delay specified.<^ checking partial_output_delay; 7 There are 0 ports with partial output delay specified.7f checking latch_loopsL H There are 0 combinational latch loops in the design through latch inputH& ns"MHz(0Bcheck_timing reportB SlowYesYes FastYesYes# Enable Multi Corner AnalysisYes Enable Pessimism RemovalYes3 Pessimism Removal ResolutionNearest Common Node& Enable Input Delay Default ClockNo Enable Preset / Clear ArcsNo Disable Flight DelaysNo Ignore I/O PathsNo. (Timing Early Launch at Borrowing LatchesNo+ $Borrow Time for Max Delay ExceptionsYes Merge Timing ExceptionsYes"B Timing Configuration Reportns"MHz(0Bconfig timing reportR  !)19AIe<>hq}ҏ6<ҏ6ͣ>8@CHP6X`ZE ) DRPclk Min Period 2w̫2.0"PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genReset_s_reg/C*n/a2, DRPclkA A"i_DRPclk_bufg/O Min Period 2w̫2.0"`\g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C*n/a2, DRPclkA A"i_DRPclk_bufg/O Min Period 2w̫2.0"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/C*n/a2, DRPclkA A"i_DRPclk_bufg/O Min Period 2w̫2.0"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/C*n/a2, DRPclkA A"i_DRPclk_bufg/O Min Period 2w̫2.0"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C*n/a2, DRPclkA A"i_DRPclk_bufg/O Min Period 2w̫2.0"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/C*n/a2, DRPclkA A"i_DRPclk_bufg/O Min Period 2w̫2.0"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/C*n/a2, DRPclkA A"i_DRPclk_bufg/O Min Period 2w̫2.0"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/C*n/a2, DRPclkA A"i_DRPclk_bufg/O Min Period 2w̫2.0"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/C*n/a2, DRPclkA A"i_DRPclk_bufg/O Min Period 2w̫2.0"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/C*n/a2, DRPclkA A"i_DRPclk_bufg/O" Low '2v+2./"`\g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C*Fast2, DRPclkA A"i_DRPclk_bufg/O" Low '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/C*Fast2, DRPclkA A"i_DRPclk_bufg/O" Low '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/C*Fast2, DRPclkA A"i_DRPclk_bufg/O" Low '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O" Low '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O" Low '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O" Low '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O" Low '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/C*Fast2, DRPclkA A"i_DRPclk_bufg/O" Low '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/C*Fast2, DRPclkA A"i_DRPclk_bufg/O" Low '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/C*Fast2, DRPclkA A"i_DRPclk_bufg/O* High '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O* High '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O* High '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O* High '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O* High '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O* High '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O* High '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O* High '2v+2./"a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O* High '2v+2./"`\g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O* High '2v+2./"`\g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[9]/C*Slow2, DRPclkA A"i_DRPclk_bufg/O  gtwiz_userclk_rx_srcclk_out[0]_1 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"IEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"IEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"NJg_gbt_bank[0].gbtbank/i_gbt_bank/g_rx_data_good[10].rx_data_good_reg[10]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"|xg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0` .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" _m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0` .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_1A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_21 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"3/g_clock_rate_din[19].rx_frameclk_div2_reg[19]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"3/g_clock_rate_din[19].rx_test_comm_cnt_reg[19]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"3/g_clock_rate_din[19].rx_test_comm_cnt_reg[19]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"2.g_clock_rate_din[19].rx_wordclk_div2_reg[19]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[19].ngccm_status_cnt_reg[19][6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[19].rx_test_comm_cnt_reg[19]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ^m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_21A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  CLKFBOUTp Min Periodb -2V20"CLKFBOUT_bufg/I*n/a27 CLKFBOUTA@EA"fabric_clk_MMCM/CLKFBOUTy Min Periodk @2V2w̫0"fabric_clk_MMCM/CLKFBOUT*n/a27 CLKFBOUTA@EA"fabric_clk_MMCM/CLKFBOUTx Min Periodj @2V2w̫0"fabric_clk_MMCM/CLKFBIN*n/a27 CLKFBOUTA@EA"fabric_clk_MMCM/CLKFBOUT ר !gtwiz_userclk_rx_srcclk_out[0]_43 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"A=SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"A=SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCSFP_GEN[41].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"HDSFP_GEN[41].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"HDSFP_GEN[41].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[12]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"HDSFP_GEN[41].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[19]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCSFP_GEN[41].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[50]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[54]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[58]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" Q 0%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" +o0%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_43A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ڦ !gtwiz_userclk_rx_srcclk_out[0]_32 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[30].ngccm_status_cnt_reg[30][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[52]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[72]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[56]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[58]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[30].rx_frameclk_div2_reg[30]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[21]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"/+SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[34]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[36]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" T 00%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" .o00%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_32A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_10 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"1-g_clock_rate_din[8].rx_frameclk_div2_reg[8]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[8].ngccm_status_cnt_reg[8][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" _m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_10A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Y TTC_rxusrclk Min Period 0VV1/1"i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O Min Period 0VV1/1"i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O Min Period o1VV1w̫0"!i_tcds2_if/bufgce_clk_40_rx/I*n/a2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O Min Period S01VV1.0"40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C*n/a2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O Min Period S01VV1.0">:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[0]/C*n/a2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O Min Period S01VV1.0"@:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[0]/C*Slow2v TTC_rxusrclkG@?"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O" Low P0V0./"@SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[54]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[60]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[62]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[64]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_44A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ֧ !gtwiz_userclk_rx_srcclk_out[0]_33 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[31].ngccm_status_cnt_reg[31][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[52]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[54]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[56]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[60]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"2.g_clock_rate_din[31].rx_wordclk_div2_reg[31]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[31].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[50]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" T 00%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" .o00%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_33A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_22 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"A=SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"A=SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[52]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[20].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" _m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_22A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Ǩ !gtwiz_userclk_rx_srcclk_out[0]_11 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[9].ngccm_status_cnt_reg[9][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0` .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" _m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0` .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_11A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  rxoutclk_out[0]_1 Min Period u0VV10"WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 rxoutclk_out[0]_1G@?"i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_45 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[43].ngccm_status_cnt_reg[43][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[32]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[34]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[43].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[66]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" T 00%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" .o00%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_45A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Ц !gtwiz_userclk_rx_srcclk_out[0]_34 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low F:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low F:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[20]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[40]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[42]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[44]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[46]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[32].ngccm_status_cnt_reg[32][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[32].rx_test_comm_cnt_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[32].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_34A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_23 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"A=SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"A=SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[21].ngccm_status_cnt_reg[21][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"3/g_clock_rate_din[21].rx_test_comm_cnt_reg[21]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[21].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" \m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_23A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ٦ !gtwiz_userclk_rx_srcclk_out[0]_12 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[12].ngccm_status_cnt_reg[12][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" _m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_12A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ) clk125 Min Period _p1_p 2_p1"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a2, clk125A@"i_clk125_bufg/O Min Periodx .1_p 2je1"40ipb/udp_if/internal_ram/ram_reg_bram_0/CLKARDCLK*n/a2, clk125A@"i_clk125_bufg/O Min Periodx 0l1_p 21"40ipb/udp_if/internal_ram/ram_reg_bram_0/CLKBWRCLK*n/a2, clk125A@"i_clk125_bufg/O Min Periody 0l1_p 21"51ipb/udp_if/ipbus_rx_ram/ram1_reg_bram_0/CLKARDCLK*n/a2, clk125A@"i_clk125_bufg/O Min Periody 0l1_p 21"51ipb/udp_if/ipbus_rx_ram/ram1_reg_bram_1/CLKARDCLK*n/a2, clk125A@"i_clk125_bufg/O Min Periody 0l1_p 21"51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKARDCLK*n/a2, clk125A@"i_clk125_bufg/O Min Periody 0l1_p 21"51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CLKARDCLK*n/a2, clk125A@"i_clk125_bufg/O Min Periody 0l1_p 21"51ipb/udp_if/ipbus_rx_ram/ram3_reg_bram_0/CLKARDCLK*n/a2, clk125A@"i_clk125_bufg/O Min Periody 0l1_p 21"51ipb/udp_if/ipbus_rx_ram/ram3_reg_bram_1/CLKARDCLK*n/a2, clk125A@"i_clk125_bufg/O Min Periody 0l1_p 21"51ipb/udp_if/ipbus_rx_ram/ram4_reg_bram_0/CLKARDCLK*n/a2, clk125A@"i_clk125_bufg/O" Low .1^p1c0"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow2, clk125A@"i_clk125_bufg/O" Low .1^p1c0"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast2, clk125A@"i_clk125_bufg/O" Lowy ?H1^p1:B0"40ipb/udp_if/internal_ram/ram_reg_bram_0/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O" Lowy ?H1^p1:B0"40ipb/udp_if/internal_ram/ram_reg_bram_0/CLKARDCLK*Fast2, clk125A@"i_clk125_bufg/O" Lowy tQ1^p1ׂ0"40ipb/udp_if/internal_ram/ram_reg_bram_0/CLKBWRCLK*Slow2, clk125A@"i_clk125_bufg/O" Lowz tQ1^p1ׂ0"51ipb/udp_if/ipbus_rx_ram/ram1_reg_bram_1/CLKARDCLK*Fast2, clk125A@"i_clk125_bufg/O" Lowz tQ1^p1ׂ0"51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKARDCLK*Fast2, clk125A@"i_clk125_bufg/O" Lowz tQ1^p1ׂ0"51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O" Lowz tQ1^p1ׂ0"51ipb/udp_if/ipbus_rx_ram/ram3_reg_bram_0/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O" Lowz tQ1^p1ׂ0"51ipb/udp_if/ipbus_rx_ram/ram4_reg_bram_0/CLKARDCLK*Fast2, clk125A@"i_clk125_bufg/O* High .1_p1c0"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow2, clk125A@"i_clk125_bufg/O* High .1_p1c0"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast2, clk125A@"i_clk125_bufg/O* Highy ?H1_p1:B0"40ipb/udp_if/internal_ram/ram_reg_bram_0/CLKARDCLK*Fast2, clk125A@"i_clk125_bufg/O* Highy ?H1`p1:B0"40ipb/udp_if/internal_ram/ram_reg_bram_0/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O* Highz tQ1^p1ׂ0"51ipb/udp_if/ipbus_rx_ram/ram3_reg_bram_1/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O* Highz tQ1^p1ׂ0"51ipb/udp_if/ipbus_rx_ram/ram4_reg_bram_0/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O* Highz tQ1^p1ׂ0"51ipb/udp_if/ipbus_rx_ram/ram4_reg_bram_1/CLKARDCLK*Slow2, clk125A@"i_clk125_bufg/O* Highy tQ1^p1ׂ0"40ipb/udp_if/ipbus_tx_ram/ram_reg_bram_4/CLKBWRCLK*Slow2, clk125A@"i_clk125_bufg/O* Highy tQ1^p1ׂ0"40ipb/udp_if/ipbus_tx_ram/ram_reg_bram_5/CLKBWRCLK*Slow2, clk125A@"i_clk125_bufg/O* Highy tQ1_p1ׂ0"40ipb/udp_if/internal_ram/ram_reg_bram_0/CLKBWRCLK*Slow2, clk125A@"i_clk125_bufg/O  clk250_dcmo Min Perioda %1_p10"i_clk250_bufg/I*n/a26 clk250_dcm@@"i_clk125_MMCM/CLKOUT3u Min Periodg <1_p1w̫0"i_clk125_MMCM/CLKOUT3*n/a26 clk250_dcm@@"i_clk125_MMCM/CLKOUT3  tx_wordclk Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O Min Period T12_p1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*n/a22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low ("11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low ("11c0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low ("11c0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low ("11c0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O" Low *"11c0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O* High *"11c0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK*Slow22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" I0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" I0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" I0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" G0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" I0-0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast22 tx_wordclkoAo@"tx_wordclk_bufg/O լ !gtwiz_userclk_rx_srcclk_out[0]_41 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[39].ngccm_status_cnt_reg[39][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" Q 0%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" +o0%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_41A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ө !gtwiz_userclk_rx_srcclk_out[0]_30 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"_[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/psAddress_reg[1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"_[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/psAddress_reg[2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[28].ngccm_status_cnt_reg[28][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_30A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  gtwiz_userclk_rx_srcclk_out[0] Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"@:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"VRg_gbt_bank[0].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][0]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"VRg_gbt_bank[0].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0` .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ]m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0` .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_2A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  gtwiz_userclk_rx_srcclk_out[0]_3 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[0].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][0]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" \m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_3A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  gtwiz_userclk_rx_srcclk_out[0]_5 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0")%SFP_GEN[3].ngccm_rx_down_cnt_reg[3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"+'SFP_GEN[3].ngccm_status_reg_reg[3][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0",(SFP_GEN[3].ngccm_status_reg_reg[3][16]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0",(SFP_GEN[3].ngccm_status_reg_reg[3][17]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0",(SFP_GEN[3].ngccm_status_reg_reg[3][18]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0",(SFP_GEN[3].ngccm_status_reg_reg[3][19]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"+'SFP_GEN[3].ngccm_status_reg_reg[3][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./")%SFP_GEN[3].ngccm_rx_down_cnt_reg[3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[3].ngccm_status_reg_reg[3][0]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./",(SFP_GEN[3].ngccm_status_reg_reg[3][17]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./",(SFP_GEN[3].ngccm_status_reg_reg[3][18]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./",(SFP_GEN[3].ngccm_status_reg_reg[3][19]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[3].ngccm_status_reg_reg[3][1]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./")%SFP_GEN[3].ngccm_rx_down_cnt_reg[3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./",(SFP_GEN[3].ngccm_status_reg_reg[3][16]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./",(SFP_GEN[3].ngccm_status_reg_reg[3][23]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./",(SFP_GEN[3].ngccm_status_reg_reg[3][24]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"($SFP_GEN[3].rx_data_ngccm_reg[3][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./")%SFP_GEN[3].rx_data_ngccm_reg[3][21]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ^m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_5A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  gtwiz_userclk_rx_srcclk_out[0]_6 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" _m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_6A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  gtwiz_userclk_rx_srcclk_out[0]_7 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][6]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][6]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"1-g_clock_rate_din[5].rx_frameclk_div2_reg[5]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"1-g_clock_rate_din[5].rx_test_comm_cnt_reg[5]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][0]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][1]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"40g_clock_rate_din[5].ngccm_status_cnt_reg[5][5]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ]m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_7A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  gtwiz_userclk_rx_srcclk_out[0]_8 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][6]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][0]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][1]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][2]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[6].ngccm_status_cnt_reg[6][5]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,g_clock_rate_din[6].rx_wordclk_div2_reg[6]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ^m0-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_8A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  gtwiz_userclk_rx_srcclk_out[0]_9 Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][0]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][1]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][2]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][3]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][4]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][5]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][6]/C*n/a2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][0]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40g_clock_rate_din[7].ngccm_status_cnt_reg[7][4]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"1-g_clock_rate_din[7].rx_frameclk_div2_reg[7]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,g_clock_rate_din[7].rx_wordclk_div2_reg[7]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5]/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0h-a0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" `m0h-;qr0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 gtwiz_userclk_rx_srcclk_out[0]_9A@"g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_46 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low F:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low F:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[76]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[78]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[44].rx_data_ngccm_reg[44][32]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[44].rx_data_ngccm_reg[44][35]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[44].rx_data_ngccm_reg[44][36]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[44].rx_data_ngccm_reg[44][37]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[44].ngccm_status_cnt_reg[44][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[44].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" T 00%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" .o00%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_46A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_35 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[33].ngccm_status_cnt_reg[33][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./";7SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/shiftA_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./";7SFP_GEN[33].ngCCM_gbt/CrossClock_DV_cnt/shiftA_reg[1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" T 00%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" .o00%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_35A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_24 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[24].ngccm_status_cnt_reg[24][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[80]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[24].ngCCM_gbt/RX_Word_rx40_reg[83]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[24].rx_data_ngccm_reg[24][49]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[24].rx_data_ngccm_reg[24][64]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[24].rx_data_ngccm_reg[24][65]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[24].rx_data_ngccm_reg[24][66]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[24].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[24].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[24].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[24].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[24].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[24].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_24A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ԧ !gtwiz_userclk_rx_srcclk_out[0]_13 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[22].ngccm_status_cnt_reg[22][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[22].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ]m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_13A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_47 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[45].ngccm_status_cnt_reg[45][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low F:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low F:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"2.g_clock_rate_din[45].rx_wordclk_div2_reg[45]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[45].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[58]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"GCSFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"HDSFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[12]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"HDSFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_47A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_36 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][7]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"*&SFP_GEN[36].rx_data_ngccm_reg[36][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"*&SFP_GEN[36].rx_data_ngccm_reg[36][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[36].ngccm_status_cnt_reg[36][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[36].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_36A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_25 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[28]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[80]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[81]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[34].rx_data_ngccm_reg[34][28]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[34].rx_data_ngccm_reg[34][42]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[34].rx_data_ngccm_reg[34][43]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[34].ngccm_status_cnt_reg[34][7]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[34].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[50]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_25A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ֧ !gtwiz_userclk_rx_srcclk_out[0]_14 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[23].ngccm_status_cnt_reg[23][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./">:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./">:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./">:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0` .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" _m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0` .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_14A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_37 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40SFP_GEN[46].ngCCM_gbt/RX_Clock_20MHz_dl_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"40SFP_GEN[46].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"73SFP_GEN[46].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"73SFP_GEN[46].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"73SFP_GEN[46].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"73SFP_GEN[46].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[46].ngccm_status_cnt_reg[46][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"2.g_clock_rate_din[46].rx_wordclk_div2_reg[46]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_37A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_26 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[60]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"0,SFP_GEN[35].ngCCM_gbt/RX_Word_rx40_reg[62]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[35].ngccm_status_cnt_reg[35][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"VRg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"VRg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"VRg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"VRg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[11].rx_data_good_cntr_reg[11][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_26A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ٦ !gtwiz_userclk_rx_srcclk_out[0]_15 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[13].ngccm_status_cnt_reg[13][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ]m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_15A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_38 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[47].ngccm_status_cnt_reg[47][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./">:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[47].rx_data_ngccm_reg[47][43]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[47].rx_data_ngccm_reg[47][45]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[47].rx_data_ngccm_reg[47][47]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"+'SFP_GEN[47].rx_data_ngccm_reg[47][49]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[47].rx_frameclk_div2_reg[47]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[47].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[47].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[47].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[47].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[42]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[47].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_38A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_27 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[25].ngccm_status_cnt_reg[25][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[1].rx_data_good_cntr_reg[1][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_27A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_16 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[14].ngccm_status_cnt_reg[14][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0h-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" `m0h-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_16A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  fabric_clk_dcmw Min Periodi -2V20"fabric_clk_bufg/I*n/a2< fabric_clk_dcmAGA"fabric_clk_MMCM/CLKOUT0} Min Periodo @2V2w̫0"fabric_clk_MMCM/CLKOUT0*n/a2< fabric_clk_dcmAGA"fabric_clk_MMCM/CLKOUT0  !gtwiz_userclk_rx_srcclk_out[0]_39 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[46]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[58]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"B>SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[60]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[37].ngccm_status_cnt_reg[37][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[44]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[37].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_39A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_28 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[2].rx_data_good_cntr_reg[2][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[2].rx_data_good_cntr_reg[2][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[2].rx_data_good_cntr_reg[2][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[2].rx_data_good_cntr_reg[2][3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"TPg_gbt_bank[2].gbtbank/i_gbt_bank/g_rx_data_good[2].rx_data_good_cntr_reg[2][4]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[26].ngccm_status_cnt_reg[26][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_28A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_17 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[15].ngccm_status_cnt_reg[15][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"2.g_clock_rate_din[15].rx_wordclk_div2_reg[15]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[3].rx_data_good_cntr_reg[3][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[3].rx_data_good_cntr_reg[3][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"TPg_gbt_bank[1].gbtbank/i_gbt_bank/g_rx_data_good[3].rx_data_good_cntr_reg[3][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0@ .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" _m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0@ .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_17A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ԫ !gtwiz_userclk_rx_srcclk_out[0]_29 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[27].ngccm_status_cnt_reg[27][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[27].rx_frameclk_div2_reg[27]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" T 00%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" .o00%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_29A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_18 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[16].ngccm_status_cnt_reg[16][7]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[16].rx_frameclk_div2_reg[16]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0` .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ^m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0` .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_18A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Ӧ !gtwiz_userclk_rx_srcclk_out[0]_19 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"3/g_clock_rate_din[17].rx_frameclk_div2_reg[17]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][3]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][5]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[17].ngccm_status_cnt_reg[17][7]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[17].rx_frameclk_div2_reg[17]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ]m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_19A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_42 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"A=SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"A=SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"B>SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_meta_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"A=SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"A=SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[4]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"B>SFP_GEN[40].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./".*SFP_GEN[40].ngCCM_gbt/RX_Clock_40MHz_reg/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[26]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[36]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[38]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_42A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK ӫ !gtwiz_userclk_rx_srcclk_out[0]_31 Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low L:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[47]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[53]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[54]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[37]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[38]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High H:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[29].ngccm_status_cnt_reg[29][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[29].rx_frameclk_div2_reg[29]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[29].rx_test_comm_cnt_reg[29]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" R 0%-a0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ,o0%-;qr0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_31A@"g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  !gtwiz_userclk_rx_srcclk_out[0]_20 Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low H:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][0]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][1]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[18].ngccm_status_cnt_reg[18][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[18].rx_frameclk_div2_reg[18]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"3/g_clock_rate_din[18].rx_test_comm_cnt_reg[18]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"2.g_clock_rate_din[18].rx_wordclk_div2_reg[18]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0` .o0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0-a0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" ^m0-;qr0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0` .ل0"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_20A@"g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Ь !gtwiz_userclk_rx_srcclk_out[0]_40 Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period ԯ12[1"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period @120"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][0]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][1]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][2]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][3]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][4]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][5]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK Min Period q22.0"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][6]/C*n/a2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK" Low q11./"g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High J:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High L:110"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"62g_clock_rate_din[38].ngccm_status_cnt_reg[38][7]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"<8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK* High q11./"D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" S 0p%-a0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0P-o0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" -o0p%-;qr0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 50P-ل0"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow2 !gtwiz_userclk_rx_srcclk_out[0]_40A@"g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK  refclk125g Min PeriodY XY1_p 20"i_refclk125_bufg/I*n/a2+ refclk125A@" refclk125_pi Min Period[ 1_p 2w̫0"i_clk125_MMCM/CLKIN1*n/a2+ refclk125A@" refclk125_p"c Low\ 0_p1?$1"i_clk125_MMCM/CLKIN1*Fast2+ refclk125A@" refclk125_p"c Low\ 0`p1?$1"i_clk125_MMCM/CLKIN1*Slow2+ refclk125A@" refclk125_p*d High\ 0^p1?$1"i_clk125_MMCM/CLKIN1*Slow2+ refclk125A@" refclk125_p*d High\ 0_p1?$1"i_clk125_MMCM/CLKIN1*Fast2+ refclk125A@" refclk125_p  tx_wordclk_dcmw Min Periodi @120"tx_wordclk_bufg/I*n/a2< tx_wordclk_dcmA@"fabric_clk_MMCM/CLKOUT1} Min Periodo 12w̫0"fabric_clk_MMCM/CLKOUT1*n/a2< tx_wordclk_dcmA@"fabric_clk_MMCM/CLKOUT1 z clk62_5_dcm Min Period [2_p2[1"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*n/a27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1 Min Period [2_p2[1"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*n/a27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1 Min Period [2_p2[1"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*n/a27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1 Min Period [2_p2[1"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2*n/a27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1q Min Periodc w2_p20"i_clk62_5_bufg/I*n/a27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1v Min Periodh /g}2_p2w̫0"i_clk125_MMCM/CLKOUT1*n/a27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1 Min Period 鶄2_p2.0"A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync1/C*n/a27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1 Min Period 鶄2_p2.0"A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync2/C*n/a27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1 Min Period 鶄2_p2.0"A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync3/C*n/a27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1 Min Period 鶄2_p2.0"A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync4/C*n/a27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1" Low \f1^p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1" Low \f1^p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1" Low \f1^p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1" Low \f1^p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1" Low ^f1_p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1" Low ^f1_p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2*Fast27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1" Low `f1`p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1" Low `f1`p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1" Low 2^p 2./"A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync1/C*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1" Low 2^p 2./"A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync2/C*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1* High ^f1_p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1* High ^f1_p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1* High ^f1_p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1* High ^f1_p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1* High ^f1_p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1* High ^f1_p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1* High ^f1_p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1* High ^f1_p 20"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2*Fast27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1* High 2^p 2./"A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync6/C*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1* High 2^p 2./"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT12eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2" 0 .o0"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT12eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" % 0`U-0"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Fast27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT12eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2"  0 -a0"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK*Fast27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT12eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2" 0F. (0"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT12eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK" a0F.~m0"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT12eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" Zm0 -;qr0"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Fast27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT12eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK" ]ru0`U-={0"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2*Fast27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT12eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK" 0 .ل0"eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2*Slow27 clk62_5_dcmAA"i_clk125_MMCM/CLKOUT1  DRPclk_dcmo Min Perioda *2w̫20"i_DRPclk_bufg/I*n/a26 DRPclk_dcmA A"i_clk125_MMCM/CLKOUT0u Min Periodg 2w̫2w̫0"i_clk125_MMCM/CLKOUT0*n/a26 DRPclk_dcmA A"i_clk125_MMCM/CLKOUT0 , fabric_clk Min Period Z2V2je1"c_SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"c_SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"d`SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O Min Period Z2V2je1"c_SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*n/a22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Fast22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Fast22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"c_SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Fast22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Fast22 fabric_clkAGA"fabric_clk_bufg/O" Low C2VV2:B0"d`SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Fast22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"c_SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Fast22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Fast22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O* High C2VV2:B0"d`SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg_bram_0/CLKARDCLK*Slow22 fabric_clkAGA"fabric_clk_bufg/O " fabric_clk_in Min Periods @2V2w̫0"fabric_clk_MMCM/CLKIN1*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Period{ 2V2.0""i_tcds2_if/BC0_early_cnt_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periodz 2V2.0"!i_tcds2_if/BC0_late_cnt_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Period| 2V2.0"#i_tcds2_if/BC0_onTime_cnt_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periodz 2V2.0"!i_tcds2_if/EvCntRes_cnt_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periodz 2V2.0"!i_tcds2_if/QIEreset_cnt_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periodu 2V2.0"i_tcds2_if/WTE_cnt_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periods 2V2.0"i_tcds2_if/WTE_i_reg/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periodu 2V2.0"i_tcds2_if/bcnt_reg[0]/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O Min Periodv 2V2.0"i_tcds2_if/bcnt_reg[10]/C*n/a2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O"{ Lowt V1VV2V1"fabric_clk_MMCM/CLKIN1*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O"{ Lowt V1VV2V1"fabric_clk_MMCM/CLKIN1*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./"C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./"C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./":6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[121]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./":6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[138]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./":6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[139]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./":6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[140]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./":6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[143]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O" Low Q2VV2./":6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[145]/C*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O*| Hight V1VV2V1"fabric_clk_MMCM/CLKIN1*Slow2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O*| Hight V1VV2V1"fabric_clk_MMCM/CLKIN1*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O* High{ Q2VV2./"!i_tcds2_if/QIEreset_cnt_reg/C*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O* High Q2VV2./"95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[10]/C*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O* High Q2VV2./":6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[115]/C*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O* High Q2VV2./":6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[124]/C*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O* High Q2VV2./"95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[12]/C*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O* High Q2VV2./":6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[134]/C*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O* High Q2VV2./":6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[135]/C*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O* High Q2VV2./":6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[141]/C*Fast2A fabric_clk_inAGA"!i_tcds2_if/bufgce_clk_40_rx/O 0 ipb_clk Min Period A3_p 31"|xSFP_GEN[1].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period A3_p 31"|xSFP_GEN[1].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period A3_p 31"uqSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period A3_p 31"uqSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period A3_p 31"uqSFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period A3_p 31"uqSFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period A3_p 31"|xSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period A3_p 31"|xSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period A3_p 31"|xSFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O Min Period A3_p 31"|xSFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK*n/a2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"|xSFP_GEN[1].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"uqSFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"|xSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"|xSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"|xSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"|xSFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"|xSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"|xSFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"uqSFP_GEN[7].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O" Low B2^p2ׂ0"uqSFP_GEN[7].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"uqSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"|xSFP_GEN[1].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"|xSFP_GEN[7].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"{wSFP_GEN[7].ngFEC_module/bram_array[2].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"{wSFP_GEN[1].ngFEC_module/bram_array[4].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"{wSFP_GEN[7].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"uqSFP_GEN[0].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"|xSFP_GEN[0].ngFEC_module/bram_array[11].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"tpSFP_GEN[0].ngFEC_module/bram_array[2].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK*Slow2. ipb_clkBA"i_ipb_clk_bufg/O* High B2^p2ׂ0"{wSFP_GEN[0].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK*Fast2. ipb_clkBA"i_ipb_clk_bufg/O  ipb_clk_dcmq Min Periodc r3_p 30"i_ipb_clk_bufg/I*n/a27 ipb_clk_dcmBA"i_clk125_MMCM/CLKOUT2v Min Periodh 3_p 3w̫0"i_clk125_MMCM/CLKOUT2*n/a27 ipb_clk_dcmBA"i_clk125_MMCM/CLKOUT28 Iq (08@HPX`hp Pulse Width Reportns"MHz(0:  ReportPulse Width Report  Design ngFEC_top ^ PartVDevice=xcku115 Package=flva2104 Speed=-1 (PRODUCTION 1.26 12-04-2018) Temperature=C T VersionIVivado v2020.2 (64-bit) SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 DateSat Mar 13 04:52:59 2021Bmin pulse width reporthpx DRPclkDRPclk!)#@13@9A#@I3@eFvAhq}<<<A rise - rise rise - rise  YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[5]/CZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]/D"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ (CARRY8=4)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuأp>}ÿˡſw>^?ˡ?<O 0>%=>zt?>a?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[5]/QProp_FFF_SLICEL_C_Q JFDREXhzr9H= WSg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[5] Jnet (fo=2, routed)XhY= d`g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[0]_i_2__46/S[5] JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[0]_i_2__46/CO[7]Prop_CARRY8_SLICEL_S[5]_CO[7] JCARRY8Xhzrxi= c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[0]_i_2__46_n_0 Jnet (fo=1, routed)Xh b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[8]_i_1__46/CI JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[8]_i_1__46/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8Xhzro< c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[8]_i_1__46_n_0 Jnet (fo=1, routed)Xh c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[16]_i_1__46/CI JXhzr fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[16]_i_1__46/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8Xhzro< d`g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[16]_i_1__46_n_0 Jnet (fo=1, routed)Xh c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]_i_1__46/CI JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]_i_1__46/O[0]Prop_CARRY8_SLICEL_CI_O[0] JCARRY8XhzrC = eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]_i_1__46_n_15 Jnet (fo=1, routed)Xh #< ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]/D JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr MIg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/DRPclk Jnet (fo=3888, routed)Xh^?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[5]/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr MIg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/DRPclk Jnet (fo=3888, routed)Xhˡ?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]/C JFDREXhzr> Jclock pessimismXhO XTg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhÿ; J arrival timeXh?/ JXh4 JslackXh<XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[3]/CYUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24]/D"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ (CARRY8=4)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu>}̿VοR%>İ?V?=O]B>u=>G?>?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[3]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= VRg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[3] Jnet (fo=2, routed)XhL= c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[0]_i_2__20/S[3] JXhzr d`g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[0]_i_2__20/CO[7]Prop_CARRY8_SLICEL_S[3]_CO[7] JCARRY8Xhzr= b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[0]_i_2__20_n_0 Jnet (fo=1, routed)Xh a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[8]_i_1__20/CI JXhzr d`g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[8]_i_1__20/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8Xhzro< b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[8]_i_1__20_n_0 Jnet (fo=1, routed)Xh b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[16]_i_1__20/CI JXhzr eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[16]_i_1__20/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8Xhzro< c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[16]_i_1__20_n_0 Jnet (fo=1, routed)Xh b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24]_i_1__20/CI JXhzr d`g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24]_i_1__20/O[0]Prop_CARRY8_SLICEL_CI_O[0] JCARRY8XhzrC = d`g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24]_i_1__20_n_15 Jnet (fo=1, routed)Xh #< YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24]/D JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/DRPclk Jnet (fo=3888, routed)Xhİ?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] XTg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[3]/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/DRPclk Jnet (fo=3888, routed)XhV?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24]/C JFDREXhzr> Jclock pessimismXhO WSg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/timer_ctr_reg[24]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh̿; J arrival timeXh?/ JXh4 JslackXh=ya]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/Ca]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ (CARRY8=3)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuD`e>}ףn= >c?ף?-+=xi'>u=>&q?>m?a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11] Jnet (fo=2, routed)XhL= jfg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__3/S[3] JXhzr kgg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__3/CO[7]Prop_CARRY8_SLICEL_S[3]_CO[7] JCARRY8Xhzr= ieg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__3_n_0 Jnet (fo=1, routed)Xh ieg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__3/CI JXhzr lhg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__3/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8Xhzro< jfg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__3_n_0 Jnet (fo=1, routed)Xh ieg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__3/CI JXhzr kgg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__3/O[0]Prop_CARRY8_SLICEL_CI_O[0] JCARRY8XhzrC = kgg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__3_n_15 Jnet (fo=1, routed)Xh #< a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)Xhc?X3Y4 (CLOCK_ROOT) a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)Xhף?X3Y4 (CLOCK_ROOT) a]g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C JFDCEXhzr> Jclock pessimismXhxi _[g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhk?/ JXh4 JslackXh-+=d`\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C`\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/D"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(CARRY8=2 LUT1=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuJs>}s><ߟ??-+=DF>X94=>`?>Z?a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/QProp_AFF_SLICEM_C_Q JFDCEXhzf9H= ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0] Jnet (fo=2, routed)Xh+= eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_5__24/I0 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_5__24/OProp_A6LUT_SLICEM_I0_O JLUT1Xhzru< fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_5__24_n_0 Jnet (fo=1, routed)Xho: kgg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__24/S[0] JXhzr lhg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__24/CO[7]Prop_CARRY8_SLICEM_S[0]_CO[7] JCARRY8Xhzr= jfg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__24_n_0 Jnet (fo=1, routed)Xh ieg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__24/CI JXhzr kgg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__24/O[0]Prop_CARRY8_SLICEM_CI_O[0] JCARRY8XhzrC = kgg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__24_n_15 Jnet (fo=1, routed)Xh #< `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/D JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)Xh<ߟ?X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)Xh?X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/C JFDCEXhzr> Jclock pessimismXhD ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhV?/ JXh4 JslackXh-+=X a]g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/CPLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_reg/D"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT6=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuo>}տֿ)>??C =ul=n>>?>G?a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) a]g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/QProp_BFF_SLICEM_C_Q JFDCEXhzf9H= _[g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25] Jnet (fo=3, routed)XhI > UQg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_i_1__41/I5 JXhzf TPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_i_1__41/OProp_D6LUT_SLICEL_I5_O JLUT6Xhzro= VRg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_i_1__41_n_0 Jnet (fo=1, routed)Xho< PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_reg/D JFDPEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)Xh?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[25]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)Xh?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_reg/C JFDPEXhzr> Jclock pessimismXhu NJg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genReset_s_regHold_DFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXhտ; J arrival timeXh#?/ JXh4 JslackXhC = a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/CPLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_reg/D"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT6=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu'>}d󭿍ro=i?r?1=zR ==>(\?>G?a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/QProp_AFF_SLICEL_C_Q JFDCEXhzf9H= _[g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24] Jnet (fo=3, routed)Xh= UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_i_1__32/I4 JXhzf TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_i_1__32/OProp_H6LUT_SLICEM_I4_O JLUT6Xhzro< VRg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_i_1__32_n_0 Jnet (fo=1, routed)Xho< PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_reg/D JFDPEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)Xhi?X3Y4 (CLOCK_ROOT) a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)Xhr?X3Y4 (CLOCK_ROOT) PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_reg/C JFDPEXhzr> Jclock pessimismXhzR  NJg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genReset_s_regHold_HFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXhd󭿐; J arrival timeXh]?/ JXh4 JslackXh1=h`\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/Ca]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/D"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(CARRY8=2 LUT1=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsut{>}s><ߟ??'=DJ>D=>`?>Z?a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/QProp_AFF_SLICEM_C_Q JFDCEXhzf9H= ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0] Jnet (fo=2, routed)Xh+= eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_5__24/I0 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_5__24/OProp_A6LUT_SLICEM_I0_O JLUT1Xhzru< fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_5__24_n_0 Jnet (fo=1, routed)Xho: kgg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__24/S[0] JXhzr lhg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__24/CO[7]Prop_CARRY8_SLICEM_S[0]_CO[7] JCARRY8Xhzr= jfg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__24_n_0 Jnet (fo=1, routed)Xh ieg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__24/CI JXhzr kgg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__24/O[2]Prop_CARRY8_SLICEM_CI_O[2] JCARRY8Xhzr= kgg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__24_n_13 Jnet (fo=1, routed)XhA`e< a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/D JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)Xh<ߟ?X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)Xh?X3Y4 (CLOCK_ROOT) a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/C JFDCEXhzr> Jclock pessimismXhD _[g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh*\?/ JXh4 JslackXh'=L zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/Cxtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/D"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZj)DRPclk rise@0.000ns - DRPclk rise@0.000nsu/>}AHG=T?G?/=|SD=l=>l?>D?a(rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/QProp_CFF2_SLICEM_C_Q JFDPEXhzrD= tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3 Jnet (fo=1, routed)Xhl= xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/D JFDPEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)XhT?X3Y4 (CLOCK_ROOT) zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)XhG?X3Y4 (CLOCK_ROOT) xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXh|S vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_regHold_AFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXhAH; J arrival timeXhƻ?/ JXh4 JslackXh/=`\g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/Ca]g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ (CARRY8=4)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuC>}/ԿA`տ 0>?A`?}94=uV>%=>'1?>ף?a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) `\g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= ^Zg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1] Jnet (fo=2, routed)XhY= kgg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__41/S[1] JXhzr lhg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__41/CO[7]Prop_CARRY8_SLICEM_S[1]_CO[7] JCARRY8Xhzr= jfg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]_i_2__41_n_0 Jnet (fo=1, routed)Xh ieg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__41/CI JXhzr lhg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__41/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8Xhzro< jfg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]_i_1__41_n_0 Jnet (fo=1, routed)Xh jfg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__41/CI JXhzr mig_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__41/CO[7]Prop_CARRY8_SLICEM_CI_CO[7] JCARRY8Xhzro< kgg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]_i_1__41_n_0 Jnet (fo=1, routed)Xh jfg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__41/CI JXhzr lhg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__41/O[0]Prop_CARRY8_SLICEM_CI_O[0] JCARRY8XhzrC = lhg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]_i_1__41_n_15 Jnet (fo=1, routed)Xh #< a]g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/D JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)Xh?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] `\g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhA`?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]/C JFDCEXhzr> Jclock pessimismXhu _[g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/generalRstProcess.timer_reg[24]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh/Կ; J arrival timeXh~?/ JXh4 JslackXh}94=X a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CPLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_reg/D"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT6=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsu/>};6¿ ̿=J ? ?S,7=} v=v=>\?>?a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDPE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})FastDRPclkDRPclkDRPclk(DCD - SCD - CPR) a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/QProp_CFF_SLICEM_C_Q JFDCEXhzfD= _[g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18] Jnet (fo=3, routed)Xh-= UQg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_i_1__19/I1 JXhzf TPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_i_1__19/OProp_D6LUT_SLICEL_I1_O JLUT6Xhzr< VRg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_i_1__19_n_0 Jnet (fo=1, routed)Xho< PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_reg/D JFDPEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhJ ?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] a]g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)Xh ?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_reg/C JFDPEXhzr> Jclock pessimismXh}  NJg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genReset_s_regHold_DFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh;6¿; J arrival timeXh?/ JXh4 JslackXhS,7=ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[23]/C[Wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]/CE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu%@}A AH둾"c@H@A =А=k>FvA$>~>jt@ |?#@lg?@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[23]/QProp_HFF_SLICEL_C_Q JFDREXhzrO > XTg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[23] Jnet (fo=2, routed)Xh-? ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/tx_timer_sat_i_6__46/I1 JXhzr ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/tx_timer_sat_i_6__46/OProp_G6LUT_SLICEL_I1_O JLUT5XhzrE= _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/tx_timer_sat_i_6__46_n_0 Jnet (fo=1, routed)Xh'1> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/tx_timer_sat_i_2__46/I5 JXhzr ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/tx_timer_sat_i_2__46/OProp_H6LUT_SLICEM_I5_O JLUT6XhzrGa= _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/tx_timer_sat_i_2__46_n_0 Jnet (fo=3, routed)Xhl> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr[0]_i_1__46/I0 JXhzr ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr[0]_i_1__46/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzr`P= PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr Jnet (fo=25, routed)XhZd? [Wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]/CE JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr MIg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/DRPclk Jnet (fo=3888, routed)Xh"c@X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[23]/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr MIg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/DRPclk Jnet (fo=3888, routed)XhH@X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ZVg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]/C JFDREXhzr> Jclock pessimismXh$>@ Jclock uncertaintyXh  XTg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/timer_ctr_reg[24]Setup_AFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh A; J arrival timeXh/ JXh4 JslackXhFvA`\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Cb^g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuJ@}A AGAŒE^@GA@A =А=k>&Ai̽>V?O@ |?@lg?l@a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/QProp_DFF_SLICEL_C_Q JFDCEXhzfV> ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] Jnet (fo=2, routed)Xh> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/I2 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzf"y> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 Jnet (fo=1, routed)XhV> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/I4 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/OProp_H6LUT_SLICEL_I4_O JLUT6Xhzfe;_> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 Jnet (fo=2, routed)XhW9? eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/I1 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/OProp_E6LUT_SLICEL_I1_O JLUT5Xhzr֣p> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 Jnet (fo=26, routed)Xh? b^g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhE^@X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhGA@X3Y4 (CLOCK_ROOT) a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/C JFDCEXhzr> Jclock pessimismXhi̽>@ Jclock uncertaintyXh  _[g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh A; J arrival timeXhB/ JXh4 JslackXh&A`\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Cb^g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuJ@}A AGAŒE^@GA@A =А=k>&Ai̽>V?O@ |?@lg?l@a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/QProp_DFF_SLICEL_C_Q JFDCEXhzfV> ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] Jnet (fo=2, routed)Xh> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/I2 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzf"y> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 Jnet (fo=1, routed)XhV> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/I4 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/OProp_H6LUT_SLICEL_I4_O JLUT6Xhzfe;_> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 Jnet (fo=2, routed)XhW9? eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/I1 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/OProp_E6LUT_SLICEL_I1_O JLUT5Xhzr֣p> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 Jnet (fo=26, routed)Xh? b^g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhE^@X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhGA@X3Y4 (CLOCK_ROOT) a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/C JFDCEXhzr> Jclock pessimismXhi̽>@ Jclock uncertaintyXh  _[g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]Setup_FFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh A; J arrival timeXhB/ JXh4 JslackXh&A`\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Cb^g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuJ@}A AGAŒE^@GA@A =А=k>&Ai̽>V?O@ |?@lg?l@a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/QProp_DFF_SLICEL_C_Q JFDCEXhzfV> ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] Jnet (fo=2, routed)Xh> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/I2 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzf"y> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 Jnet (fo=1, routed)XhV> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/I4 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/OProp_H6LUT_SLICEL_I4_O JLUT6Xhzfe;_> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 Jnet (fo=2, routed)XhW9? eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/I1 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/OProp_E6LUT_SLICEL_I1_O JLUT5Xhzr֣p> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 Jnet (fo=26, routed)Xh? b^g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhE^@X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhGA@X3Y4 (CLOCK_ROOT) a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/C JFDCEXhzr> Jclock pessimismXhi̽>@ Jclock uncertaintyXh  _[g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh A; J arrival timeXhB/ JXh4 JslackXh&A`\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Cb^g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuJ@}A AGAŒE^@GA@A =А=k>&Ai̽>V?O@ |?@lg?l@a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/QProp_DFF_SLICEL_C_Q JFDCEXhzfV> ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] Jnet (fo=2, routed)Xh> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/I2 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzf"y> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 Jnet (fo=1, routed)XhV> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/I4 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/OProp_H6LUT_SLICEL_I4_O JLUT6Xhzfe;_> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 Jnet (fo=2, routed)XhW9? eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/I1 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/OProp_E6LUT_SLICEL_I1_O JLUT5Xhzr֣p> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 Jnet (fo=26, routed)Xh? b^g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhE^@X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhGA@X3Y4 (CLOCK_ROOT) a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/C JFDCEXhzr> Jclock pessimismXhi̽>@ Jclock uncertaintyXh  _[g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh A; J arrival timeXhB/ JXh4 JslackXh&A`\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Cb^g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuZJ@}AAshAE^@shA@A =А=k>\AĽ>V?V@ |?@lg?P@a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/QProp_DFF_SLICEL_C_Q JFDCEXhzfV> ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] Jnet (fo=2, routed)Xh> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/I2 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzf"y> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 Jnet (fo=1, routed)XhV> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/I4 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/OProp_H6LUT_SLICEL_I4_O JLUT6Xhzfe;_> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 Jnet (fo=2, routed)XhW9? eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/I1 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/OProp_E6LUT_SLICEL_I1_O JLUT5Xhzr֣p> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 Jnet (fo=26, routed)Xh~? b^g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhE^@X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhshA@X3Y4 (CLOCK_ROOT) a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/C JFDCEXhzr> Jclock pessimismXhĽ>@ Jclock uncertaintyXh  _[g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhA; J arrival timeXh~j/ JXh4 JslackXh\A`\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Cb^g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuZJ@}AAshAE^@shA@A =А=k>\AĽ>V?V@ |?@lg?P@a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/QProp_DFF_SLICEL_C_Q JFDCEXhzfV> ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] Jnet (fo=2, routed)Xh> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/I2 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzf"y> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 Jnet (fo=1, routed)XhV> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/I4 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/OProp_H6LUT_SLICEL_I4_O JLUT6Xhzfe;_> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 Jnet (fo=2, routed)XhW9? eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/I1 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/OProp_E6LUT_SLICEL_I1_O JLUT5Xhzr֣p> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 Jnet (fo=26, routed)Xh~? b^g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhE^@X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhshA@X3Y4 (CLOCK_ROOT) a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/C JFDCEXhzr> Jclock pessimismXhĽ>@ Jclock uncertaintyXh  _[g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhA; J arrival timeXh~j/ JXh4 JslackXh\A`\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Ca]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/CE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuZJ@}AAshAE^@shA@A =А=k>\AĽ>V?V@ |?@lg?P@a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/QProp_DFF_SLICEL_C_Q JFDCEXhzfV> ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] Jnet (fo=2, routed)Xh> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/I2 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzf"y> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 Jnet (fo=1, routed)XhV> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/I4 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/OProp_H6LUT_SLICEL_I4_O JLUT6Xhzfe;_> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 Jnet (fo=2, routed)XhW9? eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/I1 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/OProp_E6LUT_SLICEL_I1_O JLUT5Xhzr֣p> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 Jnet (fo=26, routed)Xh~? a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhE^@X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhshA@X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]/C JFDCEXhzr> Jclock pessimismXhĽ>@ Jclock uncertaintyXh  ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[8]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhA; J arrival timeXh~j/ JXh4 JslackXh\A`\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Ca]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[9]/CE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuZJ@}AAshAE^@shA@A =А=k>\AĽ>V?V@ |?@lg?P@a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/QProp_DFF_SLICEL_C_Q JFDCEXhzfV> ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] Jnet (fo=2, routed)Xh> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/I2 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzf"y> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 Jnet (fo=1, routed)XhV> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/I4 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/OProp_H6LUT_SLICEL_I4_O JLUT6Xhzfe;_> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 Jnet (fo=2, routed)XhW9? eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/I1 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/OProp_E6LUT_SLICEL_I1_O JLUT5Xhzr֣p> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 Jnet (fo=26, routed)Xh~? a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[9]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhE^@X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhshA@X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[9]/C JFDCEXhzr> Jclock pessimismXhĽ>@ Jclock uncertaintyXh  ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[9]Setup_BFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhA; J arrival timeXh~j/ JXh4 JslackXh\A`\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/Ca]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1 LUT5=1 LUT6=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuN@}AvAshAE^@shA@A =А=k> AR>V?x@ |?@lg?P@a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})a(rising edge-triggered cell FDCE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})SlowDRPclkDRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/QProp_DFF_SLICEL_C_Q JFDCEXhzfV> ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3] Jnet (fo=2, routed)Xh> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/I2 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzf"y> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_8__27_n_0 Jnet (fo=1, routed)XhV> eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/I4 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24/OProp_H6LUT_SLICEL_I4_O JLUT6Xhzfe;_> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_3__24_n_0 Jnet (fo=2, routed)XhW9? eag_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/I1 JXhzf d`g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27/OProp_E6LUT_SLICEL_I1_O JLUT5Xhzr֣p> fbg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer[0]_i_1__27_n_0 Jnet (fo=26, routed)XhQ? a]g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CE JFDCEXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhE^@X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[3]/C JFDCEXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr FBg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/DRPclk Jnet (fo=3888, routed)XhshA@X3Y4 (CLOCK_ROOT) `\g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/C JFDCEXhzr> Jclock pessimismXhR>@ Jclock uncertaintyXh  ^Zg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhvA; J arrival timeXh/ JXh4 JslackXh A" gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]!)y@1y @9Ay@Iy @ed@hq} )= > rise - rise rise - rise  cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C)%SFP_GEN[0].rx_data_ngccm_reg[0][70]/D"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuS>}/n¿Է=Z?n?)=G*D="=(?V?;/?*?w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_BFF2_SLICEM_C_Q JFDREXhzrD=U rx_data[0][70] Jnet (fo=1, routed)Xh"=[ )%SFP_GEN[0].rx_data_ngccm_reg[0][70]/D JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~??X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[0] Jnet (fo=674, routed)XhO?X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[0].rx_data_ngccm_reg[0][70]/C JFDCEXhzr> Jclock pessimismXhG*r '#SFP_GEN[0].rx_data_ngccm_reg[0][70]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh/; J arrival timeXh'1?/ JXh4 JslackXh)= )%SFP_GEN[0].rx_data_ngccm_reg[0][77]/C/+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[76]/D"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsun>}ҽ,ƿt>W9?,?*==>(?{?;/?2?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR)w )%SFP_GEN[0].rx_data_ngccm_reg[0][77]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[83]_0[69] Jnet (fo=1, routed)Xhx=^ 0,SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[76]_i_1/I0 JXhzr /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[76]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzr/]=t 1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[76]_i_1_n_0 Jnet (fo=1, routed)Xho<a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[76]/D JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[0].rx_data_ngccm_reg[0][77]/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhsh?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[76]/C JFDCEXhzr> Jclock pessimismXhw -)SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[76]Hold_HFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhҽ; J arrival timeXhJ ?/ JXh4 JslackXh*=($SFP_GEN[0].rx_data_ngccm_reg[0][3]/C.*SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[2]/D"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuK>}yƿ=?y?4= , =l=(?i ?;/?G3?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR)v ($SFP_GEN[0].rx_data_ngccm_reg[0][3]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD=u 2.SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[83]_0[3] Jnet (fo=1, routed)Xh`=] /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[2]_i_1/I0 JXhzr~ .*SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[2]_i_1/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr=s 0,SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[2]_i_1_n_0 Jnet (fo=1, routed)XhX94<` .*SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[2]/D JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh/ݔ?X3Y0 (CLOCK_ROOT)Z ($SFP_GEN[0].rx_data_ngccm_reg[0][3]/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhʱ?X3Y0 (CLOCK_ROOT)` .*SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXh ,w ,(SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[2]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhp?/ JXh4 JslackXh4={g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuv>>}_ſW=W9??XZ*=ݢ,=j=(?{?;/? 0?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xhw= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)XhA`e< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXhݢ, g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh_; J arrival timeXh1?/ JXh4 JslackXhXZ*= )%SFP_GEN[0].rx_data_ngccm_reg[0][79]/C/+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[78]/D"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu{?5>}J),ƿ (=K?,?M9= G,E=X9=(?X9?;/?2?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR)v )%SFP_GEN[0].rx_data_ngccm_reg[0][79]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[83]_0[71] Jnet (fo=1, routed)Xh㥛=^ 0,SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[78]_i_1/I0 JXhzr /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[78]_i_1/OProp_H5LUT_SLICEM_I0_O JLUT3Xhzr #=t 1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40[78]_i_1_n_0 Jnet (fo=1, routed)XhD<a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[78]/D JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh'1?X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[0].rx_data_ngccm_reg[0][79]/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhsh?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[78]/C JFDCEXhzr> Jclock pessimismXh G,x -)SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[78]Hold_HFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhJ); J arrival timeXh?/ JXh4 JslackXhM9=&g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsun>}ˡſ>)=?ˡ?;=Y=9H=(?<?;/?&1?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= jfg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/feedbackRegister[0] Jnet (fo=2, routed)XhP= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1/OProp_A6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXhY g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXh;=og_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuz>}ĿK?)=??KC=X=`P=(??;/?=/?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh<߯?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXhX g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh+?/ JXh4 JslackXhKC=,(SFP_GEN[0].ngccm_status_reg_reg[0][23]/C,(SFP_GEN[0].ngccm_status_reg_reg[0][23]/D"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT2=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsui;=}DZĿ֣;k?Z?D=wo=Q8=(??;/?.?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR)y ,(SFP_GEN[0].ngccm_status_reg_reg[0][23]/QProp_AFF_SLICEM_C_Q JFDPEXhzr9H= D@SFP_GEN[0].ngCCM_gbt/SFP_GEN[0].ngccm_status_reg_reg[0][24]_0[7] Jnet (fo=2, routed)Xh+=p B>SFP_GEN[0].ngCCM_gbt/SFP_GEN[0].ngccm_status_reg[0][23]_i_1/I0 JXhzr A=SFP_GEN[0].ngCCM_gbt/SFP_GEN[0].ngccm_status_reg[0][23]_i_1/OProp_A6LUT_SLICEM_I0_O JLUT2Xhzru<R  p_3_out[23] Jnet (fo=1, routed)XhD<^ ,(SFP_GEN[0].ngccm_status_reg_reg[0][23]/D JFDPEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[0] Jnet (fo=674, routed)Xhˡ?X3Y0 (CLOCK_ROOT)^ ,(SFP_GEN[0].ngccm_status_reg_reg[0][23]/C JFDPEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[0] Jnet (fo=674, routed)Xhe;?X3Y0 (CLOCK_ROOT)^ ,(SFP_GEN[0].ngccm_status_reg_reg[0][23]/C JFDPEXhzr> Jclock pessimismXhwt *&SFP_GEN[0].ngccm_status_reg_reg[0][23]Hold_AFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXhD; J arrival timeXh"?/ JXh4 JslackXhD=yg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu0>}glǿn)=b?l? K=5Po==(??;/?l4?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[0] Jnet (fo=2, routed)XhO= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1/OProp_G6LUT_SLICEM_I2_O JLUT3Xhzru< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)XhA`e< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhM?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh5P g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhg; J arrival timeXhH?/ JXh4 JslackXh K=Pmig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Cmig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuS=}Sÿף;F?S?L=wo=@=(?W ?;/?D,?w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fastgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/QProp_AFF_SLICEL_C_Q JFDREXhzr9H= XTg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/timer[5] Jnet (fo=2, routed)Xh)\= qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__0/I0 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__0/OProp_A6LUT_SLICEL_I0_O JLUT6Xhzru< rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__0_n_0 Jnet (fo=1, routed)XhD< mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5?X3Y0 (CLOCK_ROOT) mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzr> Jclock pessimismXhw kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/clkSlipProcess.timer_reg[5]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhL=7!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT4=2 LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu@}AM9AIDj9~z@ID@A=А=d@"7>O?Pw@H?O??G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhA`E@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I0 JXhzf lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrj= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7/I2 JXhzr jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr֣p> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7_n_0 Jnet (fo=1, routed)Xh= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1/I5 JXhzr jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1_n_0 Jnet (fo=2, routed)Xh%? kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh*@X3Y0 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh"7>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhM9A; J arrival timeXht/ JXh4 JslackXhd@ 7!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT4=2 LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu@}AM9AIDj9~z@ID@A=А=d@"7>O?Pw@H?O??G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhA`E@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I0 JXhzf lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzrj= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7/I2 JXhzr jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr֣p> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7_n_0 Jnet (fo=1, routed)Xh= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1/I5 JXhzr jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1_n_0 Jnet (fo=2, routed)Xh%? kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh*@X3Y0 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh"7>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhM9A; J arrival timeXht/ JXh4 JslackXhd@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[0].rx_data_ngccm_reg[0][70]/CE"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuU@}A7AB$Fף@B@A=А=!@8O>(> @H?p@?Χ?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[0].rx_data_ngccm[0][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[0].rx_data_ngccm[0][83]_i_1/OProp_B6LUT_SLICEL_I0_O JLUT6Xhzr)>X rx_data_ngccm[0] Jnet (fo=76, routed)Xh\?\ *&SFP_GEN[0].rx_data_ngccm_reg[0][70]/CE JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[0] Jnet (fo=674, routed)XhG)@X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[0].rx_data_ngccm_reg[0][70]/C JFDCEXhzr> Jclock pessimismXh8O>@ Jclock uncertaintyXht '#SFP_GEN[0].rx_data_ngccm_reg[0][70]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh7A; J arrival timeXhC/ JXh4 JslackXh!@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[0].rx_data_ngccm_reg[0][68]/CE"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuʝ@}AR7AB$Fף@B@A=А=h!@8O>(>1@H?p@?Χ?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[0].rx_data_ngccm[0][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[0].rx_data_ngccm[0][83]_i_1/OProp_B6LUT_SLICEL_I0_O JLUT6Xhzr)>X rx_data_ngccm[0] Jnet (fo=76, routed)Xh-?\ *&SFP_GEN[0].rx_data_ngccm_reg[0][68]/CE JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[0] Jnet (fo=674, routed)XhG)@X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[0].rx_data_ngccm_reg[0][68]/C JFDCEXhzr> Jclock pessimismXh8O>@ Jclock uncertaintyXhs '#SFP_GEN[0].rx_data_ngccm_reg[0][68]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhR7A; J arrival timeXhL7/ JXh4 JslackXhh!@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[0].rx_data_ngccm_reg[0][71]/CE"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuʝ@}AR7AB$Fף@B@A=А=h!@8O>(>1@H?p@?Χ?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[0].rx_data_ngccm[0][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[0].rx_data_ngccm[0][83]_i_1/OProp_B6LUT_SLICEL_I0_O JLUT6Xhzr)>X rx_data_ngccm[0] Jnet (fo=76, routed)Xh-?\ *&SFP_GEN[0].rx_data_ngccm_reg[0][71]/CE JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[0] Jnet (fo=674, routed)XhG)@X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[0].rx_data_ngccm_reg[0][71]/C JFDCEXhzr> Jclock pessimismXh8O>@ Jclock uncertaintyXhs '#SFP_GEN[0].rx_data_ngccm_reg[0][71]Setup_FFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhR7A; J arrival timeXhL7/ JXh4 JslackXhh!@Lwg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT4=1 LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu+@}A08A!Bn~z@!B@A=А=Ǜ"@W>x?q@H?O???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhA`E@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I0 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzfj= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh(> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK7)@X3Y0 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh08A; J arrival timeXh?5/ JXh4 JslackXhǛ"@ wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT4=1 LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu+@}A08A!Bn~z@!B@A=А=Ǜ"@W>x?q@H?O???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhA`E@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I0 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzfj= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh(> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK7)@X3Y0 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_GFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh08A; J arrival timeXh?5/ JXh4 JslackXhǛ"@ vg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT4=1 LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu< @}Az8A!Bn~z@!B@A=А=y#@W>x?Xq@H?O???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhA`E@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I0 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzfj= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK7)@X3Y0 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhz8A; J arrival timeXh$/ JXh4 JslackXhy#@ vg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT4=1 LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu< @}Az8A!Bn~z@!B@A=А=y#@W>x?Xq@H?O???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhA`E@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I0 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzfj= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK7)@X3Y0 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_GFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhz8A; J arrival timeXh$/ JXh4 JslackXhy#@ vg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT4=1 LUT6=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu< @}Az8A!Bn~z@!B@A=А=y#@W>x?Xq@H?O???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})w(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slowgtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhA`E@ mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/I0 JXhzr lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzfj= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__0/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK7)@X3Y0 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_FFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhz8A; J arrival timeXh$/ JXh4 JslackXhy#@ &  gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1!)y@1y @9Ay@Iy @ez@hq} j+= > rise - rise rise - rise  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C*&SFP_GEN[10].rx_data_ngccm_reg[10][4]/D""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsut>}?~j==d?j?j+=#9H=\=̌>>w>S?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_FFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[10][4] Jnet (fo=1, routed)Xh\=\ *&SFP_GEN[10].rx_data_ngccm_reg[10][4]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhTE?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>m RX_WORDCLK_O[10] Jnet (fo=674, routed)Xhn?X4Y3 (CLOCK_ROOT)\ *&SFP_GEN[10].rx_data_ngccm_reg[10][4]/C JFDCEXhzr> Jclock pessimismXh#s ($SFP_GEN[10].rx_data_ngccm_reg[10][4]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh?~; J arrival timeXhz?/ JXh4 JslackXhj+=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuz>}qV.?)=yf?V?LC=s,=`P=̌>M?w>]"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__9/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__9/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh:H?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhnr?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXhs, g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhq; J arrival timeXh?/ JXh4 JslackXhLC=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuMb>}{I=d?I?CM=,=@=̌>?w>v?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__9/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__9/OProp_F6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhgfF?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhVn?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh, g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh{; J arrival timeXhZ?/ JXh4 JslackXhCM=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C+'SFP_GEN[10].rx_data_ngccm_reg[10][53]/D""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu0>}f}1GR'=d?1?3jM=`#9H=9=̌>?w>?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[10][53] Jnet (fo=1, routed)Xh9=] +'SFP_GEN[10].rx_data_ngccm_reg[10][53]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhgfF?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>m RX_WORDCLK_O[10] Jnet (fo=674, routed)Xhm?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[10].rx_data_ngccm_reg[10][53]/C JFDCEXhzr> Jclock pessimismXh`#s )%SFP_GEN[10].rx_data_ngccm_reg[10][53]Hold_GFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhf}; J arrival timeXh?/ JXh4 JslackXh3jM=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuxh>}{I=d?I?.Q=,=D=̌>?w>v?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)XhC = g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__9/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__9/OProp_G6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] Jnet (fo=1, routed)XhA`e< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhgfF?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhVn?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh, g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh{; J arrival timeXhz?/ JXh4 JslackXh.Q=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C*&SFP_GEN[10].rx_data_ngccm_reg[10][7]/D""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu,>}?~j==d?j?`T=#D==̌>>w>S?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_EFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[10][7] Jnet (fo=1, routed)Xh=\ *&SFP_GEN[10].rx_data_ngccm_reg[10][7]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhTE?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>m RX_WORDCLK_O[10] Jnet (fo=674, routed)Xhn?X4Y3 (CLOCK_ROOT)\ *&SFP_GEN[10].rx_data_ngccm_reg[10][7]/C JFDCEXhzr> Jclock pessimismXh#r ($SFP_GEN[10].rx_data_ngccm_reg[10][7]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh?~; J arrival timeXh…?/ JXh4 JslackXh`T=2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/Ckgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/D""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsul=}Nb񒿭)ף;&q??T=Mo=9H=̌>E ?w>+?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/QProp_BFF_SLICEL_C_Q JFDCEXhzf9H= TPg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/Q[1] Jnet (fo=9, routed)XhP= qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[0]_i_1__9/I0 JXhzf plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[0]_i_1__9/OProp_A6LUT_SLICEL_I0_O JLUT6Xhzru< RNg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/D[0] Jnet (fo=1, routed)XhD< kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhR?X4Y3 (CLOCK_ROOT) kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{?X4Y3 (CLOCK_ROOT) kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhM ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhNb; J arrival timeXh= ?/ JXh4 JslackXhT= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/bitSlipCmd_reg/C^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/D""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuL`=}أ]F;q?]?T=O ?w>+?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/bitSlipCmd_reg/QProp_HFF_SLICEL_C_Q JFDCEXhzfD= plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/bitSlipCmd_to_bitSlipCtrller_10 Jnet (fo=10, routed)Xh)\= b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_i_1__9/I0 JXhzf a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_i_1__9/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzru< c_g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_i_1__9_n_0 Jnet (fo=1, routed)XhA`e< ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhFS?X4Y3 (CLOCK_ROOT) ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/bitSlipCmd_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhIz?X4Y3 (CLOCK_ROOT) ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXh}qV.?)=yf?V?W=s,=j<=̌>M?w>]"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__9/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__9/OProp_C5LUT_SLICEM_I0_O JLUT3XhzrGa= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)XhX94< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh:H?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhnr?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr> Jclock pessimismXhs, g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[15]Hold_CFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhq; J arrival timeXh?/ JXh4 JslackXhW=l>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/D""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsux=}Nbo)ף;&q?o?Y=No=L=̌>E ?w>1,?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt_reg[10][7]_0[7] Jnet (fo=5, routed)Xh)\= sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt[10][7]_i_2/I4 JXhzr rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gbtBank_Clk_gen[10].cnt[10][7]_i_2/OProp_B6LUT_SLICEL_I4_O JLUT6Xhzru<m *&g_gbt_bank[0].gbtbank/i_gbt_bank_n_354 Jnet (fo=1, routed)Xhu<p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)XhR?X4Y3 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xhl{?X4Y3 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C JFDCEXhzr> Jclock pessimismXhN <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhNb; J arrival timeXh+?/ JXh4 JslackXhY=!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu#ۉ@}A,A-0ϸ$@-@A=А=z@{k>n?-*@!?l? ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I3 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh)\> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9/I2 JXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9/OProp_B5LUT_SLICEL_I2_O JLUT4XhzrC> plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9_n_0 Jnet (fo=1, routed)Xhrh> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9/I5 JXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9_n_0 Jnet (fo=2, routed)Xh > lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhff@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X4Y3 (CLOCK_ROOT) kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh{k>@ Jclock uncertaintyXh ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh,A; J arrival timeXhA/ JXh4 JslackXhz@ !g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu#ۉ@}A,A-0ϸ$@-@A=А=z@{k>n?-*@!?l? ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I3 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh)\> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9/I2 JXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9/OProp_B5LUT_SLICEL_I2_O JLUT4XhzrC> plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__9_n_0 Jnet (fo=1, routed)Xhrh> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9/I5 JXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__9_n_0 Jnet (fo=2, routed)Xh > lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhff@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X4Y3 (CLOCK_ROOT) kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh{k>@ Jclock uncertaintyXh ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]Setup_BFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh,A; J arrival timeXhA/ JXh4 JslackXhz@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[10].rx_data_ngccm_reg[10][77]/CE""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsut@}Ap*A$y$1@$@A=А=@!Y>n>!b@!?Z? ??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr>Y rx_data_ngccm[10] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[10].rx_data_ngccm_reg[10][77]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>m RX_WORDCLK_O[10] Jnet (fo=674, routed)XhX?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[10].rx_data_ngccm_reg[10][77]/C JFDCEXhzr> Jclock pessimismXh!Y>@ Jclock uncertaintyXhu )%SFP_GEN[10].rx_data_ngccm_reg[10][77]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhp*A; J arrival timeXh / JXh4 JslackXh@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuG@}A,A-0ϸ$@-@A=А=@{k>?{.@!?l? ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I3 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh$> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/I5 JXhzr zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/OProp_F6LUT_SLICEL_I5_O JLUT6XhzrQ= a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh(> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhff@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X4Y3 (CLOCK_ROOT) vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh{k>@ Jclock uncertaintyXh tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu&@}Aͽ,A-0ϸ$@-@A=А=J@{k>?-@!?l? ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I3 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh$> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/I5 JXhzr zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/OProp_F6LUT_SLICEL_I5_O JLUT6XhzrQ= a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhff@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X4Y3 (CLOCK_ROOT) vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh{k>@ Jclock uncertaintyXh tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhͽ,A; J arrival timeXhP/ JXh4 JslackXhJ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu&@}Aͽ,A-0ϸ$@-@A=А=J@{k>?-@!?l? ??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh? qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/I3 JXhzr plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__9/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh$> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/I5 JXhzr zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__10/OProp_F6LUT_SLICEL_I5_O JLUT6XhzrQ= a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhff@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X4Y3 (CLOCK_ROOT) vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh{k>@ Jclock uncertaintyXh tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhͽ,A; J arrival timeXhP/ JXh4 JslackXhJ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[10].rx_data_ngccm_reg[10][69]/CE""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuZ9l@}AA*AE3v$1@E@A=А=v@Y>n>Y@!?Z? ?A?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr>Y rx_data_ngccm[10] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[10].rx_data_ngccm_reg[10][69]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>m RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[10].rx_data_ngccm_reg[10][69]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXhv )%SFP_GEN[10].rx_data_ngccm_reg[10][69]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhA*A; J arrival timeXh/ JXh4 JslackXhv@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[10].rx_data_ngccm_reg[10][71]/CE""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuZ9l@}AA*AE3v$1@E@A=А=v@Y>n>Y@!?Z? ?A?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr>Y rx_data_ngccm[10] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[10].rx_data_ngccm_reg[10][71]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>m RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[10].rx_data_ngccm_reg[10][71]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXhv )%SFP_GEN[10].rx_data_ngccm_reg[10][71]Setup_FFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhA*A; J arrival timeXh/ JXh4 JslackXhv@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[10].rx_data_ngccm_reg[10][73]/CE""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuZ9l@}AA*AE3v$1@E@A=А=v@Y>n>Y@!?Z? ?A?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr>Y rx_data_ngccm[10] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[10].rx_data_ngccm_reg[10][73]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>m RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[10].rx_data_ngccm_reg[10][73]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXhv )%SFP_GEN[10].rx_data_ngccm_reg[10][73]Setup_GFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhA*A; J arrival timeXh/ JXh4 JslackXhv@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[10].rx_data_ngccm_reg[10][75]/CE""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuZ9l@}AA*AE3v$1@E@A=А=v@Y>n>Y@!?Z? ?A?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/I0 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/SFP_GEN[10].rx_data_ngccm[10][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr>Y rx_data_ngccm[10] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[10].rx_data_ngccm_reg[10][75]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>m RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[10].rx_data_ngccm_reg[10][75]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXhv )%SFP_GEN[10].rx_data_ngccm_reg[10][75]Setup_HFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhA*A; J arrival timeXh/ JXh4 JslackXhv@L( !gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!)y@1y @9Ay@Iy @ef@hq} N= > rise - rise rise - rise  ~g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C)%SFP_GEN[8].rx_data_ngccm_reg[8][68]/D"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu+$>}Ņ=k??N=9H=A`=̌>y?Ġ>#?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=U rx_data[8][68] Jnet (fo=1, routed)XhA`=[ )%SFP_GEN[8].rx_data_ngccm_reg[8][68]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhOM?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[8] Jnet (fo=674, routed)Xhs?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[8].rx_data_ngccm_reg[8][68]/C JFDCEXhzr> Jclock pessimismXhq '#SFP_GEN[8].rx_data_ngccm_reg[8][68]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhŅ; J arrival timeXh5^?/ JXh4 JslackXhN=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsun>}Đo,=q=j?Đ?`7=1v=L=̌>ˡ?Ġ>z&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)XhC = g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__7/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__7/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh2L?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhKw?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh1 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXh`7={g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C($SFP_GEN[8].rx_data_ngccm_reg[8][7]/D"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu)>}V5)= k?V?<8=XD==̌>gf?Ġ>J "?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_CFF2_SLICEM_C_Q JFDREXhzrD=T  rx_data[8][7] Jnet (fo=1, routed)Xh=Z ($SFP_GEN[8].rx_data_ngccm_reg[8][7]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[8] Jnet (fo=674, routed)Xhnr?X4Y3 (CLOCK_ROOT)Z ($SFP_GEN[8].rx_data_ngccm_reg[8][7]/C JFDCEXhzr> Jclock pessimismXhXq &"SFP_GEN[8].rx_data_ngccm_reg[8][7]Hold_GFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh<8=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuV>}oNb~= k?Nb?ay;=0v=j<=̌>gf?Ġ>$&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)XhC = g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__7/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__7/OProp_F6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh+v?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh0 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXho; J arrival timeXhK?/ JXh4 JslackXhay;=%)%SFP_GEN[8].rx_data_ngccm_reg[8][53]/C/+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[52]/D"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu|.>}aRX= k?R?@<=ʡ=5^=̌>gf?Ġ>"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR)v )%SFP_GEN[8].rx_data_ngccm_reg[8][53]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[83]_0[45] Jnet (fo=1, routed)Xh=^ 0,SFP_GEN[8].ngCCM_gbt/RX_Word_rx40[52]_i_1/I0 JXhzr /+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40[52]_i_1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzr<t 1-SFP_GEN[8].ngCCM_gbt/RX_Word_rx40[52]_i_1_n_0 Jnet (fo=1, routed)Xho<a /+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[52]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[8] Jnet (fo=674, routed)XhL?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[8].rx_data_ngccm_reg[8][53]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33s?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr> Jclock pessimismXhw -)SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[52]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXha; J arrival timeXhC?/ JXh4 JslackXh@<=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C)%SFP_GEN[8].rx_data_ngccm_reg[8][79]/D"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsun>}%'=^i??@=#D=[=̌>?Ġ>\"?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=U rx_data[8][79] Jnet (fo=1, routed)Xh[=[ )%SFP_GEN[8].rx_data_ngccm_reg[8][79]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhK?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[8] Jnet (fo=674, routed)Xhr?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[8].rx_data_ngccm_reg[8][79]/C JFDCEXhzr> Jclock pessimismXh#r '#SFP_GEN[8].rx_data_ngccm_reg[8][79]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh%; J arrival timeXh+?/ JXh4 JslackXh@=_[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress_reg[1]/C]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd_reg/D"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu>}x{7C=yf?{?A=,0$%=X9=̌>M?Ġ>7!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress_reg[1]/QProp_CFF_SLICEL_C_Q JFDCEXhzfD= YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress[1] Jnet (fo=8, routed)Xht= a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd_i_1__7/I4 JXhzf `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd_i_1__7/OProp_D6LUT_SLICEL_I4_O JLUT6Xhzru< WSg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd Jnet (fo=1, routed)Xho< ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh:H?X4Y3 (CLOCK_ROOT) _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhq?X4Y3 (CLOCK_ROOT) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd_reg/C JFDCEXhzr> Jclock pessimismXh,0$ [Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/bitSlipCmd_regHold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhx; J arrival timeXhȆ?/ JXh4 JslackXhA=/+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]/C+'SFP_GEN[8].ngCCM_gbt/pwr_good_pre_reg/D"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuE6>}x(|Ǘ= k?|?U(D=D=>̌>gf?Ġ>Z$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR)} /+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrD= <8SFP_GEN[8].ngCCM_gbt/GBT_Word_to_ngCCM_Pins_bkp_pwr_good Jnet (fo=3, routed)Xh>] +'SFP_GEN[8].ngCCM_gbt/pwr_good_pre_reg/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 73SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[8].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhkt?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[8].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhs )%SFP_GEN[8].ngCCM_gbt/pwr_good_pre_regHold_EFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhx(; J arrival timeXhI?/ JXh4 JslackXhU(D=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu&1>}jm=k??Q`H=-= =̌>y?Ġ>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[1] Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__7/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__7/OProp_C5LUT_SLICEL_I2_O JLUT3Xhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[18] Jnet (fo=1, routed)XhX94< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhOM?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhFs?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhj; J arrival timeXhm?/ JXh4 JslackXhQ`H=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C)%SFP_GEN[8].rx_data_ngccm_reg[8][72]/D"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu,>}vȁjH=:h??H=d#D==̌>?Ġ>#?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[8][72] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[8].rx_data_ngccm_reg[8][72]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~J?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[8] Jnet (fo=674, routed)Xhs?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[8].rx_data_ngccm_reg[8][72]/C JFDCEXhzr> Jclock pessimismXhd#q '#SFP_GEN[8].rx_data_ngccm_reg[8][72]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhvȁ; J arrival timeXhb?/ JXh4 JslackXhH=w!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuT@}A*AN<%)@@A=А=f@mZ>v?C<@I "?Y9?n?n?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhG= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr+> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7_n_0 Jnet (fo=1, routed)Xh^> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7/OProp_H6LUT_SLICEL_I5_O JLUT6XhzrE= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7_n_0 Jnet (fo=2, routed)XhG> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhI?X4Y3 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhmZ>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh*A; J arrival timeXhgf/ JXh4 JslackXhf@ w!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsun@}A*A;%)@@A=А=v@LkZ>v?ʡ-@I "?Y9?n?33?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhG= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr+> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__7_n_0 Jnet (fo=1, routed)Xh^> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7/OProp_H6LUT_SLICEL_I5_O JLUT6XhzrE= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__7_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X4Y3 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhLkZ>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhv@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu@}A=*Ay @G%)@y@A=А=x@Z>Ȧ?6@I "?Y9?n??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS= wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhq=*? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh=*A; J arrival timeXh/ JXh4 JslackXhx@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu0݄@}AU*Ay @G%)@y@A=А=hx@Z>Ȧ?V6@I "?Y9?n??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS= wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhL7)? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhU*A; J arrival timeXhB`/ JXh4 JslackXhhx@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu0݄@}AU*Ay @G%)@y@A=А=hx@Z>Ȧ?V6@I "?Y9?n??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS= wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhL7)? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhU*A; J arrival timeXhB`/ JXh4 JslackXhhx@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuD@}A+AA1%)@A@A=А=@SZ>n?O'@I "?Y9?n?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhe;= yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__8/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__8/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh/> vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhh?X4Y3 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhSZ>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh+A; J arrival timeXhW/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu~j@}Ae+AA1%)@A@A=А=8I@SZ>n?K'@I "?Y9?n?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhe;= yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__8/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__8/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh"> vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhh?X4Y3 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhSZ>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhe+A; J arrival timeXh/ JXh4 JslackXh8I@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu~j@}Ae+AA1%)@A@A=А=8I@SZ>n?K'@I "?Y9?n?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhe;= yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__8/I5 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__8/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh"> vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhh?X4Y3 (CLOCK_ROOT) uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhSZ>@ Jclock uncertaintyXh sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhe+A; J arrival timeXh/ JXh4 JslackXh8I@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuA@}A#+ANb/%)@Nb@A=А=d@uNZ>Ȧ?-@I "?Y9?n??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS= wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhZ? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhuNZ>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh#+A; J arrival timeXh/ JXh4 JslackXhd@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuA@}A#+ANb/%)@Nb@A=А=d@uNZ>Ȧ?-@I "?Y9?n??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__7/OProp_D6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS= wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__8/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhZ? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhuNZ>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_BFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh#+A; J arrival timeXh/ JXh4 JslackXhd@ ( !gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!)y@1y @9Ay@Iy @e@hq} ]= > rise - rise rise - rise  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C)%SFP_GEN[9].rx_data_ngccm_reg[9][76]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsun>}َq^=yf?َ?]=c#D=\=I>]?A>S#?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=U rx_data[9][76] Jnet (fo=1, routed)Xh\=[ )%SFP_GEN[9].rx_data_ngccm_reg[9][76]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh:H?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[9] Jnet (fo=674, routed)Xhts?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][76]/C JFDCEXhzr> Jclock pessimismXhc#r '#SFP_GEN[9].rx_data_ngccm_reg[9][76]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh…?/ JXh4 JslackXh]=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu/>}d;-g=+g?d;?:*=c#=`P=I>?A>$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__8/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__8/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr/]= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[0] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhH?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9t?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXhc# g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhK?/ JXh4 JslackXh:*=}g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C)%SFP_GEN[9].rx_data_ngccm_reg[9][44]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuY%>}jR0(~=d?R?4=#9H=l=I>A?A>n#?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=U rx_data[9][44] Jnet (fo=1, routed)Xhl=[ )%SFP_GEN[9].rx_data_ngccm_reg[9][44]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhgfF?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh33s?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][44]/C JFDCEXhzr> Jclock pessimismXh#q '#SFP_GEN[9].rx_data_ngccm_reg[9][44]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhj; J arrival timeXh> ?/ JXh4 JslackXh4=~g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C)%SFP_GEN[9].rx_data_ngccm_reg[9][48]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuUb>}k1%='1h??!7=.D=v=I> ?A> #?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_FFF2_SLICEM_C_Q JFDREXhzrD=U rx_data[9][48] Jnet (fo=1, routed)Xhv=[ )%SFP_GEN[9].rx_data_ngccm_reg[9][48]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhI?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[9] Jnet (fo=674, routed)Xhs?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][48]/C JFDCEXhzr> Jclock pessimismXh.r '#SFP_GEN[9].rx_data_ngccm_reg[9][48]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhk; J arrival timeXh$?/ JXh4 JslackXh!7=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu'>}V2=c?V?{8=# ף=1=I>v>A>M"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)XhC= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__8/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__8/OProp_H6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhB`E?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhnr?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXh# g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhȆ?/ JXh4 JslackXh{8=#)%SFP_GEN[9].rx_data_ngccm_reg[9][44]/C/+SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsut>}I`,=lg??Dy;=x/=L=I>o?A> #?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR)v )%SFP_GEN[9].rx_data_ngccm_reg[9][44]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[83]_0[36] Jnet (fo=1, routed)XhC =^ 0,SFP_GEN[9].ngCCM_gbt/RX_Word_rx40[44]_i_1/I1 JXhzr /+SFP_GEN[9].ngCCM_gbt/RX_Word_rx40[44]_i_1/OProp_D6LUT_SLICEL_I1_O JLUT3XhzrQ8=t 1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40[44]_i_1_n_0 Jnet (fo=1, routed)Xho<a /+SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[9] Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][44]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhs?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/C JFDCEXhzr> Jclock pessimismXhx/w -)SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhI; J arrival timeXh$?/ JXh4 JslackXhDy;=.sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuxi>}vS:>A`e?S?;=%x=x=I>$?A>I,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] Jnet (fo=29, routed)Xh= ieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[36]_i_1__4/I2 JXhzr hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[36]_i_1__4/OProp_B6LUT_SLICEM_I2_O JLUT5Xhzr= `\g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg00[36] Jnet (fo=1, routed)Xhu< eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh+G?X4Y3 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhj|?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]/C JFDCEXhzr> Jclock pessimismXh% c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[36]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhv; J arrival timeXh;ߏ?/ JXh4 JslackXh;=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[33]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[33]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsun>}E둿'=*\o??c<='9H==I>  ?A>x)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[33]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[33] Jnet (fo=1, routed)Xh= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[33]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh&Q?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[33]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhy?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[33]/C JFDCEXhzr> Jclock pessimismXh' c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[33]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhE; J arrival timeXh?/ JXh4 JslackXhc<=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C)%SFP_GEN[9].rx_data_ngccm_reg[9][77]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuO>}َ3 W=lg?َ?v>=S#9H==I>o?A>S#?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=U rx_data[9][77] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[9].rx_data_ngccm_reg[9][77]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[9] Jnet (fo=674, routed)Xhts?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][77]/C JFDCEXhzr> Jclock pessimismXhS#q '#SFP_GEN[9].rx_data_ngccm_reg[9][77]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhP?/ JXh4 JslackXhv>=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu>}vo,=gff?v?_C=Q.=T=I>I ?A>\"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xht= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__8/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__8/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1H?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh!r?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhQ. g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhT?/ JXh4 JslackXh_C=g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[67]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu,}@}A".AZhP'@Z@A=А=@b>d;?{6@!?sh?n?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[7]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[7] J GTHE3_CHANNELXhzrd;? [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[7] Jnet (fo=6, routed)Xh{6@ eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[67]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh& @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[67]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[67]Setup_BFF_SLICEL_C_D JFDCEXh}=/ JXh< J required timeXh".A; J arrival timeXh/ JXh4 JslackXh@ "eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[92]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT4=1 LUT6=3)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuo@}AG,A0}p-@@A=А=К@Y>7a?l7@!?/?n?rh?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[92]/QProp_CFF2_SLICEL_C_Q JFDCEXhzrV> plg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxencdata_s[9]_53[27] Jnet (fo=9, routed)XhA`> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___77_i_3__8/I1 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___77_i_3__8/OProp_F6LUT_SLICEL_I1_O JLUT6XhzrMb> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___77_i_3__8_n_0 Jnet (fo=1, routed)Xhy&? g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___77_i_2__8/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___77_i_2__8/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrZd> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[92]_0[1] Jnet (fo=49, routed)Xh^? okg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_3__8/I2 JXhzr njg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_3__8/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzrx> plg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_3__8_n_0 Jnet (fo=1, routed)Xh)\> xtg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__18/I2 JXhzr wsg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__18/OProp_H6LUT_SLICEM_I2_O JLUT6XhzrGa= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg_3 Jnet (fo=1, routed)Xh*\= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh= @X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[92]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/CLK Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C JFDREXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_regSetup_HFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXhG,A; J arrival timeXh/ JXh4 JslackXhК@1g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[87]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu33s@}AiC.AxP'@@A=А=&@b>d;?+@!?sh?n?p?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[7]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[7] J GTHE3_CHANNELXhzrd;? [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[7] Jnet (fo=6, routed)Xh+@ eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[87]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh& @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[87]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[87]Setup_DFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXhiC.A; J arrival timeXhA`/ JXh4 JslackXh&@g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[9].rx_data_ngccm_reg[9][63]/CE"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu/]@}A*A3V.@@A=А=؏@-PY>>J@!??n?I ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhNb? uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[9] Jnet (fo=76, routed)Xh?\ *&SFP_GEN[9].rx_data_ngccm_reg[9][63]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[9] Jnet (fo=674, routed)XhC?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][63]/C JFDCEXhzr> Jclock pessimismXh-PY>@ Jclock uncertaintyXhs '#SFP_GEN[9].rx_data_ngccm_reg[9][63]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXh؏@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[9].rx_data_ngccm_reg[9][69]/CE"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsup=Z@}A~+A V.@ @A=А=Bӑ@=&Y>>H@!??n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhNb? uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[9] Jnet (fo=76, routed)Xh?\ *&SFP_GEN[9].rx_data_ngccm_reg[9][69]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[9] Jnet (fo=674, routed)XhO?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][69]/C JFDCEXhzr> Jclock pessimismXh=&Y>@ Jclock uncertaintyXht '#SFP_GEN[9].rx_data_ngccm_reg[9][69]Setup_AFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh~+A; J arrival timeXhI/ JXh4 JslackXhBӑ@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[9].rx_data_ngccm_reg[9][68]/CE"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuJ Z@}A+A V.@ @A=А=@=&Y>>G@!??n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhNb? uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[9] Jnet (fo=76, routed)Xhe;?\ *&SFP_GEN[9].rx_data_ngccm_reg[9][68]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[9] Jnet (fo=674, routed)XhO?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][68]/C JFDCEXhzr> Jclock pessimismXh=&Y>@ Jclock uncertaintyXhs '#SFP_GEN[9].rx_data_ngccm_reg[9][68]Setup_AFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh+A; J arrival timeXh'1/ JXh4 JslackXh@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[9].rx_data_ngccm_reg[9][70]/CE"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuJ Z@}A+A V.@ @A=А=@=&Y>>G@!??n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhNb? uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[9] Jnet (fo=76, routed)Xhe;?\ *&SFP_GEN[9].rx_data_ngccm_reg[9][70]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[9] Jnet (fo=674, routed)XhO?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][70]/C JFDCEXhzr> Jclock pessimismXh=&Y>@ Jclock uncertaintyXhs '#SFP_GEN[9].rx_data_ngccm_reg[9][70]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh+A; J arrival timeXh'1/ JXh4 JslackXh@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[7]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuf@}Aڑ,A|5P'@@A=А=@Y>d;?+@!?sh?n?$?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[7]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[7] J GTHE3_CHANNELXhzrd;? [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[7] Jnet (fo=6, routed)Xh+@ d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[7]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh& @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhp=?X4Y3 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[7]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh b^g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[7]Setup_CFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXhڑ,A; J arrival timeXh+/ JXh4 JslackXh@D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C40g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]/D"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuzd@}Aa@-A&nWX9,@&@A=А=&@rUY>$>FK@!??n?$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\>k &"SFP_GEN[9].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xhx@x JFSFP_GEN[9].ngCCM_gbt/g_clock_rate_din[9].ngccm_status_cnt[9][5]_i_1/I2 JXhzr IESFP_GEN[9].ngCCM_gbt/g_clock_rate_din[9].ngccm_status_cnt[9][5]_i_1/OProp_G5LUT_SLICEM_I2_O JLUT4Xhzr|>a SFP_GEN[9].ngCCM_gbt_n_412 Jnet (fo=1, routed)XhH?f 40g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh @X4Y3 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh(\?X4Y3 (CLOCK_ROOT)f 40g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]/C JFDREXhzr> Jclock pessimismXhrUY>@ Jclock uncertaintyXh~ 2.g_clock_rate_din[9].ngccm_status_cnt_reg[9][5]Setup_CFF2_SLICEM_C_D JFDREXh+=/ JXh< J required timeXha@-A; J arrival timeXhZ/ JXh4 JslackXh&@g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[9].rx_data_ngccm_reg[9][58]/CE"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu6Y@}A~+A V.@ @A=А=_-@=&Y>>KG@!??n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhNb? uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[9].rx_data_ngccm[9][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[9] Jnet (fo=76, routed)Xh@5?\ *&SFP_GEN[9].rx_data_ngccm_reg[9][58]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[9] Jnet (fo=674, routed)XhO?X4Y3 (CLOCK_ROOT)[ )%SFP_GEN[9].rx_data_ngccm_reg[9][58]/C JFDCEXhzr> Jclock pessimismXh=&Y>@ Jclock uncertaintyXht '#SFP_GEN[9].rx_data_ngccm_reg[9][58]Setup_AFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh~+A; J arrival timeXh/ JXh4 JslackXh_-@L&  gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2!)y@1y @9Ay@Iy @eH@hq} *\= > rise - rise rise - rise  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuu>}󍿍8t>lg?8?*\=3`=O >̌>?w>(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)Xh"= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__10/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__10/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrY= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh3 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh󍿐; J arrival timeXhn?/ JXh4 JslackXh*\=fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[39]/Cfbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[39]/D"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuv>}Px>ts?P?t=3D=ˡE>̌>?w>4?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[39]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= `\g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[39] Jnet (fo=1, routed)XhˡE> fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[39]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh}?U?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[39]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhn?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[39]/C JFDCEXhzr> Jclock pessimismXh3 d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[39]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhu?/ JXh4 JslackXht=j0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[23]/CGCSFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/D"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuk>}p%o= >i?%?~=39H=X9>̌>B`?w>'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR)} 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[23]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=p -)SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/Q[7] Jnet (fo=5, routed)XhX9>y GCSFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/D JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[11].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[11].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X4Y3 (CLOCK_ROOT)y GCSFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]/C JFDREXhzr> Jclock pessimismXh3 EASFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[7]Hold_GFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhp; J arrival timeXhn?/ JXh4 JslackXh~=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C+'SFP_GEN[11].rx_data_ngccm_reg[11][34]/D"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuD>}"ۉp=Dl?p?=3D=t>̌>?w> ?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_HFF_SLICEL_C_Q JFDREXhzrD=V rx_data[11][34] Jnet (fo=1, routed)Xht>] +'SFP_GEN[11].rx_data_ngccm_reg[11][34]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhVN?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>m RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh֣p?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[11].rx_data_ngccm_reg[11][34]/C JFDCEXhzr> Jclock pessimismXh3s )%SFP_GEN[11].rx_data_ngccm_reg[11][34]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh"ۉ; J arrival timeXhَ?/ JXh4 JslackXh=fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[23]/Cfbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]/D"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuK7>}R'$=zt?$?=jD 9H=>̌>;?w>-2?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[23]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= `\g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[23] Jnet (fo=1, routed)Xh> fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[23]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh%?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]/C JFDCEXhzr> Jclock pessimismXhjD  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhR'; J arrival timeXh&?/ JXh4 JslackXh=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuEz>}󍿍8t>lg?8? #=3A`='1>̌>?w>(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)Xh"= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__10/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__10/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr%= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[6] Jnet (fo=1, routed)XhX94< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXh3 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh󍿐; J arrival timeXho?/ JXh4 JslackXh #=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuw>}i& >lg?&? #=3F=l=̌>?w>)1(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xhe;= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__10/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__10/OProp_G6LUT_SLICEL_I2_O JLUT3Xhzr)\= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)XhA`e< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhdx?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh3 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhi; J arrival timeXh!?/ JXh4 JslackXh #=fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[54]/Cfbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[54]/D"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuأp>} EI >s?E?D,=3D=|?>̌>*\?w>n2?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[54]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= `\g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[54] Jnet (fo=1, routed)Xh|?> fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[54]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhU?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[54]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh&?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[54]/C JFDCEXhzr> Jclock pessimismXh3 d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[54]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh ; J arrival timeXhc?/ JXh4 JslackXhD,=Vg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu(>} Ĉ=im? ?,=^v=-=̌>?w>$&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD= kgg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/feedbackRegister[1] Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[20]_i_2__10/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[20]_i_2__10/OProp_F6LUT_SLICEL_I0_O JLUT3Xhzr< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh)\O?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhv?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXh^ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhm?/ JXh4 JslackXh,=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[11].rx_data_ngccm_reg[11][39]/D"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuϡE>}"ۉpv=im?p?}94=3D=z>̌>?w> ?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[11][39] Jnet (fo=1, routed)Xhz>] +'SFP_GEN[11].rx_data_ngccm_reg[11][39]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh)\O?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>m RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh֣p?X4Y3 (CLOCK_ROOT)] +'SFP_GEN[11].rx_data_ngccm_reg[11][39]/C JFDCEXhzr> Jclock pessimismXh3t )%SFP_GEN[11].rx_data_ngccm_reg[11][39]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh"ۉ; J arrival timeXh|?/ JXh4 JslackXh}94=!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu@}A+Ar21)@r@A=А=H@C >}??GJ@G!?T?-?/ݴ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh@ rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I2 JXhzr qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh&> plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrA`e> qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10_n_0 Jnet (fo=1, routed)Xhʡ= plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10/I5 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr1,> qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10_n_0 Jnet (fo=2, routed)Xh#? lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhH@ !g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu@}A+Ar21)@r@A=А=H@C >}??GJ@G!?T?-?/ݴ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh@ rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I2 JXhzr qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh&> plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10/I2 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrA`e> qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__10_n_0 Jnet (fo=1, routed)Xhʡ= plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10/I5 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr1,> qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__10_n_0 Jnet (fo=2, routed)Xh#? lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhH@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuK@}A8+A+)@+@A=А=T]@C >?>@G!?T?-?M?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh@ rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I2 JXhzr qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/I3 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhQ? uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhYd?X4Y3 (CLOCK_ROOT) tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh8+A; J arrival timeXh / JXh4 JslackXhT]@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu43@}A+A+)@+@A=А=U^@C >?gf>@G!?T?-?M?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh@ rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I2 JXhzr qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/I3 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhP? uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhYd?X4Y3 (CLOCK_ROOT) tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh+A; J arrival timeXh3/ JXh4 JslackXhU^@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuz@}A+Awt)@w@A=А=(d@C >sh?A8@G!?T?-?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh@ rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I2 JXhzr qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^:> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__11/I5 JXhzr zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__11/OProp_B6LUT_SLICEL_I5_O JLUT6Xhzr!r> a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)XhK? wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X4Y3 (CLOCK_ROOT) vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh+A; J arrival timeXhO/ JXh4 JslackXh(d@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuOb@}A`+Awt)@w@A=А=d@C >sh?b8@G!?T?-?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh@ rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I2 JXhzr qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^:> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__11/I5 JXhzr zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__11/OProp_B6LUT_SLICEL_I5_O JLUT6Xhzr!r> a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh+? wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X4Y3 (CLOCK_ROOT) vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh`+A; J arrival timeXhM7/ JXh4 JslackXhd@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuM@}A+Az)@@A=А=Qrh@C >?4@G!?T?-?S?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh@ rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I2 JXhzr qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/I3 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~j?X4Y3 (CLOCK_ROOT) tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh+A; J arrival timeXh"/ JXh4 JslackXhQrh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuA5@}AG+Az)@@A=А=h@C >?j4@G!?T?-?S?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh@ rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I2 JXhzr qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/I3 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhd;> uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~j?X4Y3 (CLOCK_ROOT) tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhG+A; J arrival timeXh? / JXh4 JslackXhh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuA5@}AG+Az)@@A=А=h@C >?j4@G!?T?-?S?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh@ rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I2 JXhzr qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/I3 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhd;> uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~j?X4Y3 (CLOCK_ROOT) tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhG+A; J arrival timeXh? / JXh4 JslackXhh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuo@}A+AAC )@A@A=А=|o@C >?$.@G!?T?-?z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh@ rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/I2 JXhzr qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__10/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/I3 JXhzr xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__11/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrlg> _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhV> uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC @X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhi?X4Y3 (CLOCK_ROOT) tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh+A; J arrival timeXhm/ JXh4 JslackXh|o@ &  gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3!)y@1y @9Ay@Iy @eE?hq} = > rise - rise rise - rise  sg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C)%SFP_GEN[1].rx_data_ngccm_reg[1][69]/D""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuUb>}Ngſ+[=B`??=!2LD=v=(?Nb?/?1?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[1][69] Jnet (fo=1, routed)Xhv=[ )%SFP_GEN[1].rx_data_ngccm_reg[1][69]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhE?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[1] Jnet (fo=674, routed)Xhף?X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][69]/C JFDCEXhzr> Jclock pessimismXh!2Lr '#SFP_GEN[1].rx_data_ngccm_reg[1][69]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhNg; J arrival timeXhl?/ JXh4 JslackXh=sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]/D""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu{?5>}1뵿Y9Ŀö=S?Y9?=H+v==(?I ?/?.?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_GFF_SLICEM_C_Q JFDCEXhzfD= qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)Xh-= fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[35]_i_1/I1 JXhzf eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[35]_i_1/OProp_E6LUT_SLICEL_I1_O JLUT5Xhzr< `\g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg00[35] Jnet (fo=1, routed)XhD< eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhX9?X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]/C JFDCEXhzr> Jclock pessimismXhH+ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[35]Hold_EFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh1뵿; J arrival timeXh?/ JXh4 JslackXh=sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]/D""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuE6>}1뵿Y9Ŀö=S?Y9?^/=H+v==(?I ?/?.?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_GFF_SLICEM_C_Q JFDCEXhzfD= qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)XhX9= fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[34]_i_1/I1 JXhzf eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[34]_i_1/OProp_F6LUT_SLICEL_I1_O JLUT5Xhzr< `\g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg00[34] Jnet (fo=1, routed)XhD< eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhX9?X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]/C JFDCEXhzr> Jclock pessimismXhH+ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[34]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh1뵿; J arrival timeXh?/ JXh4 JslackXh^/=sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]/D""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsup=>}1뵿Y9Ŀö=S?Y9?["=H+ʡ==(?I ?/?.?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_GFF_SLICEM_C_Q JFDCEXhzfD= qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)XhQ= fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[23]_i_1/I1 JXhzf eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[23]_i_1/OProp_H6LUT_SLICEL_I1_O JLUT5Xhzr< `\g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg00[23] Jnet (fo=1, routed)Xho< eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhX9?X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]/C JFDCEXhzr> Jclock pessimismXhH+ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]Hold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh1뵿; J arrival timeXh ?/ JXh4 JslackXh["=W/+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[18]/CFBSFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu'>}_Nb=M?Nb?(=/,9H==(?p= ?/?z&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR)} /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[18]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H=o ,(SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/Q[2] Jnet (fo=5, routed)Xh=x FBSFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 73SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[1].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X3Y0 (CLOCK_ROOT)x FBSFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/C JFDREXhzr> Jclock pessimismXh/, D@SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]Hold_DFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh_; J arrival timeXhK?/ JXh4 JslackXh(=sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/D""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu~>}WϱY9Ŀ j=S?Y9?/=L%=v=(?I ?/?.?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/QProp_HFF_SLICEM_C_Q JFDCEXhzfD= qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] Jnet (fo=28, routed)Xhʡ= fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[30]_i_1/I0 JXhzf eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[30]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT5Xhzru< `\g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg00[30] Jnet (fo=1, routed)XhA`e< eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhX9?X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/C JFDCEXhzr> Jclock pessimismXhL c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhWϱ; J arrival timeXhK?/ JXh4 JslackXh/=)%SFP_GEN[1].rx_data_ngccm_reg[1][35]/C/+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[34]/D""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu&1>}Fβ&J=n?&?ܥ8=,,X9={=(?~ ?/?r(?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR)v )%SFP_GEN[1].rx_data_ngccm_reg[1][35]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD=v 3/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[27] Jnet (fo=1, routed)Xh=^ 0,SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[34]_i_1/I0 JXhzr /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[34]_i_1/OProp_D5LUT_SLICEM_I0_O JLUT3Xhzr #=t 1-SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[34]_i_1_n_0 Jnet (fo=1, routed)XhD<a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[34]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[1] Jnet (fo=674, routed)XhS?X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][35]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXh,,x -)SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[34]Hold_DFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhFβ; J arrival timeXhu?/ JXh4 JslackXhܥ8=)%SFP_GEN[1].rx_data_ngccm_reg[1][48]/C/+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[48]/D""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu/>}TſW=ˡ?T?9=L=`P=(?b?/?1?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR)v )%SFP_GEN[1].rx_data_ngccm_reg[1][48]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=v 3/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[40] Jnet (fo=1, routed)Xh)\=^ 0,SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[48]_i_1/I1 JXhzr /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[48]_i_1/OProp_D6LUT_SLICEM_I1_O JLUT3Xhzr/]=t 1-SFP_GEN[1].ngCCM_gbt/RX_Word_rx40[48]_i_1_n_0 Jnet (fo=1, routed)Xho<a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[48]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh,?X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][48]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[1].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhİ?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[48]/C JFDCEXhzr> Jclock pessimismXhLw -)SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[48]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhX?/ JXh4 JslackXh9=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsut>}Jұſo,=}???Dy;=;X=L=(? ?/?1?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)XhC = g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__0/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__0/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh$?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh;X g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhJұ; J arrival timeXh?/ JXh4 JslackXhDy;=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu@>}}ſ=??izB=+==(?ף?/?1?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xhw= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__0/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__0/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhff?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh+ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh}; J arrival timeXhh?/ JXh4 JslackXhizB=j!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu"@}Ap8A~B)x@~B@A=А=E?\>b?@??~?O?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhlW@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzr֣p> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhף> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzrj= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0_n_0 Jnet (fo=1, routed)XhT%> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhnZ@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh$)@X3Y0 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhp8A; J arrival timeXh/ JXh4 JslackXhE? j!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu"@}Ap8A~B)x@~B@A=А=E?\>b?@??~?O?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhlW@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__0/OProp_C6LUT_SLICEL_I0_O JLUT4Xhzr֣p> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhף> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzrj= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__0_n_0 Jnet (fo=1, routed)XhT%> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__0_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhnZ@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh$)@X3Y0 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhp8A; J arrival timeXh/ JXh4 JslackXhE? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[1].rx_data_ngccm_reg[1][42]/CE""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsur=@}A9A CQ*b@ C@A=А=?AR>>@?Z@~?t?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhFS@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>X rx_data_ngccm[1] Jnet (fo=76, routed)XhA@\ *&SFP_GEN[1].rx_data_ngccm_reg[1][42]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh7)@X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][42]/C JFDCEXhzr> Jclock pessimismXhAR>@ Jclock uncertaintyXhs '#SFP_GEN[1].rx_data_ngccm_reg[1][42]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh9A; J arrival timeXh&/ JXh4 JslackXh?Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[1].rx_data_ngccm_reg[1][43]/CE""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu/@}A:%9ACJ(b@C@A=А=+?G>>@?Z@~??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhFS@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>X rx_data_ngccm[1] Jnet (fo=76, routed)XhI?\ *&SFP_GEN[1].rx_data_ngccm_reg[1][43]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[1] Jnet (fo=674, routed)XhJ *@X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][43]/C JFDCEXhzr> Jclock pessimismXhG>@ Jclock uncertaintyXhs '#SFP_GEN[1].rx_data_ngccm_reg[1][43]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh:%9A; J arrival timeXh/ JXh4 JslackXh+?Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[1].rx_data_ngccm_reg[1][47]/CE""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuγ@}Ae9AjDy#b@jD@A=А=?.>>P@?Z@~?0?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhFS@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>X rx_data_ngccm[1] Jnet (fo=76, routed)Xh?\ *&SFP_GEN[1].rx_data_ngccm_reg[1][47]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[1] Jnet (fo=674, routed)XhC+@X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][47]/C JFDCEXhzr> Jclock pessimismXh.>@ Jclock uncertaintyXht '#SFP_GEN[1].rx_data_ngccm_reg[1][47]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhe9A; J arrival timeXh/ JXh4 JslackXh?Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[1].rx_data_ngccm_reg[1][51]/CE""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuγ@}Ae9AjDy#b@jD@A=А=?.>>P@?Z@~?0?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhFS@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>X rx_data_ngccm[1] Jnet (fo=76, routed)Xh?\ *&SFP_GEN[1].rx_data_ngccm_reg[1][51]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[1] Jnet (fo=674, routed)XhC+@X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][51]/C JFDCEXhzr> Jclock pessimismXh.>@ Jclock uncertaintyXht '#SFP_GEN[1].rx_data_ngccm_reg[1][51]Setup_FFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhe9A; J arrival timeXh/ JXh4 JslackXh?Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[1].rx_data_ngccm_reg[1][72]/CE""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuγ@}Ae9AjDy#b@jD@A=А=?.>>P@?Z@~?0?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhFS@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>X rx_data_ngccm[1] Jnet (fo=76, routed)Xh?\ *&SFP_GEN[1].rx_data_ngccm_reg[1][72]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[1] Jnet (fo=674, routed)XhC+@X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][72]/C JFDCEXhzr> Jclock pessimismXh.>@ Jclock uncertaintyXht '#SFP_GEN[1].rx_data_ngccm_reg[1][72]Setup_GFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhe9A; J arrival timeXh/ JXh4 JslackXh?Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[1].rx_data_ngccm_reg[1][75]/CE""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuγ@}Ae9AjDy#b@jD@A=А=?.>>P@?Z@~?0?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhFS@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>X rx_data_ngccm[1] Jnet (fo=76, routed)Xh?\ *&SFP_GEN[1].rx_data_ngccm_reg[1][75]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[1] Jnet (fo=674, routed)XhC+@X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][75]/C JFDCEXhzr> Jclock pessimismXh.>@ Jclock uncertaintyXht '#SFP_GEN[1].rx_data_ngccm_reg[1][75]Setup_HFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhe9A; J arrival timeXh/ JXh4 JslackXh?Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[1].rx_data_ngccm_reg[1][46]/CE""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuE@}AEr9AjDy#b@jD@A=А=w?.>>t@?Z@~?0?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhFS@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>X rx_data_ngccm[1] Jnet (fo=76, routed)Xhff?\ *&SFP_GEN[1].rx_data_ngccm_reg[1][46]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[1] Jnet (fo=674, routed)XhC+@X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][46]/C JFDCEXhzr> Jclock pessimismXh.>@ Jclock uncertaintyXhs '#SFP_GEN[1].rx_data_ngccm_reg[1][46]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhEr9A; J arrival timeXhT/ JXh4 JslackXhw?Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[1].rx_data_ngccm_reg[1][50]/CE""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuE@}AEr9AjDy#b@jD@A=А=w?.>>t@?Z@~?0?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhFS@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[1].rx_data_ngccm[1][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>X rx_data_ngccm[1] Jnet (fo=76, routed)Xhff?\ *&SFP_GEN[1].rx_data_ngccm_reg[1][50]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[1] Jnet (fo=674, routed)XhC+@X3Y0 (CLOCK_ROOT)[ )%SFP_GEN[1].rx_data_ngccm_reg[1][50]/C JFDCEXhzr> Jclock pessimismXh.>@ Jclock uncertaintyXhs '#SFP_GEN[1].rx_data_ngccm_reg[1][50]Setup_FFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhEr9A; J arrival timeXhT/ JXh4 JslackXhw?L&  gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4!)y@1y @9Ay@Iy @e})?hq} @ =  >  rise - rise rise - rise  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu+>}w_=أ?w?@ =^/v=E=Yd??/?$&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhP= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__1/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__1/OProp_B6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xhu< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh^/ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh@ =g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsut>}eSÿgi5=]?S?K 3=|X=L=Yd? ?/?O-?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)XhC = g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__1/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__1/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xht?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?5?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh|X g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhe; J arrival timeXh?/ JXh4 JslackXhK 3=Y/+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]/CGCSFP_GEN[2].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu/$>} O{7x=Mb?{?5=~/9H=A`=Yd?+?/?"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR)| /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H=p -)SFP_GEN[2].ngCCM_gbt/gbt_rx_checker/Q[11] Jnet (fo=2, routed)XhA`=y GCSFP_GEN[2].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/D JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 73SFP_GEN[2].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[2].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT)y GCSFP_GEN[2].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C JFDREXhzr> Jclock pessimismXh~/ EASFP_GEN[2].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]Hold_GFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh O; J arrival timeXh?/ JXh4 JslackXh5=rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[2]/Cb^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/shiftPsAddr_reg_inv/D"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu>}ףQ=A?ף? kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/shiftPsAddr_reg_inv/C JFDPEXhzr> Jclock pessimismXh$N `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/shiftPsAddr_reg_invHold_BFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh; J arrival timeXhG?/ JXh4 JslackXh}w_=أ?w?b9=^/ =-=Yd??/?$&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhP= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__1/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__1/OProp_B5LUT_SLICEL_I0_O JLUT3Xhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[3] Jnet (fo=1, routed)XhT< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr> Jclock pessimismXh^/ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]Hold_BFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhȶ?/ JXh4 JslackXhb9=,(SFP_GEN[2].ngccm_status_reg_reg[2][24]/C,(SFP_GEN[2].ngccm_status_reg_reg[2][24]/D"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsui;=}_-¿֣;?-?D=|o=Q8=Yd?r= ?/?+?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR)y ,(SFP_GEN[2].ngccm_status_reg_reg[2][24]/QProp_AFF_SLICEM_C_Q JFDPEXhzr9H= D@SFP_GEN[2].ngCCM_gbt/SFP_GEN[2].ngccm_status_reg_reg[2][24]_0[8] Jnet (fo=2, routed)Xh+=p B>SFP_GEN[2].ngCCM_gbt/SFP_GEN[2].ngccm_status_reg[2][24]_i_2/I0 JXhzr A=SFP_GEN[2].ngCCM_gbt/SFP_GEN[2].ngccm_status_reg[2][24]_i_2/OProp_A6LUT_SLICEM_I0_O JLUT2Xhzru<a SFP_GEN[2].ngCCM_gbt_n_393 Jnet (fo=1, routed)XhD<^ ,(SFP_GEN[2].ngccm_status_reg_reg[2][24]/D JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[2] Jnet (fo=674, routed)XhВ?X3Y0 (CLOCK_ROOT)^ ,(SFP_GEN[2].ngccm_status_reg_reg[2][24]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[2] Jnet (fo=674, routed)XhW?X3Y0 (CLOCK_ROOT)^ ,(SFP_GEN[2].ngccm_status_reg_reg[2][24]/C JFDPEXhzr> Jclock pessimismXh|t *&SFP_GEN[2].ngccm_status_reg_reg[2][24]Hold_AFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXh_; J arrival timeXh=߯?/ JXh4 JslackXhD=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuw>}eSÿgi5=]?S?-G=|X=Q8=Yd? ?/?O-?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)XhC = g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__1/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__1/OProp_D5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[2] Jnet (fo=1, routed)XhX94< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xht?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?5?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr> Jclock pessimismXh|X g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhe; J arrival timeXh̡?/ JXh4 JslackXh-G=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuǡE>}m=??1I=:/[=9=Yd?l?/?)?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__1/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__1/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzrj<= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[16] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhsh?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhD?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh:/ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhK7?/ JXh4 JslackXh1I=]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/C]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/D"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuS=}Ԩףף;$?ף?L=wo=@=Yd?r?/?'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/ready_from_bitSlipCtrller_2 Jnet (fo=2, routed)Xh)\= a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_i_1__1/I2 JXhzr `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_i_1__1/OProp_A6LUT_SLICEL_I2_O JLUT3Xhzru< b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_i_1__1_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXhw [Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_regHold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhԨ; J arrival timeXhd;?/ JXh4 JslackXhL=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[71]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[71]/D"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuM>}n¿j=Mb?n?CM=,/D=>Yd?+?/? +?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[71]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[71] Jnet (fo=1, routed)Xh> eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[71]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhG?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[71]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhO?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[71]/C JFDCEXhzr> Jclock pessimismXh,/ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[71]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhCM=h!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuˡ@}A8ABGy@B@A=А=})?$>?@?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhL@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhO> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1/OProp_B5LUT_SLICEL_I2_O JLUT4Xhzr8> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1_n_0 Jnet (fo=1, routed)Xhrh> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHZ@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhף(@X3Y0 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh$>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh8A; J arrival timeXh"/ JXh4 JslackXh})? h!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuˡ@}A8ABGy@B@A=А=})?$>?@?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhL@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhO> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1/OProp_B5LUT_SLICEL_I2_O JLUT4Xhzr8> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__1_n_0 Jnet (fo=1, routed)Xhrh> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__1_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHZ@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhף(@X3Y0 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh$>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh8A; J arrival timeXh"/ JXh4 JslackXh})? zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu @}A8AA Gy@A@A=А=t @>?y~@?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhL@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrA`> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh/? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHZ@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'@X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh8A; J arrival timeXh/ JXh4 JslackXht @ zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu @}A8AA Gy@A@A=А=t @>?y~@?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhL@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrA`> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh/? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHZ@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'@X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh8A; J arrival timeXh/ JXh4 JslackXht @ yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu@}A68AA Gy@A@A=А= @>?Q~@?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhL@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrA`> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHZ@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'@X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh68A; J arrival timeXh/ JXh4 JslackXh @ yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu@}A68AA Gy@A@A=А= @>?Q~@?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhL@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrA`> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHZ@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'@X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh68A; J arrival timeXh/ JXh4 JslackXh @ yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu@}A68AA Gy@A@A=А= @>?Q~@?"???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhL@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr/> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xȟ> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__2/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrA`> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHZ@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'@X3Y0 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh68A; J arrival timeXh/ JXh4 JslackXh @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuj@}A~8A&A)Gy@&A@A=А=@>Z?v@?"??k?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhL@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzf/> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh}?5> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh"> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHZ@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'@X3Y0 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh~8A; J arrival timeXh+/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuj@}A~8A&A)Gy@&A@A=А=@>Z?v@?"??k?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhL@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzf/> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh}?5> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh"> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHZ@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'@X3Y0 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_GFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh~8A; J arrival timeXh+/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuI@}A-8A&A)Gy@&A@A=А=Q@>Z?ffv@?"??k?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhL@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/I0 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__1/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzf/> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh}?5> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__2/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHZ@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'@X3Y0 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh-8A; J arrival timeXhv/ JXh4 JslackXhQ@ &  gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5!)y@1y @9Ay@Iy @e~?hq} =  >   rise - rise rise - rise  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu(>}G=В??=1#v=-=&>?r?V.?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_CFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__2/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__2/OProp_A6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZd?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh1# g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhG; J arrival timeXh?/ JXh4 JslackXh=sg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C)%SFP_GEN[3].rx_data_ngccm_reg[3][28]/D""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuUb>}"*:=h?"?a!==D=v=&>Z?r?#?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[3][28] Jnet (fo=1, routed)Xhv=[ )%SFP_GEN[3].rx_data_ngccm_reg[3][28]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh|?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[3].rx_data_ngccm_reg[3][28]/C JFDCEXhzr> Jclock pessimismXh=r '#SFP_GEN[3].rx_data_ngccm_reg[3][28]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXha!=tg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C)%SFP_GEN[3].rx_data_ngccm_reg[3][58]/D""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuQ>}NbX<=َ?Nb?0!=+9H=v>&>z?r?|.?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/QProp_BFF_SLICEM_C_Q JFDREXhzr9H=U rx_data[3][58] Jnet (fo=1, routed)Xhv>[ )%SFP_GEN[3].rx_data_ngccm_reg[3][58]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh|?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[3] Jnet (fo=674, routed)XhC?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[3].rx_data_ngccm_reg[3][58]/C JFDCEXhzr> Jclock pessimismXh+q '#SFP_GEN[3].rx_data_ngccm_reg[3][58]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh0!=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu/>}@㢿 =-? ?H%=:D# ף=5^=&>i ?r?j-?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__2/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__2/OProp_H6LUT_SLICEM_I2_O JLUT3Xhzro= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xho?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh:D# g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_HFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh@㢿; J arrival timeXhc?/ JXh4 JslackXhH%=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu433>}@㢿 =-? ?6=:D#X9=-=&>i ?r?j-?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__2/OProp_H5LUT_SLICEM_I0_O JLUT3Xhzr #= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xho?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr> Jclock pessimismXh:D# g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]Hold_HFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh@㢿; J arrival timeXhu?/ JXh4 JslackXh6=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu >}|D̬:VT=v?̬?8==o=E=&>$?r?y&?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)XhP= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__2/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xhu< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ~?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh|D; J arrival timeXhI ?/ JXh4 JslackXh8=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu<33>}G=В??==1# =E=&>?r?V.?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_CFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__2/OProp_A5LUT_SLICEL_I0_O JLUT3Xhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[7] Jnet (fo=1, routed)XhA`e< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZd?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr> Jclock pessimismXh1# g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]Hold_AFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhG; J arrival timeXhM7?/ JXh4 JslackXh==)%SFP_GEN[3].rx_data_ngccm_reg[3][58]/C/+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[58]/D""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu-2>}㢿 =]? ?">=>#-=-=&>V?r?j-?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR)v )%SFP_GEN[3].rx_data_ngccm_reg[3][58]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H=v 3/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]_0[50] Jnet (fo=1, routed)Xh㥛=^ 0,SFP_GEN[3].ngCCM_gbt/RX_Word_rx40[58]_i_1/I1 JXhzr /+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40[58]_i_1/OProp_C5LUT_SLICEL_I1_O JLUT3Xhzr=t 1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40[58]_i_1_n_0 Jnet (fo=1, routed)XhX94<a /+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[58]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[3] Jnet (fo=674, routed)Xht?X3Y1 (CLOCK_ROOT)[ )%SFP_GEN[3].rx_data_ngccm_reg[3][58]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[58]/C JFDCEXhzr> Jclock pessimismXh>#x -)SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[58]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh㢿; J arrival timeXhԨ?/ JXh4 JslackXh">=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuph>}nW=*\?W?KC=TF=D=&>?r?l'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xht= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__2/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__2/OProp_F6LUT_SLICEM_I2_O JLUT3Xhzrj<= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhA?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXhTF g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_FFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhn; J arrival timeXh8?/ JXh4 JslackXhKC=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuph>}nW=*\?W?KC=TF=D=&>?r?l'?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)Xht= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__2/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__2/OProp_E6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhA?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhTF g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_EFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhn; J arrival timeXh8?/ JXh4 JslackXhKC=j!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu@}A7n2A~*Pyb`@~*@A=А=~?>&?@/?$?Nb??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhnR@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh`> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__2/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__2/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzrx> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__2_n_0 Jnet (fo=1, routed)Xh = njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2_n_0 Jnet (fo=2, routed)Xh~> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh%@X3Y1 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh7n2A; J arrival timeXh/ JXh4 JslackXh~? j!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu@}A7n2A~*Pyb`@~*@A=А=~?>&?@/?$?Nb??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhnR@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh`> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__2/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__2/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzrx> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__2_n_0 Jnet (fo=1, routed)Xh = njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__2_n_0 Jnet (fo=2, routed)Xh~> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh%@X3Y1 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh7n2A; J arrival timeXh/ JXh4 JslackXh~? |g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuLb@}AE2A#)b`@#)@A=А=e?>v?Ĉ@/?$?Nb?Nb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhnR@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh+? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhNb@X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhE2A; J arrival timeXh?5/ JXh4 JslackXhe? |g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuLb@}AE2A#)b`@#)@A=А=e?>v?Ĉ@/?$?Nb?Nb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhnR@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh+? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhNb@X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhE2A; J arrival timeXh?5/ JXh4 JslackXhe? {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuI@}AI2A#)b`@#)@A=А=s?>v?@/?$?Nb?Nb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhnR@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhNb@X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhI2A; J arrival timeXh(/ JXh4 JslackXhs? {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuI@}AI2A#)b`@#)@A=А=s?>v?@/?$?Nb?Nb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhnR@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhNb@X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_AFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhI2A; J arrival timeXh(/ JXh4 JslackXhs? {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuI@}AI2A#)b`@#)@A=А=s?>v?@/?$?Nb?Nb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhnR@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhNb@X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhI2A; J arrival timeXh(/ JXh4 JslackXhs? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu@}A#2Am+ b`@m+@A=А=@{>?1@/?$?Nb?z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhnR@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I1 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_D6LUT_SLICEL_I1_O JLUT4XhzfFs> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh ? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn@X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh{>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh#2A; J arrival timeXh"/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuN@}Am2Am+ b`@m+@A=А=@{>?m@/?$?Nb?z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhnR@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I1 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_D6LUT_SLICEL_I1_O JLUT4XhzfFs> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__3/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn@X3Y1 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh{>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhm2A; J arrival timeXh/ JXh4 JslackXh@ {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu@}A2AH* b`@H*@A=А= @>v?a@/?$?Nb?n?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhnR@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__2/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__3/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhA@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhrh@X3Y1 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh2A; J arrival timeXhE/ JXh4 JslackXh @ &  gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6!)y@1y @9Ay@Iy @ee<@hq} V = >   rise - rise rise - rise  ug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C)%SFP_GEN[4].rx_data_ngccm_reg[4][74]/D""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsun>}Lq=R[=I?q=?V =8D=\=">,? >-R?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=U rx_data[4][74] Jnet (fo=1, routed)Xh\=[ )%SFP_GEN[4].rx_data_ngccm_reg[4][74]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh5^z?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[4].rx_data_ngccm_reg[4][74]/C JFDCEXhzr> Jclock pessimismXh8r '#SFP_GEN[4].rx_data_ngccm_reg[4][74]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhL; J arrival timeXh?/ JXh4 JslackXhV =ug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C)%SFP_GEN[4].rx_data_ngccm_reg[4][57]/D""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu+>}Pxc=C?x?IU=D=F=">O-? >ףP?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[4][57] Jnet (fo=1, routed)XhF=[ )%SFP_GEN[4].rx_data_ngccm_reg[4][57]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhGz?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[4] Jnet (fo=674, routed)XhZ?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[4].rx_data_ngccm_reg[4][57]/C JFDCEXhzr> Jclock pessimismXhq '#SFP_GEN[4].rx_data_ngccm_reg[4][57]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhP; J arrival timeXh?/ JXh4 JslackXhIU=ug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C)%SFP_GEN[4].rx_data_ngccm_reg[4][19]/D""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu^d;>}Xo=l??pj=Ŋ9H=L7 >">0,? >R?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=U rx_data[4][19] Jnet (fo=1, routed)XhL7 >[ )%SFP_GEN[4].rx_data_ngccm_reg[4][19]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[4].rx_data_ngccm_reg[4][19]/C JFDCEXhzr> Jclock pessimismXhŊr '#SFP_GEN[4].rx_data_ngccm_reg[4][19]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhX; J arrival timeXhS?/ JXh4 JslackXhpj=rg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C)%SFP_GEN[4].rx_data_ngccm_reg[4][25]/D""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsup=>}y+=l??x#=&9H=C >">0,? >33S?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_BFF_SLICEM_C_Q JFDREXhzr9H=U rx_data[4][25] Jnet (fo=1, routed)XhC >[ )%SFP_GEN[4].rx_data_ngccm_reg[4][25]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[4] Jnet (fo=674, routed)Xhˡ?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[4].rx_data_ngccm_reg[4][25]/C JFDCEXhzr> Jclock pessimismXh&r '#SFP_GEN[4].rx_data_ngccm_reg[4][25]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhy; J arrival timeXh?/ JXh4 JslackXhx#=tg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C)%SFP_GEN[4].rx_data_ngccm_reg[4][55]/D""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu/>}Pxc=C?x?#=D=l=">O-? >ףP?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=U rx_data[4][55] Jnet (fo=1, routed)Xhl=[ )%SFP_GEN[4].rx_data_ngccm_reg[4][55]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhGz?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[4] Jnet (fo=674, routed)XhZ?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[4].rx_data_ngccm_reg[4][55]/C JFDCEXhzr> Jclock pessimismXhq '#SFP_GEN[4].rx_data_ngccm_reg[4][55]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhP; J arrival timeXhn?/ JXh4 JslackXh#=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu433>}y#۩B=C?#۩?'=c =E=">O-? >thQ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_17_in Jnet (fo=2, routed)Xh-= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__3/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__3/OProp_G5LUT_SLICEL_I2_O JLUT3Xhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[7] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhGz?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhk?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr> Jclock pessimismXhc g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]Hold_GFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhy; J arrival timeXh?/ JXh4 JslackXh'=)%SFP_GEN[4].rx_data_ngccm_reg[4][24]/C/+SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[24]/D""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuJ>}kٞ c=? ?'=9H=u>">_)? >GS?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR)w )%SFP_GEN[4].rx_data_ngccm_reg[4][24]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[83]_0[16] Jnet (fo=1, routed)Xhu>a /+SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[24]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[4] Jnet (fo=674, routed)XhKw?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[4].rx_data_ngccm_reg[4][24]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[24]/C JFDCEXhzr> Jclock pessimismXhw -)SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[24]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhkٞ; J arrival timeXh?/ JXh4 JslackXh'=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu!>}5L7q=~?L7?J0=b9v= ף=">K7)? > P?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_GFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xh+= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__3/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__3/OProp_G6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)XhA`e< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhv?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXhb9 g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh5; J arrival timeXhS?/ JXh4 JslackXhJ0=)%SFP_GEN[4].rx_data_ngccm_reg[4][28]/C/+SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]/D""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuL>}RHᪿ=?H?_94=D=>">_)? >tS?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR)w )%SFP_GEN[4].rx_data_ngccm_reg[4][28]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD=v 3/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[83]_0[20] Jnet (fo=1, routed)Xh>a /+SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[4] Jnet (fo=674, routed)XhKw?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[4].rx_data_ngccm_reg[4][28]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[4].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh•?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXhw -)SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhR; J arrival timeXhZ?/ JXh4 JslackXh_94=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu{?5>}+=?+?25=ʡ=9=">&1(? >2L?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__3/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__3/OProp_C6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhu?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhJ ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh֣?/ JXh4 JslackXh25=|g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuI@}A0AV&Z=.@V&@A=А=e<@ad>D?&@*?$??j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh}?E@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr&1> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh-> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/OProp_B6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhB`? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/ @X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhe<@ |g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuNb@}A0A&u2=.@&@A=А=ě<@ad>D?}?@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh}?E@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr&1> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh-> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/OProp_B6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh$? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh-/ JXh4 JslackXhě<@ {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuI@}A60A&u2=.@&@A=А=K<@ad>D?&@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh}?E@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr&1> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh-> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/OProp_B6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhB`? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh60A; J arrival timeXh/ JXh4 JslackXhK<@ {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu(@}A0AV&Z=.@V&@A=А=N<@ad>D?%@*?$??j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh}?E@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr&1> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh-> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/OProp_B6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhZ? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/ @X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhN<@ {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu(@}A0AV&Z=.@V&@A=А=N<@ad>D?%@*?$??j?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh}?E@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr&1> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh-> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/OProp_B6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhZ? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/ @X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhN<@ j!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuΫ@}A0A?5&=.@?5&@A=А=d`=@ad>̼?K7y@*?$??(?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh}?E@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr&1> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh7A> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr(> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3_n_0 Jnet (fo=1, routed)XhSc> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3/OProp_C6LUT_SLICEL_I5_O JLUT6Xhzr`P= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3_n_0 Jnet (fo=2, routed)XhO> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj @X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXhrh/ JXh4 JslackXhd`=@ j!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuΫ@}A0A?5&=.@?5&@A=А=d`=@ad>̼?K7y@*?$??(?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh}?E@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr&1> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh7A> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr(> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__3_n_0 Jnet (fo=1, routed)XhSc> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3/OProp_C6LUT_SLICEL_I5_O JLUT6Xhzr`P= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__3_n_0 Jnet (fo=2, routed)XhO> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj @X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXhrh/ JXh4 JslackXhd`=@ {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuX9@}A0A+&&=.@+&@A=А=LD@ad>D?-z@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh}?E@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr&1> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh-> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/OProp_B6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh^> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU @X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXhe;/ JXh4 JslackXhLD@ {g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuX9@}A0A+&&=.@+&@A=А=LD@ad>D?-z@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh}?E@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr&1> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh-> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__4/OProp_B6LUT_SLICEL_I3_O JLUT5XhzrE= ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh^> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU @X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXhe;/ JXh4 JslackXhLD@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT4=1 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuS@}A0A+&&=.@+&@A=А=vF@ad>?Ss@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh}?E@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/I0 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__3/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzf&1> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/I0 JXhzf zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__4/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr1,> b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh!> xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU @X4Y2 (CLOCK_ROOT) wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh0A; J arrival timeXhV/ JXh4 JslackXhvF@ &  gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7!)y@1y @9Ay@Iy @e@@hq} E>= >   rise - rise rise - rise  xg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C)%SFP_GEN[5].rx_data_ngccm_reg[5][60]/D"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsut>}D Mg=??E>=?D==>4? >m[?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[5][60] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[5].rx_data_ngccm_reg[5][60]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][60]/C JFDCEXhzr> Jclock pessimismXh?r '#SFP_GEN[5].rx_data_ngccm_reg[5][60]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhD; J arrival timeXhn?/ JXh4 JslackXhE>=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu&1>}xz󭿭=Đ??-="-= =>+6? >Y?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[1] Jnet (fo=2, routed)XhP= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__4/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__4/OProp_H5LUT_SLICEL_I2_O JLUT3Xhzrw= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[18] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXh" g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Hold_HFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhxz; J arrival timeXhy?/ JXh4 JslackXh-=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu|.>}is=Đ?i? .=~,ʡ=5^=>+6? >X?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__4/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__4/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhr?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh~, g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh+?/ JXh4 JslackXh .=_[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[1]/C]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/D"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu>}ߚCX=?C?J0=t<%=E=>.? >Y9T?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[1]/QProp_HFF_SLICEL_C_Q JFDCEXhzfD= YUg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress[1] Jnet (fo=8, routed)Xh= a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_i_1__4/I4 JXhzf `\g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_i_1__4/OProp_H6LUT_SLICEL_I4_O JLUT6Xhzru< WSg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd Jnet (fo=1, routed)Xho< ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{?X4Y2 (CLOCK_ROOT) _[g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[1]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh$?X4Y2 (CLOCK_ROOT) ]Yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/C JFDCEXhzr> Jclock pessimismXht< [Wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_regHold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhߚ; J arrival timeXhNb?/ JXh4 JslackXhJ0=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[31]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]/D"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsun>}_Iy/=َ?I?8=?D=[=>!2? >EV?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[31]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[31] Jnet (fo=1, routed)Xh[= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh|?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[31]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh+?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]/C JFDCEXhzr> Jclock pessimismXh? c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh_; J arrival timeXh&?/ JXh4 JslackXh8=tg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C)%SFP_GEN[5].rx_data_ngccm_reg[5][48]/D"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuS>};u@5ȐU=?@5?;?=;X?9H==>X94? >Z?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=U rx_data[5][48] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[5].rx_data_ngccm_reg[5][48]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][48]/C JFDCEXhzr> Jclock pessimismXh;X?q '#SFP_GEN[5].rx_data_ngccm_reg[5][48]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh;u; J arrival timeXht?/ JXh4 JslackXh;?=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu433>}is=Đ?i?ńB=~,X9=-=>+6? >X?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__4/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__4/OProp_D5LUT_SLICEM_I0_O JLUT3Xhzr #= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhr?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr> Jclock pessimismXh~, g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]Hold_DFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh+?/ JXh4 JslackXhńB=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[73]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[73]/D"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuS>}ڔIJ=|?I?J=>D="=>&1? >EV?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[73]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[73] Jnet (fo=1, routed)Xh"= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[73]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh}?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[73]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh+?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[73]/C JFDCEXhzr> Jclock pessimismXh> c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[73]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhڔ; J arrival timeXh?/ JXh4 JslackXhJ=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuK7>}m,ڕ=v??L=v==>1? >jT?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/QProp_CFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_9_in Jnet (fo=2, routed)Xh{= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__4/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__4/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[5] Jnet (fo=1, routed)Xho< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ~?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhff?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhm; J arrival timeXhA`?/ JXh4 JslackXhL=tg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C)%SFP_GEN[5].rx_data_ngccm_reg[5][44]/D"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu">}?t@5Y=|?@5?pYL=`?9H=G=>3? >Z?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=U rx_data[5][44] Jnet (fo=1, routed)XhG=[ )%SFP_GEN[5].rx_data_ngccm_reg[5][44]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhNb?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][44]/C JFDCEXhzr> Jclock pessimismXh`?q '#SFP_GEN[5].rx_data_ngccm_reg[5][44]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh?t; J arrival timeXh ף?/ JXh4 JslackXhpYL=g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[3]/D"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuj@}A3A-*{~8>k,@-*@A=А=@@>ta>?C@q=*?P???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/D[3] Jnet (fo=10, routed)XhC@ d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[3]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh:@X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[3]/C JFDCEXhzr> Jclock pessimismXh>ta>@ Jclock uncertaintyXh b^g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[3]Setup_FFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXh3A; J arrival timeXhZd/ JXh4 JslackXh@@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[23]/D"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu\@}A*3AH*C>k,@H*@A=А=1E@>ta>K?k@q=*?P???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/D[3] Jnet (fo=10, routed)Xh@ ieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[23]_i_1__8/I3 JXhzr hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0[23]_i_1__8/OProp_D6LUT_SLICEL_I3_O JLUT5Xhzr> `\g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg00[23] Jnet (fo=1, routed)Xh*\= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[23]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhrh@X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[23]/C JFDCEXhzr> Jclock pessimismXh>ta>@ Jclock uncertaintyXh c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[23]Setup_DFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXh*3A; J arrival timeXhv/ JXh4 JslackXh1E@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[5].rx_data_ngccm_reg[5][67]/CE"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu= @}AO1A-*=F3@-*@A=А=|L@a>>^@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^*@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[5] Jnet (fo=76, routed)Xh @\ *&SFP_GEN[5].rx_data_ngccm_reg[5][67]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh:@X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][67]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXht '#SFP_GEN[5].rx_data_ngccm_reg[5][67]Setup_AFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhO1A; J arrival timeXh`/ JXh4 JslackXh|L@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[5].rx_data_ngccm_reg[5][72]/CE"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu= @}AO1A-*=F3@-*@A=А=|L@a>>^@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^*@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[5] Jnet (fo=76, routed)Xh @\ *&SFP_GEN[5].rx_data_ngccm_reg[5][72]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh:@X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][72]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXht '#SFP_GEN[5].rx_data_ngccm_reg[5][72]Setup_BFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhO1A; J arrival timeXh`/ JXh4 JslackXh|L@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[5].rx_data_ngccm_reg[5][75]/CE"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu= @}AO1A-*=F3@-*@A=А=|L@a>>^@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^*@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[5] Jnet (fo=76, routed)Xh @\ *&SFP_GEN[5].rx_data_ngccm_reg[5][75]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh:@X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][75]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXht '#SFP_GEN[5].rx_data_ngccm_reg[5][75]Setup_CFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhO1A; J arrival timeXh`/ JXh4 JslackXh|L@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[5].rx_data_ngccm_reg[5][77]/CE"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu= @}AO1A-*=F3@-*@A=А=|L@a>>^@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^*@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[5] Jnet (fo=76, routed)Xh @\ *&SFP_GEN[5].rx_data_ngccm_reg[5][77]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh:@X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][77]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXht '#SFP_GEN[5].rx_data_ngccm_reg[5][77]Setup_DFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhO1A; J arrival timeXh`/ JXh4 JslackXh|L@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[5].rx_data_ngccm_reg[5][58]/CE"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu㥣@}AR2AF++=F3@F+@A=А==M@a>>V@q=*???+?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^*@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[5] Jnet (fo=76, routed)XhM @\ *&SFP_GEN[5].rx_data_ngccm_reg[5][58]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xhq=@X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][58]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXht '#SFP_GEN[5].rx_data_ngccm_reg[5][58]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhR2A; J arrival timeXh/ JXh4 JslackXh=M@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[5].rx_data_ngccm_reg[5][60]/CE"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu㥣@}AR2AF++=F3@F+@A=А==M@a>>V@q=*???+?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^*@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[5] Jnet (fo=76, routed)XhM @\ *&SFP_GEN[5].rx_data_ngccm_reg[5][60]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xhq=@X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][60]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXht '#SFP_GEN[5].rx_data_ngccm_reg[5][60]Setup_FFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhR2A; J arrival timeXh/ JXh4 JslackXh=M@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[5].rx_data_ngccm_reg[5][62]/CE"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu㥣@}AR2AF++=F3@F+@A=А==M@a>>V@q=*???+?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^*@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[5] Jnet (fo=76, routed)XhM @\ *&SFP_GEN[5].rx_data_ngccm_reg[5][62]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xhq=@X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][62]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXht '#SFP_GEN[5].rx_data_ngccm_reg[5][62]Setup_GFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhR2A; J arrival timeXh/ JXh4 JslackXh=M@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[5].rx_data_ngccm_reg[5][69]/CE"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu㥣@}AR2AF++=F3@F+@A=А==M@a>>V@q=*???+?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^*@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[5].rx_data_ngccm[5][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr>X rx_data_ngccm[5] Jnet (fo=76, routed)XhM @\ *&SFP_GEN[5].rx_data_ngccm_reg[5][69]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[5] Jnet (fo=674, routed)Xhq=@X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[5].rx_data_ngccm_reg[5][69]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXht '#SFP_GEN[5].rx_data_ngccm_reg[5][69]Setup_HFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhR2A; J arrival timeXh/ JXh4 JslackXh=M@L&  gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8!)y@1y @9Ay@Iy @enr@hq} =  >    rise - rise rise - rise  tg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C)%SFP_GEN[6].rx_data_ngccm_reg[6][24]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu&1>}F=&q?F?= D=>>U?>ˡ%?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[6][24] Jnet (fo=1, routed)Xh>[ )%SFP_GEN[6].rx_data_ngccm_reg[6][24]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhR?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[6] Jnet (fo=674, routed)Xh/}?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[6].rx_data_ngccm_reg[6][24]/C JFDCEXhzr> Jclock pessimismXh q '#SFP_GEN[6].rx_data_ngccm_reg[6][24]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhS?/ JXh4 JslackXh=xg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C)%SFP_GEN[6].rx_data_ngccm_reg[6][35]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuxh>}sSVH=Nbp?S?Px=7&D==>?>0$?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[6][35] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[6].rx_data_ngccm_reg[6][35]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-R?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[6] Jnet (fo=674, routed)Xhj|?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[6].rx_data_ngccm_reg[6][35]/C JFDCEXhzr> Jclock pessimismXh7&r '#SFP_GEN[6].rx_data_ngccm_reg[6][35]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhs; J arrival timeXh6^?/ JXh4 JslackXhPx=)%SFP_GEN[6].rx_data_ngccm_reg[6][59]/C/+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu&1>}Вv= p?В?#=`(-= =>/?> #?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR)v )%SFP_GEN[6].rx_data_ngccm_reg[6][59]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H=v 3/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[83]_0[51] Jnet (fo=1, routed)Xh=^ 0,SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[58]_i_1/I0 JXhzr /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[58]_i_1/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr=t 1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[58]_i_1_n_0 Jnet (fo=1, routed)XhX94<a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[6] Jnet (fo=674, routed)XhQ?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[6].rx_data_ngccm_reg[6][59]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]/C JFDCEXhzr> Jclock pessimismXh`(x -)SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh@5?/ JXh4 JslackXh#=wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C)%SFP_GEN[6].rx_data_ngccm_reg[6][37]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuz>}ք!];=?>#?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=U rx_data[6][37] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[6].rx_data_ngccm_reg[6][37]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[6] Jnet (fo=674, routed)Xh"{?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[6].rx_data_ngccm_reg[6][37]/C JFDCEXhzr> Jclock pessimismXhD'r '#SFP_GEN[6].rx_data_ngccm_reg[6][37]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhք; J arrival timeXh~?/ JXh4 JslackXhq5=og_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C($SFP_GEN[6].rx_data_ngccm_reg[6][4]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsut>}!/=أp?!?8='D==>B`?>#?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=T  rx_data[6][4] Jnet (fo=1, routed)Xh=Z ($SFP_GEN[6].rx_data_ngccm_reg[6][4]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhnR?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[6] Jnet (fo=674, routed)Xh"{?X4Y2 (CLOCK_ROOT)Z ($SFP_GEN[6].rx_data_ngccm_reg[6][4]/C JFDCEXhzr> Jclock pessimismXh'q &"SFP_GEN[6].rx_data_ngccm_reg[6][4]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh8=]/+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[26]/CGCSFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuQ8>}8񒿭=أp??PgD=9H=$>>B`?>$?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR)| /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[26]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H=p -)SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/Q[10] Jnet (fo=2, routed)Xh$>y GCSFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/D JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhnR?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[26]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[6].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{?X4Y2 (CLOCK_ROOT)y GCSFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/C JFDREXhzr> Jclock pessimismXh EASFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]Hold_HFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh8; J arrival timeXh*\?/ JXh4 JslackXhPgD=^/+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[29]/CGCSFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu;^:>}8񒿭=أp??L=D=L7 >>B`?>$?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR)} /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[29]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD=p -)SFP_GEN[6].ngCCM_gbt/gbt_rx_checker/Q[13] Jnet (fo=2, routed)XhL7 >y GCSFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhnR?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[29]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[6].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{?X4Y2 (CLOCK_ROOT)y GCSFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/C JFDREXhzr> Jclock pessimismXh EASFP_GEN[6].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]Hold_GFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh8; J arrival timeXh?/ JXh4 JslackXhL=wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C)%SFP_GEN[6].rx_data_ngccm_reg[6][76]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu^d;>}o!=>?>#?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_HFF_SLICEM_C_Q JFDREXhzrD=U rx_data[6][76] Jnet (fo=1, routed)Xhp= >[ )%SFP_GEN[6].rx_data_ngccm_reg[6][76]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[6] Jnet (fo=674, routed)Xh"{?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[6].rx_data_ngccm_reg[6][76]/C JFDCEXhzr> Jclock pessimismXh-r '#SFP_GEN[6].rx_data_ngccm_reg[6][76]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXho; J arrival timeXh*\?/ JXh4 JslackXhHL=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[29]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[29]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu">} ͅt4R= p?t?gS=&9H=G=>/?>%?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[29]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[29] Jnet (fo=1, routed)XhG= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[29]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhQ?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[29]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh |?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[29]/C JFDCEXhzr> Jclock pessimismXh& c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[29]Hold_GFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh ͅ; J arrival timeXhj?/ JXh4 JslackXhgS=%sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu/$>}^SY=*\o?S?KT=&%=9=>?>0$?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/QProp_CFF2_SLICEL_C_Q JFDCEXhzfD= qmg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] Jnet (fo=28, routed)Xh= ieg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[20]_i_1__7/I0 JXhzf hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[20]_i_1__7/OProp_C6LUT_SLICEL_I0_O JLUT5Xhzru< `\g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg00[20] Jnet (fo=1, routed)Xho< eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh&Q?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhj|?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]/C JFDCEXhzr> Jclock pessimismXh& c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[20]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh^; J arrival timeXhI?/ JXh4 JslackXhKT=l!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsun@}Aw;+Attˡ-@t@A=А=nr@q3\>?7)@)?x??&?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhC? plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzru> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh?5> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr/> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5_n_0 Jnet (fo=1, routed)Xh= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhd;@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5?X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhq3\>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhw;+A; J arrival timeXh}?/ JXh4 JslackXhnr@ l!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsun@}Aw;+Attˡ-@t@A=А=nr@q3\>?7)@)?x??&?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhC? plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzru> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh?5> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr/> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__5_n_0 Jnet (fo=1, routed)Xh= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__5_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhd;@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5?X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhq3\>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhw;+A; J arrival timeXh}?/ JXh4 JslackXhnr@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[42]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsud;@}Ao-Ag_ˡ-@@A=А=lӀ@a[>?A@)?x?? ף?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/D[2] Jnet (fo=10, routed)XhA@ eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[42]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhd;@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[42]/C JFDCEXhzr> Jclock pessimismXha[>@ Jclock uncertaintyXh c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[42]Setup_DFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXho-A; J arrival timeXhJ / JXh4 JslackXhlӀ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[64]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu"@}A.-AMRYˡ-@M@A=А=@[>c?q=:@)?x???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[4]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[4] J GTHE3_CHANNELXhzrc? [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/D[4] Jnet (fo=6, routed)Xhq=:@ eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[64]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhd;@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[64]/C JFDCEXhzr> Jclock pessimismXh[>@ Jclock uncertaintyXh c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[64]Setup_DFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXh.-A; J arrival timeXh/ JXh4 JslackXh@~g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuz@}A++Attˡ-@t@A=А=@q3\>G?-"@)?x??&?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhC? plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzru> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh 0> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhd;@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhq3\>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh++A; J arrival timeXhY9/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[51]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu@}A_-Avcˡ-@@A=А=a@\>C?x9@)?x??S?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[9]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[9] J GTHE3_CHANNELXhzrC? \Xg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/D[11] Jnet (fo=6, routed)Xhx9@ eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[51]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhd;@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhNb?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[51]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[51]Setup_FFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXh_-A; J arrival timeXh5^/ JXh4 JslackXha@~g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu1t@}A&'+AQxˡ-@Q@A=А=@=\>G?W9@)?x??ף?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhC? plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzru> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh 0> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhO> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhd;@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh=\>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh&'+A; J arrival timeXh~?/ JXh4 JslackXh@ }g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsut@}A=++AQxˡ-@Q@A=А=7@=\>G?@)?x??ף?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhC? plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzru> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh 0> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhd;@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh=\>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh=++A; J arrival timeXh/ JXh4 JslackXh7@ }g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT5=1)j]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsut@}A=++AQxˡ-@Q@A=А=7@=\>G?@)?x??ף?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhC? plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/I0 JXhzf okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__5/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzru> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh 0> wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/I3 JXhzr vrg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__6/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhd;@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X4Y2 (CLOCK_ROOT) sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh=\>@ Jclock uncertaintyXh qmg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh=++A; J arrival timeXh/ JXh4 JslackXh7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[83]/D"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsut{@}Ag-Aoaˡ-@@A=А=:D@\>?&1@)?x???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/D[3] Jnet (fo=10, routed)Xh&1@ eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[83]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhd;@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh֣?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[83]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[83]Setup_CFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXhg-A; J arrival timeXhC/ JXh4 JslackXh:D@ &  gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9!)y@1y @9Ay@Iy @e^xD@hq}  =  >  ! rise - rise rise - rise  eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[38]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[38]/D"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuph>}8AoKH=ʑ?A? =nA9H=v=>> 7?X9>(\?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[38]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[38] Jnet (fo=1, routed)Xhv= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[38]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh!?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[38]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh"?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[38]/C JFDCEXhzr> Jclock pessimismXhnA c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[38]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh8; J arrival timeXh?/ JXh4 JslackXh =xg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C)%SFP_GEN[7].rx_data_ngccm_reg[7][38]/D"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu 0>}+١=a?? "=K9H=l=>}?5?X9>X?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[7][38] Jnet (fo=1, routed)Xhl=[ )%SFP_GEN[7].rx_data_ngccm_reg[7][38]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhʁ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xhx?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][38]/C JFDCEXhzr> Jclock pessimismXhKq '#SFP_GEN[7].rx_data_ngccm_reg[7][38]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh+١; J arrival timeXhy?/ JXh4 JslackXh "=)%SFP_GEN[7].rx_data_ngccm_reg[7][18]/C/+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/D"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu #>}nn/4_{=rh?/?.=x]D=A`=>E6?X9>V?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR)w )%SFP_GEN[7].rx_data_ngccm_reg[7][18]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD=v 3/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[83]_0[10] Jnet (fo=1, routed)XhA`=a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[7] Jnet (fo=674, routed)XhM?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][18]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr> Jclock pessimismXhx]x -)SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]Hold_AFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhnn; J arrival timeXhT?/ JXh4 JslackXh.=)%SFP_GEN[7].rx_data_ngccm_reg[7][47]/C/+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[46]/D"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuD>}x)\-<=?)\?2=U=X9=>!2?X9>5^Z?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR)v )%SFP_GEN[7].rx_data_ngccm_reg[7][47]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[83]_0[39] Jnet (fo=1, routed)Xh-=^ 0,SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[46]_i_1/I0 JXhzr /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[46]_i_1/OProp_D5LUT_SLICEL_I0_O JLUT3XhzrGa=t 1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[46]_i_1_n_0 Jnet (fo=1, routed)XhX94<a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[46]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][47]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhq=?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[46]/C JFDCEXhzr> Jclock pessimismXhUx -)SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[46]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhx; J arrival timeXh'1?/ JXh4 JslackXh2=g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuE6>} 3󭿭PO=??C=x]X9=Q=>z4?X9>PW?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_15_in Jnet (fo=2, routed)Xhw= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__6/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__6/OProp_H5LUT_SLICEM_I2_O JLUT3Xhzr #= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[6] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D JFDREXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhsh?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXhx] g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Hold_HFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh 3; J arrival timeXhK?/ JXh4 JslackXhC=ug_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C)%SFP_GEN[7].rx_data_ngccm_reg[7][21]/D"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu'>}{Nbu=أ?Nb?D=@9H==>k4?X9>j\?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=U rx_data[7][21] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[7].rx_data_ngccm_reg[7][21]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[7] Jnet (fo=674, routed)XhC?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][21]/C JFDCEXhzr> Jclock pessimismXh@q '#SFP_GEN[7].rx_data_ngccm_reg[7][21]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh{; J arrival timeXh̡?/ JXh4 JslackXhD=wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C)%SFP_GEN[7].rx_data_ngccm_reg[7][30]/D"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuC>}u$<߯!A=a?<߯?sF=G.9H=sh>>}?5?X9>[d[?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=U rx_data[7][30] Jnet (fo=1, routed)Xhsh>[ )%SFP_GEN[7].rx_data_ngccm_reg[7][30]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhʁ?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][30]/C JFDCEXhzr> Jclock pessimismXhG.r '#SFP_GEN[7].rx_data_ngccm_reg[7][30]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhu$; J arrival timeXhX?/ JXh4 JslackXhsF=)%SFP_GEN[7].rx_data_ngccm_reg[7][71]/C/+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[70]/D"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuw>}tܝwi5=$?w?G=/hH=Q8=>5?X9>"[?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR)v )%SFP_GEN[7].rx_data_ngccm_reg[7][71]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[83]_0[63] Jnet (fo=1, routed)XhC =^ 0,SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[70]_i_1/I0 JXhzr /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[70]_i_1/OProp_C5LUT_SLICEL_I0_O JLUT3XhzrGa=t 1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40[70]_i_1_n_0 Jnet (fo=1, routed)XhX94<a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[70]/D JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][71]/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[70]/C JFDCEXhzr> Jclock pessimismXh/hHx -)SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[70]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhtܝ; J arrival timeXh?/ JXh4 JslackXhG=eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[22]/Ceag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[22]/D"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsut>}󭿭$=??EuH=B9H=[=>z4?X9>PW?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[22]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[22] Jnet (fo=1, routed)Xh[= eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[22]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhsh?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[22]/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhԘ?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[22]/C JFDCEXhzr> Jclock pessimismXhB c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[22]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhEuH=vg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C)%SFP_GEN[7].rx_data_ngccm_reg[7][27]/D"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu(>}{Nbu=أ?Nb?GH=@D==>k4?X9>j\?y(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_BFF2_SLICEM_C_Q JFDREXhzrD=U rx_data[7][27] Jnet (fo=1, routed)Xh=[ )%SFP_GEN[7].rx_data_ngccm_reg[7][27]/D JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>l RX_WORDCLK_O[7] Jnet (fo=674, routed)XhC?X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][27]/C JFDCEXhzr> Jclock pessimismXh@q '#SFP_GEN[7].rx_data_ngccm_reg[7][27]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh{; J arrival timeXh¥?/ JXh4 JslackXhGH=n!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuO@}A1Aq=*>0@q=*@A=А=^xD@8d>`?-r@.??v?M?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhT=@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/OProp_C6LUT_SLICEL_I1_O JLUT4Xhzr> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhp=> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6/OProp_H6LUT_SLICEL_I2_O JLUT4Xhzr +> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6_n_0 Jnet (fo=1, routed)Xh= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6/OProp_F6LUT_SLICEL_I5_O JLUT6XhzrQ= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6_n_0 Jnet (fo=2, routed)Xh!> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh8d>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh^xD@ n!g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=2 LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuO@}A1Aq=*>0@q=*@A=А=^xD@8d>`?-r@.??v?M?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhT=@ plg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/I1 JXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__6/OProp_C6LUT_SLICEL_I1_O JLUT4Xhzr> sog_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhp=> njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6/I2 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6/OProp_H6LUT_SLICEL_I2_O JLUT4Xhzr +> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__6_n_0 Jnet (fo=1, routed)Xh= njg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6/I5 JXhzr mig_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6/OProp_F6LUT_SLICEL_I5_O JLUT6XhzrQ= okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__6_n_0 Jnet (fo=2, routed)Xh!> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT) jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh8d>@ Jclock uncertaintyXh hdg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh^xD@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[7].rx_data_ngccm_reg[7][69]/CE"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu@}A/2A(,? W=> 7@(,@A=А=E@ c>>̜@.?#?v?$?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(,@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6XhzrP>X rx_data_ngccm[7] Jnet (fo=76, routed)Xhp @\ *&SFP_GEN[7].rx_data_ngccm_reg[7][69]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][69]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXht '#SFP_GEN[7].rx_data_ngccm_reg[7][69]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh/2A; J arrival timeXh/ JXh4 JslackXhE@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[7].rx_data_ngccm_reg[7][49]/CE"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuz@}A~C2Az, k=> 7@z,@A=А=E@ c>>`@.?#?v??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(,@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6XhzrP>X rx_data_ngccm[7] Jnet (fo=76, routed)Xhˡ @\ *&SFP_GEN[7].rx_data_ngccm_reg[7][49]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][49]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXht '#SFP_GEN[7].rx_data_ngccm_reg[7][49]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh~C2A; J arrival timeXh/ JXh4 JslackXhE@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[7].rx_data_ngccm_reg[7][51]/CE"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuz@}A~C2Az, k=> 7@z,@A=А=E@ c>>`@.?#?v??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(,@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6XhzrP>X rx_data_ngccm[7] Jnet (fo=76, routed)Xhˡ @\ *&SFP_GEN[7].rx_data_ngccm_reg[7][51]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][51]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXht '#SFP_GEN[7].rx_data_ngccm_reg[7][51]Setup_FFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh~C2A; J arrival timeXh/ JXh4 JslackXhE@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[7].rx_data_ngccm_reg[7][58]/CE"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuR@}AN;2A(,? W=> 7@(,@A=А=VF@ c>>:@.?#?v?$?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(,@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6XhzrP>X rx_data_ngccm[7] Jnet (fo=76, routed)Xh}? @\ *&SFP_GEN[7].rx_data_ngccm_reg[7][58]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][58]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXhs '#SFP_GEN[7].rx_data_ngccm_reg[7][58]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhN;2A; J arrival timeXh9/ JXh4 JslackXhVF@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[7].rx_data_ngccm_reg[7][71]/CE"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuR@}AN;2A(,? W=> 7@(,@A=А=VF@ c>>:@.?#?v?$?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(,@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6XhzrP>X rx_data_ngccm[7] Jnet (fo=76, routed)Xh}? @\ *&SFP_GEN[7].rx_data_ngccm_reg[7][71]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][71]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXhs '#SFP_GEN[7].rx_data_ngccm_reg[7][71]Setup_FFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhN;2A; J arrival timeXh9/ JXh4 JslackXhVF@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[7].rx_data_ngccm_reg[7][48]/CE"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu@}AO2Az, k=> 7@z,@A=А==F@ c>>̜@.?#?v??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(,@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6XhzrP>X rx_data_ngccm[7] Jnet (fo=76, routed)Xhp @\ *&SFP_GEN[7].rx_data_ngccm_reg[7][48]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][48]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXhs '#SFP_GEN[7].rx_data_ngccm_reg[7][48]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhO2A; J arrival timeXh/ JXh4 JslackXh=F@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[7].rx_data_ngccm_reg[7][50]/CE"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu@}AO2Az, k=> 7@z,@A=А==F@ c>>̜@.?#?v??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(,@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6XhzrP>X rx_data_ngccm[7] Jnet (fo=76, routed)Xhp @\ *&SFP_GEN[7].rx_data_ngccm_reg[7][50]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][50]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXhs '#SFP_GEN[7].rx_data_ngccm_reg[7][50]Setup_FFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhO2A; J arrival timeXh/ JXh4 JslackXh=F@Lg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C*&SFP_GEN[7].rx_data_ngccm_reg[7][59]/CE"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu@}AO2Az, k=> 7@z,@A=А==F@ c>>̜@.?#?v??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(,@ uqg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/I0 JXhzr tpg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[7].rx_data_ngccm[7][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6XhzrP>X rx_data_ngccm[7] Jnet (fo=76, routed)Xhp @\ *&SFP_GEN[7].rx_data_ngccm_reg[7][59]/CE JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>l RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)[ )%SFP_GEN[7].rx_data_ngccm_reg[7][59]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXhs '#SFP_GEN[7].rx_data_ngccm_reg[7][59]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhO2A; J arrival timeXh/ JXh4 JslackXh=F@L  txoutclk_out[0]_49txoutclk_out[0]_49!)Ë>?1Ë>@9AË>?IË>@e8(?hq} P7< ѣ>  rise - rise rise - rise  F/+i_tcds2_if/txgearbox_inst/dataWord_reg[3]/Ci_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[3]"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZjAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsu-2>}|~,}c$Y?,}?P7<9H=>(\>?|>W9?k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})t(rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)| /+i_tcds2_if/txgearbox_inst/dataWord_reg[3]/QProp_BFF_SLICEM_C_Q JFDREXhzr9H= i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[3] Jnet (fo=1, routed)Xh> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[3] J GTHE3_CHANNELXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)Xh;?X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/txgearbox_inst/dataWord_reg[3]/C JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=539, routed)XhtS?X5Y0 (CLOCK_ROOT) i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST&Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[3] J GTHE3_CHANNELXh >/ JXh< J required timeXh|~; J arrival timeXh43?/ JXh4 JslackXhP7<M0,i_tcds2_if/txgearbox_inst/dataWord_reg[21]/Ci_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[21]"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZjAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsuD`e>}~,}!C<$Y?,}? q=*9H=333>(\>?|>W9?k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})t(rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)} 0,i_tcds2_if/txgearbox_inst/dataWord_reg[21]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[21] Jnet (fo=1, routed)Xh333> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[21] J GTHE3_CHANNELXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)Xh;?X5Y0 (CLOCK_ROOT)b 0,i_tcds2_if/txgearbox_inst/dataWord_reg[21]/C JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=539, routed)XhtS?X5Y0 (CLOCK_ROOT) i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh* i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[21] J GTHE3_CHANNELXhQ8>/ JXh< J required timeXh~; J arrival timeXh?/ JXh4 JslackXh q=-)i_tcds2_if/prbs_generator/data_o_reg[7]/CA=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[46]/D"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT6=1)jAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsu">}Qz𧆿=m[??K=Ho=\=(\>?|> #?k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR){ -)i_tcds2_if/prbs_generator/data_o_reg[7]/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H=q .*i_tcds2_if/txdatapath_inst/UPS/FEC5L0/Q[7] Jnet (fo=2, routed)Xhʡ=s EAi_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData[46]_i_1__2/I1 JXhzr D@i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData[46]_i_1__2/OProp_C6LUT_SLICEL_I1_O JLUT6Xhzru< FBi_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData[46]_i_1__2_n_0 Jnet (fo=1, routed)Xho<s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[46]/D JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh.=?X5Y0 (CLOCK_ROOT)_ -)i_tcds2_if/prbs_generator/data_o_reg[7]/C JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> -)i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK Jnet (fo=539, routed)Xhoc?X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[46]/C JFDREXhzr> Jclock pessimismXhH ?;i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[46]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhQz; J arrival timeXhM?/ JXh4 JslackXhK=M0,i_tcds2_if/txgearbox_inst/dataWord_reg[19]/Ci_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[19]"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZjAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsu@>}ỳ,}î"[?,}?]=Bs9H=V>(\>U?|>W9?k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})t(rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)} 0,i_tcds2_if/txgearbox_inst/dataWord_reg[19]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H= i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[19] Jnet (fo=1, routed)XhV> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[19] J GTHE3_CHANNELXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)Xh i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=539, routed)XhtS?X5Y0 (CLOCK_ROOT) i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXhBs i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[19] J GTHE3_CHANNELXhV->/ JXh< J required timeXhỳ; J arrival timeXh̡?/ JXh4 JslackXh]=M0,i_tcds2_if/txgearbox_inst/dataWord_reg[12]/Ci_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[12]"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZjAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsuhff>}IF,}ꭅ: \?,}?=2 9H=X94>(\>l?|>W9?k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})t(rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)} 0,i_tcds2_if/txgearbox_inst/dataWord_reg[12]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H= i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[12] Jnet (fo=1, routed)XhX94> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[12] J GTHE3_CHANNELXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)Xhv>?X5Y0 (CLOCK_ROOT)b 0,i_tcds2_if/txgearbox_inst/dataWord_reg[12]/C JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=539, routed)XhtS?X5Y0 (CLOCK_ROOT) i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh2  i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[12] J GTHE3_CHANNELXhv>>/ JXh< J required timeXhIF; J arrival timeXh"?/ JXh4 JslackXh=M0,i_tcds2_if/txgearbox_inst/dataWord_reg[10]/Ci_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[10]"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZjAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsuE6>}0B,}ꭅ: \?,}?=2 9H=>(\>l?|>W9?k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})t(rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)} 0,i_tcds2_if/txgearbox_inst/dataWord_reg[10]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[10] Jnet (fo=1, routed)Xh> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[10] J GTHE3_CHANNELXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)Xhv>?X5Y0 (CLOCK_ROOT)b 0,i_tcds2_if/txgearbox_inst/dataWord_reg[10]/C JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=539, routed)XhtS?X5Y0 (CLOCK_ROOT) i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh2  i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[10] J GTHE3_CHANNELXhV>/ JXh< J required timeXh0B; J arrival timeXh?/ JXh4 JslackXh=M0,i_tcds2_if/txgearbox_inst/dataWord_reg[27]/Ci_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[27]"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZjAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsuxi>}ff,}MD;(\?,}?=oD=Q8>(\>y?|>W9?k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})t(rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)} 0,i_tcds2_if/txgearbox_inst/dataWord_reg[27]/QProp_HFF_SLICEL_C_Q JFDREXhzrD= i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[27] Jnet (fo=1, routed)XhQ8> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[27] J GTHE3_CHANNELXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)Xh=?X5Y0 (CLOCK_ROOT)b 0,i_tcds2_if/txgearbox_inst/dataWord_reg[27]/C JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=539, routed)XhtS?X5Y0 (CLOCK_ROOT) i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXho i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[27] J GTHE3_CHANNELXh|?>/ JXh< J required timeXhff; J arrival timeXhC?/ JXh4 JslackXh=F/+i_tcds2_if/txgearbox_inst/dataWord_reg[8]/Ci_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[8]"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZjAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsuL>}\,}MD;(\?,}? #=oD=>(\>y?|>W9?k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})t(rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)| /+i_tcds2_if/txgearbox_inst/dataWord_reg[8]/QProp_HFF_SLICEL_C_Q JFDREXhzrD= i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[8] Jnet (fo=1, routed)Xh> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[8] J GTHE3_CHANNELXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)Xh=?X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/txgearbox_inst/dataWord_reg[8]/C JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=539, routed)XhtS?X5Y0 (CLOCK_ROOT) i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXho i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST&Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[8] J GTHE3_CHANNELXh >/ JXh< J required timeXh\; J arrival timeXh?/ JXh4 JslackXh #=51i_tcds2_if/txgearbox_inst/gearboxCounter_reg[2]/C/+i_tcds2_if/txgearbox_inst/dataWord_reg[8]/D"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZ (MUXF7=1)jAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsuZd;>}`~'1 =Y?'1? &=C==(\>Z?|>y&?k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR) 51i_tcds2_if/txgearbox_inst/gearboxCounter_reg[2]/QProp_HFF2_SLICEM_C_Q JFDREXhzrD= <8i_tcds2_if/txdatapath_inst/UPS/FEC5L1/dataWord_reg[0][2] Jnet (fo=34, routed)Xh`=m ?;i_tcds2_if/txdatapath_inst/UPS/FEC5L1/dataWord_reg[8]_i_1/S JXhzr ?;i_tcds2_if/txdatapath_inst/UPS/FEC5L1/dataWord_reg[8]_i_1/OProp_F7MUX_GH_SLICEL_S_O JMUXF7Xhzr ף<e "i_tcds2_if/txgearbox_inst/D[8] Jnet (fo=1, routed)XhT<a /+i_tcds2_if/txgearbox_inst/dataWord_reg[8]/D JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)XhZd;?X5Y0 (CLOCK_ROOT)g 51i_tcds2_if/txgearbox_inst/gearboxCounter_reg[2]/C JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh)\= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)Xh$f?X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/txgearbox_inst/dataWord_reg[8]/C JFDREXhzr> Jclock pessimismXhw -)i_tcds2_if/txgearbox_inst/dataWord_reg[8]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh`~; J arrival timeXhX9?/ JXh4 JslackXh &="M0,i_tcds2_if/txgearbox_inst/dataWord_reg[23]/Ci_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[23]"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZjAtxoutclk_out[0]_49 rise@0.000ns - txoutclk_out[0]_49 rise@0.000nsuT>},}î"[?,}??%/=Bs9H=">(\>U?|>W9?k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})t(rising edge-triggered cell GTHE3_CHANNEL clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Fasttxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49(DCD - SCD - CPR)} 0,i_tcds2_if/txgearbox_inst/dataWord_reg[23]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H= i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[23] Jnet (fo=1, routed)Xh"> i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[23] J GTHE3_CHANNELXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xht< WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=z !i_tcds2_if/txgearbox_inst/CLK Jnet (fo=539, routed)Xh i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txusrclk2_in[0] Jnet (fo=539, routed)XhtS?X5Y0 (CLOCK_ROOT) i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXhBs i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[23] J GTHE3_CHANNELXhj<>/ JXh< J required timeXh; J arrival timeXh(1?/ JXh4 JslackXh?%/=XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C/+i_tcds2_if/prbs_generator/data_o_reg[150]/R"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT3=1)jAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsu@}G@i@aE@a@G@=А=8(?>>>?A??>/ݤ?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>q ,(ctrl_regs_inst/gtwiz_reset_tx_done_in[0] Jnet (fo=273, routed)Xh;?V ($ctrl_regs_inst/data_o[233]_i_1__0/I2 JXhzfw '#ctrl_regs_inst/data_o[233]_i_1__0/OProp_B6LUT_SLICEL_I2_O JLUT3Xhzr!r>h #i_tcds2_if/prbs_generator/SR[0] Jnet (fo=234, routed)XhE?a /+i_tcds2_if/prbs_generator/data_o_reg[150]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhe;?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh?X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[150]/C JFDREXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXhx -)i_tcds2_if/prbs_generator/data_o_reg[150]Setup_DFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXhi@; J arrival timeXhb/ JXh4 JslackXh8(?XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C/+i_tcds2_if/prbs_generator/data_o_reg[184]/R"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT3=1)jAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsu@}G@i@aE@a@G@=А=8(?>>>?A??>/ݤ?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>q ,(ctrl_regs_inst/gtwiz_reset_tx_done_in[0] Jnet (fo=273, routed)Xh;?V ($ctrl_regs_inst/data_o[233]_i_1__0/I2 JXhzfw '#ctrl_regs_inst/data_o[233]_i_1__0/OProp_B6LUT_SLICEL_I2_O JLUT3Xhzr!r>h #i_tcds2_if/prbs_generator/SR[0] Jnet (fo=234, routed)XhE?a /+i_tcds2_if/prbs_generator/data_o_reg[184]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhe;?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh?X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[184]/C JFDREXhzr> Jclock pessimismXh>>@ Jclock uncertaintyXhx -)i_tcds2_if/prbs_generator/data_o_reg[184]Setup_CFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXhi@; J arrival timeXhb/ JXh4 JslackXh8(?i_tcds2_if/tx_strobe_reg/CB>i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[43]/CE"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZjAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsu^ @}G@s@  R5^a @  @G@=А=)?=I >@A?1?>?k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)l i_tcds2_if/tx_strobe_reg/QProp_HFF2_SLICEL_C_Q JFDREXhzrI >s .*i_tcds2_if/txdatapath_inst/UPS/FEC5L0/E[0] Jnet (fo=492, routed)Xh@t B>i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[43]/CE JFDSEXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>t i_tcds2_if/txusrclk_out Jnet (fo=539, routed)Xh~@X5Y0 (CLOCK_ROOT)P i_tcds2_if/tx_strobe_reg/C JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> -)i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK Jnet (fo=539, routed)Xhn?X5Y0 (CLOCK_ROOT)s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[43]/C JFDSEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXh ?;i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[43]Setup_DFF_SLICEL_C_CE JFDSEXh/]/ JXh< J required timeXhs@; J arrival timeXhO/ JXh4 JslackXh)?i_tcds2_if/tx_strobe_reg/CA=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[4]/CE"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZjAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsu^ @}G@s@  R5^a @  @G@=А=)?=I >@A?1?>?k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDSE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)l i_tcds2_if/tx_strobe_reg/QProp_HFF2_SLICEL_C_Q JFDREXhzrI >s .*i_tcds2_if/txdatapath_inst/UPS/FEC5L0/E[0] Jnet (fo=492, routed)Xh@s A=i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[4]/CE JFDSEXhzrV J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>t i_tcds2_if/txusrclk_out Jnet (fo=539, routed)Xh~@X5Y0 (CLOCK_ROOT)P i_tcds2_if/tx_strobe_reg/C JFDREXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> -)i_tcds2_if/txdatapath_inst/UPS/FEC5L0/CLK Jnet (fo=539, routed)Xhn?X5Y0 (CLOCK_ROOT)r @ Jclock pessimismXh=@ Jclock uncertaintyXh >:i_tcds2_if/txdatapath_inst/UPS/FEC5L0/scrambledData_reg[4]Setup_CFF_SLICEL_C_CE JFDSEXh/]/ JXh< J required timeXhs@; J arrival timeXhO/ JXh4 JslackXh)?XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C/+i_tcds2_if/prbs_generator/data_o_reg[147]/R"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT3=1)jAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsuG@}G@@rȆa@r@G@=А=)?qZ>>n?A??>?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>q ,(ctrl_regs_inst/gtwiz_reset_tx_done_in[0] Jnet (fo=273, routed)Xh;?V ($ctrl_regs_inst/data_o[233]_i_1__0/I2 JXhzfw '#ctrl_regs_inst/data_o[233]_i_1__0/OProp_B6LUT_SLICEL_I2_O JLUT3Xhzr!r>h #i_tcds2_if/prbs_generator/SR[0] Jnet (fo=234, routed)Xh?a /+i_tcds2_if/prbs_generator/data_o_reg[147]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhe;?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh?X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[147]/C JFDREXhzr> Jclock pessimismXhqZ>@ Jclock uncertaintyXhx -)i_tcds2_if/prbs_generator/data_o_reg[147]Setup_HFF_SLICEL_C_R JFDREXh\½/ JXh< J required timeXh@; J arrival timeXh㥗/ JXh4 JslackXh)?XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C/+i_tcds2_if/prbs_generator/data_o_reg[153]/R"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT3=1)jAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsuG@}G@@rȆa@r@G@=А=)?qZ>>n?A??>?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>q ,(ctrl_regs_inst/gtwiz_reset_tx_done_in[0] Jnet (fo=273, routed)Xh;?V ($ctrl_regs_inst/data_o[233]_i_1__0/I2 JXhzfw '#ctrl_regs_inst/data_o[233]_i_1__0/OProp_B6LUT_SLICEL_I2_O JLUT3Xhzr!r>h #i_tcds2_if/prbs_generator/SR[0] Jnet (fo=234, routed)Xh?a /+i_tcds2_if/prbs_generator/data_o_reg[153]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhe;?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh?X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[153]/C JFDREXhzr> Jclock pessimismXhqZ>@ Jclock uncertaintyXhx -)i_tcds2_if/prbs_generator/data_o_reg[153]Setup_GFF_SLICEL_C_R JFDREXh\½/ JXh< J required timeXh@; J arrival timeXh㥗/ JXh4 JslackXh)?XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C/+i_tcds2_if/prbs_generator/data_o_reg[187]/R"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT3=1)jAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsuG@}G@@rȆa@r@G@=А=)?qZ>>n?A??>?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>q ,(ctrl_regs_inst/gtwiz_reset_tx_done_in[0] Jnet (fo=273, routed)Xh;?V ($ctrl_regs_inst/data_o[233]_i_1__0/I2 JXhzfw '#ctrl_regs_inst/data_o[233]_i_1__0/OProp_B6LUT_SLICEL_I2_O JLUT3Xhzr!r>h #i_tcds2_if/prbs_generator/SR[0] Jnet (fo=234, routed)Xh?a /+i_tcds2_if/prbs_generator/data_o_reg[187]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhe;?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh?X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[187]/C JFDREXhzr> Jclock pessimismXhqZ>@ Jclock uncertaintyXhx -)i_tcds2_if/prbs_generator/data_o_reg[187]Setup_FFF_SLICEL_C_R JFDREXh\½/ JXh< J required timeXh@; J arrival timeXh㥗/ JXh4 JslackXh)?XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C/+i_tcds2_if/prbs_generator/data_o_reg[220]/R"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT3=1)jAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsu}? @}G@ߪ@& sｵ@& @G@=А=)?V>>5^?A??>A`?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>q ,(ctrl_regs_inst/gtwiz_reset_tx_done_in[0] Jnet (fo=273, routed)Xh;?V ($ctrl_regs_inst/data_o[233]_i_1__0/I2 JXhzfw '#ctrl_regs_inst/data_o[233]_i_1__0/OProp_B6LUT_SLICEL_I2_O JLUT3Xhzr!r>h #i_tcds2_if/prbs_generator/SR[0] Jnet (fo=234, routed)XhD?a /+i_tcds2_if/prbs_generator/data_o_reg[220]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhe;?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh(\?X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[220]/C JFDREXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXhx -)i_tcds2_if/prbs_generator/data_o_reg[220]Setup_BFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXhߪ@; J arrival timeXhˡ/ JXh4 JslackXh)?XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C/+i_tcds2_if/prbs_generator/data_o_reg[135]/R"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT3=1)jAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsuB` @}G@@x P彵@x @G@=А=**? V>>?A??>?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>q ,(ctrl_regs_inst/gtwiz_reset_tx_done_in[0] Jnet (fo=273, routed)Xh;?V ($ctrl_regs_inst/data_o[233]_i_1__0/I2 JXhzfw '#ctrl_regs_inst/data_o[233]_i_1__0/OProp_B6LUT_SLICEL_I2_O JLUT3Xhzr!r>h #i_tcds2_if/prbs_generator/SR[0] Jnet (fo=234, routed)Xȟ?a /+i_tcds2_if/prbs_generator/data_o_reg[135]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhe;?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh?X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[135]/C JFDREXhzr> Jclock pessimismXh V>@ Jclock uncertaintyXhx -)i_tcds2_if/prbs_generator/data_o_reg[135]Setup_DFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXh@; J arrival timeXh-/ JXh4 JslackXh**?XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C/+i_tcds2_if/prbs_generator/data_o_reg[175]/R"!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT*X5Y02!RCLK_CLEL_L_X82Y89/CLK_VDISTR_BOT:X5Y0BJZ(LUT3=1)jAtxoutclk_out[0]_49 rise@3.119ns - txoutclk_out[0]_49 rise@0.000nsuB` @}G@@x P彵@x @G@=А=**? V>>?A??>?k(rising edge-triggered cell FDCE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})k(rising edge-triggered cell FDRE clocked by txoutclk_out[0]_49 {rise@0.000ns fall@1.559ns period=3.119ns})Slowtxoutclk_out[0]_49txoutclk_out[0]_49txoutclk_out[0]_49#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzfV>q ,(ctrl_regs_inst/gtwiz_reset_tx_done_in[0] Jnet (fo=273, routed)Xh;?V ($ctrl_regs_inst/data_o[233]_i_1__0/I2 JXhzfw '#ctrl_regs_inst/data_o[233]_i_1__0/OProp_B6LUT_SLICEL_I2_O JLUT3Xhzr!r>h #i_tcds2_if/prbs_generator/SR[0] Jnet (fo=234, routed)Xȟ?a /+i_tcds2_if/prbs_generator/data_o_reg[175]/R JFDREXhzr V J$(clock txoutclk_out[0]_49 rise edge)Xhzr i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)Xh5^= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXhzr WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_sync3_reg_0 Jnet (fo=539, routed)Xhe;?X5Y0 (CLOCK_ROOT) XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_tx_done_inst/rst_in_out_reg/C JFDCEXhzrV J$(clock txoutclk_out[0]_49 rise edge)XhzrG@ i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK J GTHE3_CHANNELXhzrz 73i_tcds2_if/i_mgt_wrapper/i_txusrclk/txoutclk_out[0] Jnet (fo=2, routed)XhT= WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/I JXh WSi_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>z !i_tcds2_if/prbs_generator/CLK Jnet (fo=539, routed)Xh?X5Y0 (CLOCK_ROOT)a /+i_tcds2_if/prbs_generator/data_o_reg[175]/C JFDREXhzr> Jclock pessimismXh V>@ Jclock uncertaintyXhx -)i_tcds2_if/prbs_generator/data_o_reg[175]Setup_CFF_SLICEL_C_R JFDREXhĽ/ JXh< J required timeXh@; J arrival timeXh-/ JXh4 JslackXh**?( !gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!)y@1y @9Ay@Iy @e'A@hq}  = > rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C+'SFP_GEN[12].rx_data_ngccm_reg[12][45]/D""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu433>} ꟿ1=ҍ?1? =>ID=I >">;/? >U?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_CFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[12][45] Jnet (fo=1, routed)XhI >] +'SFP_GEN[12].rx_data_ngccm_reg[12][45]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp}?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[1].gbtbank_n_0 Jnet (fo=674, routed)Xhy?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[12].rx_data_ngccm_reg[12][45]/C JFDCEXhzr> Jclock pessimismXh>Is )%SFP_GEN[12].rx_data_ngccm_reg[12][45]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh ꟿ; J arrival timeXhW9?/ JXh4 JslackXh =g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C+'SFP_GEN[12].rx_data_ngccm_reg[12][76]/D""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu 0>}Z~%=?~?p=oxD==">{.? >"R?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_HFF_SLICEL_C_Q JFDREXhzrD=V rx_data[12][76] Jnet (fo=1, routed)Xh=] +'SFP_GEN[12].rx_data_ngccm_reg[12][76]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh{?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[1].gbtbank_n_0 Jnet (fo=674, routed)XhB`?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[12].rx_data_ngccm_reg[12][76]/C JFDCEXhzr> Jclock pessimismXhoxs )%SFP_GEN[12].rx_data_ngccm_reg[12][76]Hold_FFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhZ; J arrival timeXh?/ JXh4 JslackXhp=/*&SFP_GEN[12].rx_data_ngccm_reg[12][4]/C/+SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[4]/D""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu)>}L7=j?L7?[j=v=X9=">V-? > P?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)w *&SFP_GEN[12].rx_data_ngccm_reg[12][4]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD=v 3/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[4] Jnet (fo=1, routed)XhP=^ 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[4]_i_1/I1 JXhzr /+SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[4]_i_1/OProp_G6LUT_SLICEM_I1_O JLUT3Xhzr<t 1-SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[4]_i_1_n_0 Jnet (fo=1, routed)XhA`e<a /+SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[4]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=v g_gbt_bank[1].gbtbank_n_0 Jnet (fo=674, routed)Xhz?X4Y7 (CLOCK_ROOT)\ *&SFP_GEN[12].rx_data_ngccm_reg[12][4]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)a /+SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[4]/C JFDCEXhzr> Jclock pessimismXhw -)SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[4]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh[j=<+'SFP_GEN[12].rx_data_ngccm_reg[12][47]/C0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[46]/D""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuK7>} ꟿ1=ҍ?1?K=>IE=Q=">;/? >U?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)x +'SFP_GEN[12].rx_data_ngccm_reg[12][47]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[39] Jnet (fo=1, routed)Xhw=_ 1-SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[46]_i_1/I0 JXhzr 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[46]_i_1/OProp_D5LUT_SLICEM_I0_O JLUT3Xhzr #=u 2.SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[46]_i_1_n_0 Jnet (fo=1, routed)XhD<b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[46]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=v g_gbt_bank[1].gbtbank_n_0 Jnet (fo=674, routed)Xhp}?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[12].rx_data_ngccm_reg[12][47]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[46]/C JFDCEXhzr> Jclock pessimismXh>Iy .*SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[46]Hold_DFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh ꟿ; J arrival timeXhj?/ JXh4 JslackXhK=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu-2>}ȝf.=O??0=m ף==">.? >33S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xhw= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__11/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__11/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj|?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhˡ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXhm g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhȝ; J arrival timeXh?/ JXh4 JslackXh0=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu 0>}H=-??7=.sʡ=v=">/? >Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xh-= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__11/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__11/OProp_D6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/}?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh.s g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhH; J arrival timeXhF?/ JXh4 JslackXh7=;+'SFP_GEN[12].rx_data_ngccm_reg[12][45]/C0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[44]/D""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu/>}{1%W=?5?1?Q9=ȥ8=`P=">ף0? >U?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)x +'SFP_GEN[12].rx_data_ngccm_reg[12][45]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[37] Jnet (fo=1, routed)Xh)\=_ 1-SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[44]_i_1/I0 JXhzr 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[44]_i_1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr/]=u 2.SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[44]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[44]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=v g_gbt_bank[1].gbtbank_n_0 Jnet (fo=674, routed)Xh@5~?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[12].rx_data_ngccm_reg[12][45]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[44]/C JFDCEXhzr> Jclock pessimismXhȥ8x .*SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[44]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh{; J arrival timeXh?/ JXh4 JslackXhQ9=;+'SFP_GEN[12].rx_data_ngccm_reg[12][32]/C0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]/D""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu/>}~W=̌?~?o9=7=`P=">-? >"R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)x +'SFP_GEN[12].rx_data_ngccm_reg[12][32]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[24] Jnet (fo=1, routed)Xh)\=_ 1-SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[32]_i_1/I1 JXhzr 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[32]_i_1/OProp_D6LUT_SLICEM_I1_O JLUT3Xhzr/]=u 2.SFP_GEN[12].ngCCM_gbt/RX_Word_rx40[32]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=v g_gbt_bank[1].gbtbank_n_0 Jnet (fo=674, routed)Xh[d{?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[12].rx_data_ngccm_reg[12][32]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[12].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXh7x .*SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXho9=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu-2>}H=-???=.s =X9=">/? >Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xh-= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__11/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__11/OProp_C5LUT_SLICEL_I2_O JLUT3Xhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)XhX94< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/}?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr> Jclock pessimismXh.s g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhH; J arrival timeXh?/ JXh4 JslackXh?=.sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[37]/D""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu #>} כƫlg=p?ƫ?]B=8=\=">/? >~?U?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/QProp_DFF2_SLICEM_C_Q JFDCEXhzf9H= qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] Jnet (fo=28, routed)Xh ף= jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0[37]_i_1__13/I0 JXhzf ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0[37]_i_1__13/OProp_B6LUT_SLICEM_I0_O JLUT5Xhzro< `\g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg00[37] Jnet (fo=1, routed)Xhu< eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[37]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh |?X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[37]/C JFDCEXhzr> Jclock pessimismXh8 c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[37]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh כ; J arrival timeXh?/ JXh4 JslackXh]B=U!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu!@}A"1A'T=.@'@A=А='A@ad>8?l@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] Jnet (fo=10, routed)XhZ4@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11/OProp_D5LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11_n_0 Jnet (fo=1, routed)Xh> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11/OProp_H6LUT_SLICEL_I5_O JLUT6XhzrY= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11_n_0 Jnet (fo=2, routed)Xh}> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh?5@X4Y7 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh"1A; J arrival timeXh/ JXh4 JslackXh'A@ U!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu!@}A"1A'T=.@'@A=А='A@ad>8?l@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] Jnet (fo=10, routed)XhZ4@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11/OProp_D5LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__11_n_0 Jnet (fo=1, routed)Xh> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11/OProp_H6LUT_SLICEL_I5_O JLUT6XhzrY= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__11_n_0 Jnet (fo=2, routed)Xh}> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh?5@X4Y7 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh"1A; J arrival timeXh/ JXh4 JslackXh'A@ qg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu}?@}A0A= 's=.@= '@A=А="[@ad>?j\@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] Jnet (fo=10, routed)XhZ4@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhw> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xhh @X4Y7 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh0A; J arrival timeXhA/ JXh4 JslackXh"[@ bg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuB`@}A0A'Ȕ=.@'@A=А=P3[@ad>?\@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] Jnet (fo=10, routed)XhZ4@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhX9= xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__12/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__12/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh1 ? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xhˡ @X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh0A; J arrival timeXhOb/ JXh4 JslackXhP3[@ cg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuB`@}A0A+'=.@+'@A=А=T3[@ad>?\@*?$??z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] Jnet (fo=10, routed)XhZ4@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhX9= xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__12/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__12/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh1 ? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh- @X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXhOb/ JXh4 JslackXhT3[@ bg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu}?@}A1A+'=.@+'@A=А=>[@ad>?k\@*?$??z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] Jnet (fo=10, routed)XhZ4@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhX9= xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__12/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__12/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh  ? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh- @X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh1A; J arrival timeXhA/ JXh4 JslackXh>[@ pg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu@}A0A= 's=.@= '@A=А=[@ad>?z\@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] Jnet (fo=10, routed)XhZ4@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh-> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xhh @X4Y7 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh / JXh4 JslackXh[@ pg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu@}A0A= 's=.@= '@A=А=[@ad>?z\@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] Jnet (fo=10, routed)XhZ4@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhF> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__12/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh-> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xhh @X4Y7 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh / JXh4 JslackXh[@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuM@}A1A'T=.@'@A=А=Aa@ad>㥻?V@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] Jnet (fo=10, routed)XhZ4@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzf֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhG> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh?5@X4Y7 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXhO/ JXh4 JslackXhAa@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuM@}A1A'T=.@'@A=А=Aa@ad>㥻?V@*?$???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? gcg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[2] Jnet (fo=10, routed)XhZ4@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__11/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzf֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhG> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__12/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh?5@X4Y7 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhad>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_BFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXhO/ JXh4 JslackXhAa@ ( !gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!)y@1y @9Ay@Iy @e@hq}  <  >% rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C+'SFP_GEN[22].rx_data_ngccm_reg[22][64]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu)>}Ll$*l` >@*@ <mCe"= 0>`?ƫ?|?:?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_CFF_SLICEL_C_Q JFDREXhzr"=V rx_data[22][64] Jnet (fo=1, routed)Xh 0>] +'SFP_GEN[22].rx_data_ngccm_reg[22][64]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX9?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)XhX9 @X4Y9 (CLOCK_ROOT)] +'SFP_GEN[22].rx_data_ngccm_reg[22][64]/C JFDCEXhzr> Jclock pessimismXhmCet )%SFP_GEN[22].rx_data_ngccm_reg[22][64]Hold_EFF2_SLICEL_C_D JFDCEXhI >/ JXh< J required timeXhLl$; J arrival timeXhff&@/ JXh4 JslackXh <g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C+'SFP_GEN[22].rx_data_ngccm_reg[22][57]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsut>}Qʑ?=m?ʑ?w(= '9H=\=>q= ?d;>^)?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H=V rx_data[22][57] Jnet (fo=1, routed)Xh\=] +'SFP_GEN[22].rx_data_ngccm_reg[22][57]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)XhXy?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[22].rx_data_ngccm_reg[22][57]/C JFDCEXhzr> Jclock pessimismXh 't )%SFP_GEN[22].rx_data_ngccm_reg[22][57]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhQ; J arrival timeXhX?/ JXh4 JslackXhw(=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsut>}!vsho,=k?sh?Dy;=0=L=>'1?d;>(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)XhC = g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__21/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__21/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhhM?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhvx?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh0 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh!v; J arrival timeXhQ?/ JXh4 JslackXhDy;=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu">}g%ϼc=q=j?%?y&B=1L&v=T=>?d;>'1(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)XhO= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__21/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__21/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh2L?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh1L& g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhg; J arrival timeXhx?/ JXh4 JslackXhy&B=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuph>}a吿=2l?a?KC=/=D=>r?d;>'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__21/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__21/OProp_E6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhM?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhPw?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh/ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_EFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh'1?/ JXh4 JslackXhKC=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuz>}ٙsh:?d;>(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__21/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__21/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh{N?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhvx?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh/ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhٙ; J arrival timeXh:?/ JXh4 JslackXhLC=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu>}:Mo,=Om?M?_C=1=T=>_ ?d;>*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__21/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__21/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh5^z?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXh1 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh:; J arrival timeXhX?/ JXh4 JslackXh_C=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu>}J o,=Vm?J ?_C=0=T=>x ?d;>r=*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_9_in Jnet (fo=2, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__21/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__21/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhN?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh$y?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh0 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhK7?/ JXh4 JslackXh_C=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C+'SFP_GEN[22].rx_data_ngccm_reg[22][34]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuz>}a吿1%=k?a?G=/D==>?d;>'?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_HFF_SLICEM_C_Q JFDREXhzrD=V rx_data[22][34] Jnet (fo=1, routed)Xh=] +'SFP_GEN[22].rx_data_ngccm_reg[22][34]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhOM?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)XhPw?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[22].rx_data_ngccm_reg[22][34]/C JFDCEXhzr> Jclock pessimismXh/t )%SFP_GEN[22].rx_data_ngccm_reg[22][34]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhQ?/ JXh4 JslackXhG=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsut>}a吿=2l?a?.}K=/=L=>r?d;>'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__21/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__21/OProp_G6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)XhA`e< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhM?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhPw?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh/ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhr?/ JXh4 JslackXh.}K=}!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu@}A,Awѽr(@@A=А=@/d>S?6^@|?Z?`?ƫ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh2? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/I0 JXhzf qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzru> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'1> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21/I2 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzrx> qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21_n_0 Jnet (fo=1, routed)XhV-> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21/I5 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr&1> qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21_n_0 Jnet (fo=2, routed)Xh> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)XhX9?X4Y9 (CLOCK_ROOT) kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh/d>@ Jclock uncertaintyXh ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh,A; J arrival timeXhp=/ JXh4 JslackXh@ }!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu@}A,Awѽr(@@A=А=@/d>S?6^@|?Z?`?ƫ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh2? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/I0 JXhzf qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__21/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzru> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh'1> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21/I2 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzrx> qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__21_n_0 Jnet (fo=1, routed)XhV-> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21/I5 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr&1> qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__21_n_0 Jnet (fo=2, routed)Xh> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)XhX9?X4Y9 (CLOCK_ROOT) kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh/d>@ Jclock uncertaintyXh ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh,A; J arrival timeXhp=/ JXh4 JslackXh@ FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C/+SFP_GEN[22].ngccm_status_reg_reg[22][23]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu(@}Ax0Ah%=+@h%@A=А=@`[>>u@|?~?`?v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh1D@s EASFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/I1 JXhzr D@SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/OProp_H6LUT_SLICEL_I1_O JLUT2Xhzr+>_ rx_test_comm_cnt259_out Jnet (fo=18, routed)XhG?a /+SFP_GEN[22].ngccm_status_reg_reg[22][23]/CE JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT)` .*SFP_GEN[22].ngccm_status_reg_reg[22][23]/C JFDPEXhzr> Jclock pessimismXh`[>@ Jclock uncertaintyXhx ,(SFP_GEN[22].ngccm_status_reg_reg[22][23]Setup_DFF_SLICEM_C_CE JFDPEXh/]/ JXh< J required timeXhx0A; J arrival timeXh/ JXh4 JslackXh@FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C.*SFP_GEN[22].ngccm_status_reg_reg[22][1]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsurh@}A0A+&! >+@+&@A=А=@ @`[>>rp@|?~?`??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh1D@s EASFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/I1 JXhzr D@SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/OProp_H6LUT_SLICEL_I1_O JLUT2Xhzr+>_ rx_test_comm_cnt259_out Jnet (fo=18, routed)Xh1?` .*SFP_GEN[22].ngccm_status_reg_reg[22][1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)XhU @X4Y9 (CLOCK_ROOT)_ -)SFP_GEN[22].ngccm_status_reg_reg[22][1]/C JFDCEXhzr> Jclock pessimismXh`[>@ Jclock uncertaintyXhx +'SFP_GEN[22].ngccm_status_reg_reg[22][1]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh0A; J arrival timeXh+/ JXh4 JslackXh@ @FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C.*SFP_GEN[22].ngccm_status_reg_reg[22][4]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsurh@}A0A+&! >+@+&@A=А=@ @`[>>rp@|?~?`??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh1D@s EASFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/I1 JXhzr D@SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/OProp_H6LUT_SLICEL_I1_O JLUT2Xhzr+>_ rx_test_comm_cnt259_out Jnet (fo=18, routed)Xh1?` .*SFP_GEN[22].ngccm_status_reg_reg[22][4]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)XhU @X4Y9 (CLOCK_ROOT)_ -)SFP_GEN[22].ngccm_status_reg_reg[22][4]/C JFDCEXhzr> Jclock pessimismXh`[>@ Jclock uncertaintyXhx +'SFP_GEN[22].ngccm_status_reg_reg[22][4]Setup_FFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh0A; J arrival timeXh+/ JXh4 JslackXh@ @FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C.*SFP_GEN[22].ngccm_status_reg_reg[22][6]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsurh@}A0A+&! >+@+&@A=А=@ @`[>>rp@|?~?`??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh1D@s EASFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/I1 JXhzr D@SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/OProp_H6LUT_SLICEL_I1_O JLUT2Xhzr+>_ rx_test_comm_cnt259_out Jnet (fo=18, routed)Xh1?` .*SFP_GEN[22].ngccm_status_reg_reg[22][6]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)XhU @X4Y9 (CLOCK_ROOT)_ -)SFP_GEN[22].ngccm_status_reg_reg[22][6]/C JFDCEXhzr> Jclock pessimismXh`[>@ Jclock uncertaintyXhx +'SFP_GEN[22].ngccm_status_reg_reg[22][6]Setup_GFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh0A; J arrival timeXh+/ JXh4 JslackXh@ @ FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C.*SFP_GEN[22].ngccm_status_reg_reg[22][0]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuG@}A0A+&! >+@+&@A=А=Y@`[>>'1p@|?~?`??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh1D@s EASFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/I1 JXhzr D@SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/OProp_H6LUT_SLICEL_I1_O JLUT2Xhzr+>_ rx_test_comm_cnt259_out Jnet (fo=18, routed)Xhף0?` .*SFP_GEN[22].ngccm_status_reg_reg[22][0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)XhU @X4Y9 (CLOCK_ROOT)_ -)SFP_GEN[22].ngccm_status_reg_reg[22][0]/C JFDCEXhzr> Jclock pessimismXh`[>@ Jclock uncertaintyXhw +'SFP_GEN[22].ngccm_status_reg_reg[22][0]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXh> / JXh4 JslackXhY@ FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C.*SFP_GEN[22].ngccm_status_reg_reg[22][3]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuG@}A0A+&! >+@+&@A=А=Y@`[>>'1p@|?~?`??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh1D@s EASFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/I1 JXhzr D@SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/OProp_H6LUT_SLICEL_I1_O JLUT2Xhzr+>_ rx_test_comm_cnt259_out Jnet (fo=18, routed)Xhף0?` .*SFP_GEN[22].ngccm_status_reg_reg[22][3]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)XhU @X4Y9 (CLOCK_ROOT)_ -)SFP_GEN[22].ngccm_status_reg_reg[22][3]/C JFDCEXhzr> Jclock pessimismXh`[>@ Jclock uncertaintyXhw +'SFP_GEN[22].ngccm_status_reg_reg[22][3]Setup_FFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXh> / JXh4 JslackXhY@ FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C.*SFP_GEN[22].ngccm_status_reg_reg[22][5]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuG@}A0A+&! >+@+&@A=А=Y@`[>>'1p@|?~?`??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh1D@s EASFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/I1 JXhzr D@SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/OProp_H6LUT_SLICEL_I1_O JLUT2Xhzr+>_ rx_test_comm_cnt259_out Jnet (fo=18, routed)Xhף0?` .*SFP_GEN[22].ngccm_status_reg_reg[22][5]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)XhU @X4Y9 (CLOCK_ROOT)_ -)SFP_GEN[22].ngccm_status_reg_reg[22][5]/C JFDCEXhzr> Jclock pessimismXh`[>@ Jclock uncertaintyXhw +'SFP_GEN[22].ngccm_status_reg_reg[22][5]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXh> / JXh4 JslackXhY@ FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C.*SFP_GEN[22].ngccm_status_reg_reg[22][8]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuG@}A0A+&! >+@+&@A=А=Y@`[>>'1p@|?~?`??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>l '#SFP_GEN[22].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh1D@s EASFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/I1 JXhzr D@SFP_GEN[22].ngCCM_gbt/SFP_GEN[22].ngccm_status_reg[22][24]_i_1/OProp_H6LUT_SLICEL_I1_O JLUT2Xhzr+>_ rx_test_comm_cnt259_out Jnet (fo=18, routed)Xhף0?` .*SFP_GEN[22].ngccm_status_reg_reg[22][8]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_124 Jnet (fo=674, routed)XhU @X4Y9 (CLOCK_ROOT)_ -)SFP_GEN[22].ngccm_status_reg_reg[22][8]/C JFDCEXhzr> Jclock pessimismXh`[>@ Jclock uncertaintyXhw +'SFP_GEN[22].ngccm_status_reg_reg[22][8]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXh> / JXh4 JslackXhY@( !gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!)y@1y @9Ay@Iy @eE@hq} l8= >) rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C*&SFP_GEN[23].rx_data_ngccm_reg[23][7]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsus>}Á (l=gff? ?l8=zID==p=>o?.>?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=U rx_data[23][7] Jnet (fo=1, routed)Xh=\ *&SFP_GEN[23].rx_data_ngccm_reg[23][7]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1H?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_134 Jnet (fo=674, routed)Xhk?X4Y9 (CLOCK_ROOT)\ *&SFP_GEN[23].rx_data_ngccm_reg[23][7]/C JFDCEXhzr> Jclock pessimismXhzIs ($SFP_GEN[23].rx_data_ngccm_reg[23][7]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhÁ; J arrival timeXhE?/ JXh4 JslackXhl8=Jg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsun>}2S=rh??H=E"%= ף=p=>?.>%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_EFF2_SLICEM_C_Q JFDCEXhzrD= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O84[1] Jnet (fo=2, routed)XhC= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__22/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__22/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhq=J?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhs?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXhE" g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh,?/ JXh4 JslackXhH=G+'SFP_GEN[23].rx_data_ngccm_reg[23][63]/C0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[62]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu]B>}ãَ}=ˡe?َ?/==-=p=>M?.>$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)y +'SFP_GEN[23].rx_data_ngccm_reg[23][63]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[83]_0[55] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[62]_i_1/I0 JXhzr 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[62]_i_1/OProp_H5LUT_SLICEL_I0_O JLUT3XhzrGa=u 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40[62]_i_1_n_0 Jnet (fo=1, routed)XhD<b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[62]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[1].gbtbank_n_134 Jnet (fo=674, routed)XhlG?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[23].rx_data_ngccm_reg[23][63]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhts?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[62]/C JFDCEXhzr> Jclock pessimismXhy .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[62]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhã; J arrival timeXh"?/ JXh4 JslackXh/=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsut>}e~󍿭`,=ˡe??ay;=--=L=p=>M?.>"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)XhC = g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__22/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__22/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhlG?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhq?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh-- g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhe~; J arrival timeXh}??/ JXh4 JslackXhay;=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuy&>} 􁿍9v=$f??cr?="ʡ=1=p=>?.>%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)XhC= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__22/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__22/OProp_D6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhs?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh" g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh 􁿐; J arrival timeXh?/ JXh4 JslackXhcr?=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu>}wJ?5B,=$f??5?|C=1-=T=p=>?.>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/O83[0] Jnet (fo=2, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__22/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__22/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh -r?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh1- g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhwJ; J arrival timeXh…?/ JXh4 JslackXh|C=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu)>} 􁿍9v=$f??)K="-=ʡ=p=>?.>%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)XhC= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__22/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__22/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)XhX94< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhs?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr> Jclock pessimismXh" g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh 􁿐; J arrival timeXhQ?/ JXh4 JslackXh)K=U.*SFP_GEN[23].ngccm_status_reg_reg[23][24]/C.*SFP_GEN[23].ngccm_status_reg_reg[23][24]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuS=}أ;9??L=/]o=@=p=>z.?.>`P?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR){ .*SFP_GEN[23].ngccm_status_reg_reg[23][24]/QProp_AFF_SLICEL_C_Q JFDPEXhzr9H= GCSFP_GEN[23].ngCCM_gbt/SFP_GEN[23].ngccm_status_reg_reg[23][24]_0[8] Jnet (fo=2, routed)Xh)\=s EASFP_GEN[23].ngCCM_gbt/SFP_GEN[23].ngccm_status_reg[23][24]_i_2/I0 JXhzr D@SFP_GEN[23].ngCCM_gbt/SFP_GEN[23].ngccm_status_reg[23][24]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT2Xhzru<b SFP_GEN[23].ngCCM_gbt_n_393 Jnet (fo=1, routed)XhD<` .*SFP_GEN[23].ngccm_status_reg_reg[23][24]/D JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[1].gbtbank_n_134 Jnet (fo=674, routed)Xh33s?X4Y9 (CLOCK_ROOT)` .*SFP_GEN[23].ngccm_status_reg_reg[23][24]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_134 Jnet (fo=674, routed)Xh;ߏ?X4Y9 (CLOCK_ROOT)` .*SFP_GEN[23].ngccm_status_reg_reg[23][24]/C JFDPEXhzr> Jclock pessimismXh/]v ,(SFP_GEN[23].ngccm_status_reg_reg[23][24]Hold_AFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh; J arrival timeXhx?/ JXh4 JslackXhL=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C+'SFP_GEN[23].rx_data_ngccm_reg[23][56]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu #>}d@)\+[=rh?)\?zN=;6"9H=S=p=>?.>ʡ%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=V rx_data[23][56] Jnet (fo=1, routed)XhS=] +'SFP_GEN[23].rx_data_ngccm_reg[23][56]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhq=J?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_134 Jnet (fo=674, routed)Xhzt?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[23].rx_data_ngccm_reg[23][56]/C JFDCEXhzr> Jclock pessimismXh;6"t )%SFP_GEN[23].rx_data_ngccm_reg[23][56]Hold_BFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhd@; J arrival timeXh:?/ JXh4 JslackXhzN=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu1,>} 􁿍9v=$f??DS=" ==p=>?.>%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xhrh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__22/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__22/OProp_C5LUT_SLICEL_I2_O JLUT3Xhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)XhX94< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhs?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr> Jclock pessimismXh" g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh 􁿐; J arrival timeXhu?/ JXh4 JslackXhDS=g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu7@}AVb*A [:(@ @A=А=E@S>E?W@R?}??Mb?Nb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh&@ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfFs> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhr? }yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/I0 JXhzf |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzr> c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh!? yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y9 (CLOCK_ROOT) xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhS>@ Jclock uncertaintyXh vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhVb*A; J arrival timeXhS/ JXh4 JslackXhE@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu7@}AVb*A [:(@ @A=А=E@S>E?W@R?}??Mb?Nb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh&@ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfFs> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhr? }yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/I0 JXhzf |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzr> c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh!? yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y9 (CLOCK_ROOT) xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhS>@ Jclock uncertaintyXh vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhVb*A; J arrival timeXhS/ JXh4 JslackXhE@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsup@}Anf*A [:(@ @A=А=9F@S>E?vW@R?}??Mb?Nb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh&@ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfFs> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhr? }yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/I0 JXhzf |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzr> c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y9 (CLOCK_ROOT) xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhS>@ Jclock uncertaintyXh vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhnf*A; J arrival timeXh/ JXh4 JslackXh9F@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsup@}Anf*A [:(@ @A=А=9F@S>E?vW@R?}??Mb?Nb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh&@ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfFs> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhr? }yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/I0 JXhzf |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzr> c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y9 (CLOCK_ROOT) xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhS>@ Jclock uncertaintyXh vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhnf*A; J arrival timeXh/ JXh4 JslackXh9F@ !g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuA`@}A=*A ?>e:(@ @A=А=łM@T>"?/E@R?}??Mb??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh&@ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhG> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22/I2 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr+> qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22_n_0 Jnet (fo=1, routed)Xhʡ= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22/I5 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22_n_0 Jnet (fo=2, routed)Xh+> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK?X4Y9 (CLOCK_ROOT) kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhT>@ Jclock uncertaintyXh ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh=*A; J arrival timeXh^/ JXh4 JslackXhłM@ !g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuA`@}A=*A ?>e:(@ @A=А=łM@T>"?/E@R?}??Mb??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh&@ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhG> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22/I2 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr+> qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__22_n_0 Jnet (fo=1, routed)Xhʡ= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22/I5 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__22_n_0 Jnet (fo=2, routed)Xh+> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK?X4Y9 (CLOCK_ROOT) kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhT>@ Jclock uncertaintyXh ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]Setup_CFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh=*A; J arrival timeXh^/ JXh4 JslackXhłM@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu'1@}A:Z*Aˡ  "]:(@ˡ @A=А=bRP@T>E?|?M@R?}??Mb? ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh&@ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfFs> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhr? }yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/I0 JXhzf |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__23/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzr> c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh;> yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y9 (CLOCK_ROOT) xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhT>@ Jclock uncertaintyXh vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh:Z*A; J arrival timeXhC/ JXh4 JslackXhbRP@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu @}Aef*A sZ:(@ @A=А=ϣ`@ S>?tC@R?}??Mb??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh&@ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhʡ> yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__23/I3 JXhzr xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__23/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh֣> uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh9?X4Y9 (CLOCK_ROOT) tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh S>@ Jclock uncertaintyXh rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhef*A; J arrival timeXhz/ JXh4 JslackXhϣ`@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu2@}A|j*A sZ:(@ @A=А=T`@ S>?CC@R?}??Mb??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh&@ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhʡ> yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__23/I3 JXhzr xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__23/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh9?X4Y9 (CLOCK_ROOT) tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh S>@ Jclock uncertaintyXh rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh|j*A; J arrival timeXhOb/ JXh4 JslackXhT`@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu@}A V*A [:(@ @A=А=xa@S>?B@R?}??Mb?Nb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh&@ rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/I2 JXhzr qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__22/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhP> {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__23/I5 JXhzr zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__23/OProp_F6LUT_SLICEM_I5_O JLUT6XhzrGa= a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh > wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y9 (CLOCK_ROOT) vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhS>@ Jclock uncertaintyXh tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh V*A; J arrival timeXh/ JXh4 JslackXhxa@ ( !gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!)y@1y @9Ay@Iy @eʑJ@hq} T.= >, rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C+'SFP_GEN[13].rx_data_ngccm_reg[13][38]/D"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuT>}ҭBJ=?ҭ?T.=O?9H==>X94? >XY?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/QProp_FFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[13][38] Jnet (fo=1, routed)Xh=] +'SFP_GEN[13].rx_data_ngccm_reg[13][38]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_34 Jnet (fo=674, routed)Xh:?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[13].rx_data_ngccm_reg[13][38]/C JFDCEXhzr> Jclock pessimismXhO?s )%SFP_GEN[13].rx_data_ngccm_reg[13][38]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh]?/ JXh4 JslackXhT.=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu>}\ӜiU=?i?yg3=|H?=`P=>2? >X?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__12/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__12/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrT= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhr?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXh|H? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh\Ӝ; J arrival timeXhn?/ JXh4 JslackXhyg3=>+'SFP_GEN[13].rx_data_ngccm_reg[13][56]/C0,SFP_GEN[13].ngCCM_gbt/RX_Word_rx40_reg[56]/D"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsut>}KpB,=S?p?y;=9J=L=>n2? >uX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR)x +'SFP_GEN[13].rx_data_ngccm_reg[13][56]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=u 2.g_gbt_bank[1].gbtbank/RX_Word_rx40_reg[78][32] Jnet (fo=1, routed)XhC =_ 1-g_gbt_bank[1].gbtbank/RX_Word_rx40[56]_i_1/I1 JXhzr 0,g_gbt_bank[1].gbtbank/RX_Word_rx40[56]_i_1/OProp_D6LUT_SLICEL_I1_O JLUT3XhzrQ8=w 40SFP_GEN[13].ngCCM_gbt/RX_Word_rx40_reg[83]_0[32] Jnet (fo=1, routed)Xho<b 0,SFP_GEN[13].ngCCM_gbt/RX_Word_rx40_reg[56]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_34 Jnet (fo=674, routed)Xhe;?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[13].rx_data_ngccm_reg[13][56]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[13].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[13].ngCCM_gbt/RX_Word_rx40_reg[56]/C JFDCEXhzr> Jclock pessimismXh9Jx .*SFP_GEN[13].ngCCM_gbt/RX_Word_rx40_reg[56]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhK; J arrival timeXh&?/ JXh4 JslackXhy;=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsut>}{B,=*\?{?y;=9J=L=>F3? >#Y?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)XhC = g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__12/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__12/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhA?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh9J g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhʡ?/ JXh4 JslackXhy;=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C+'SFP_GEN[13].rx_data_ngccm_reg[13][26]/D"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu>}>|ȹN=v?|?!>=?9H==>z4? >%Y?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[13][26] Jnet (fo=1, routed)Xh=] +'SFP_GEN[13].rx_data_ngccm_reg[13][26]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_34 Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[13].rx_data_ngccm_reg[13][26]/C JFDCEXhzr> Jclock pessimismXh?t )%SFP_GEN[13].rx_data_ngccm_reg[13][26]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh>; J arrival timeXh33?/ JXh4 JslackXh!>=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuv>}\ӜiU=?i?C=|H?=Y=>2? >X?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)XhP= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__12/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__12/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzr/]= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhr?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh|H? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh\Ӝ; J arrival timeXh?/ JXh4 JslackXhC=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C+'SFP_GEN[13].rx_data_ngccm_reg[13][35]/D"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuF>}3ҭ=َ?ҭ?dLO=KD=>>!2? >XY?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/QProp_BFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[13][35] Jnet (fo=1, routed)Xh>] +'SFP_GEN[13].rx_data_ngccm_reg[13][35]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_34 Jnet (fo=674, routed)Xh:?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[13].rx_data_ngccm_reg[13][35]/C JFDCEXhzr> Jclock pessimismXhKt )%SFP_GEN[13].rx_data_ngccm_reg[13][35]Hold_FFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh3; J arrival timeXh?/ JXh4 JslackXhdLO=7g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsut>} /~=?/?CO=@J=L=>233? >cX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/O85[1] Jnet (fo=2, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__12/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__12/OProp_G6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[1] Jnet (fo=1, routed)XhA`e< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhc?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXh@J g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXh7?/ JXh4 JslackXhCO=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuw>}{B,=*\?{?aO=9J=Q8=>F3? >#Y?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)XhC = g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__12/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__12/OProp_C5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[6] Jnet (fo=1, routed)XhX94< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhA?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXh9J g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhn?/ JXh4 JslackXhaO=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu">}ۏOYxQ=َ?O?jT=4X?v=U=>!2? >QX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)XhL7= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__12/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__12/OProp_G6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)XhA`e< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh|?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh4X? g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhۏ; J arrival timeXh33?/ JXh4 JslackXhjT=}!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu+@}A#1Aw'>k,@w'@A=А=ʑJ@>ta>7?Id@q=*?P??e;?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh?@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_C6LUT_SLICEL_I1_O JLUT4XhzrA`> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhbX> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr+> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12_n_0 Jnet (fo=1, routed)Xhʡ= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12/OProp_H6LUT_SLICEL_I5_O JLUT6Xhzr +> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12_n_0 Jnet (fo=2, routed)XhV> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhE@X4Y7 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh>ta>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh#1A; J arrival timeXh`/ JXh4 JslackXhʑJ@ }!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu+@}A#1Aw'>k,@w'@A=А=ʑJ@>ta>7?Id@q=*?P??e;?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh?@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_C6LUT_SLICEL_I1_O JLUT4XhzrA`> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhbX> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr+> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__12_n_0 Jnet (fo=1, routed)Xhʡ= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12/OProp_H6LUT_SLICEL_I5_O JLUT6Xhzr +> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__12_n_0 Jnet (fo=2, routed)XhV> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhE@X4Y7 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh>ta>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh#1A; J arrival timeXh`/ JXh4 JslackXhʑJ@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuҡ@}A&m1AG)n(*>k,@G)@A=А=LRU@>ta>1?ˡe@q=*?P??M?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh?@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_C6LUT_SLICEL_I1_O JLUT4XhzrA`> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhw= zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__13/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__13/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh? vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh>ta>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh&m1A; J arrival timeXh&1/ JXh4 JslackXhLRU@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu&@}AS1A<'F>k,@<'@A=А=sU@>ta>(?X9d@q=*?P??|?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh?@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I1 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_C6LUT_SLICEL_I1_O JLUT4XhzfA`> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> W> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xhȶ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff@X4Y7 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh>ta>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhS1A; J arrival timeXh/ JXh4 JslackXhsU@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu&@}AS1A<'F>k,@<'@A=А=sU@>ta>(?X9d@q=*?P??|?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh?@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I1 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_C6LUT_SLICEL_I1_O JLUT4XhzfA`> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> W> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xhȶ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff@X4Y7 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh>ta>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhS1A; J arrival timeXh/ JXh4 JslackXhsU@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuV@}Ak#1A<'F>k,@<'@A=А=U@>ta>(?1d@q=*?P??|?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh?@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I1 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_C6LUT_SLICEL_I1_O JLUT4XhzfA`> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> W> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh}?> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff@X4Y7 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh>ta>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhk#1A; J arrival timeXhl/ JXh4 JslackXhU@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuV@}Ak#1A<'F>k,@<'@A=А=U@>ta>(?1d@q=*?P??|?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh?@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I1 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_C6LUT_SLICEL_I1_O JLUT4XhzfA`> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> W> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh}?> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff@X4Y7 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh>ta>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhk#1A; J arrival timeXhl/ JXh4 JslackXhU@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuV@}Ak#1A<'F>k,@<'@A=А=U@>ta>(?1d@q=*?P??|?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh?@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I1 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_C6LUT_SLICEL_I1_O JLUT4XhzfA`> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> W> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__13/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh}?> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff@X4Y7 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh>ta>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhk#1A; J arrival timeXhl/ JXh4 JslackXhU@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu^@}Apy1AG)n(*>k,@G)@A=А=U@>ta>1?pe@q=*?P??M?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh?@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_C6LUT_SLICEL_I1_O JLUT4XhzrA`> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhw= zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__13/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__13/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)XhI ? vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh>ta>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhpy1A; J arrival timeXh/ JXh4 JslackXhU@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuz@}A1A'>k,@'@A=А=V@>ta>?fff@q=*?P???(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh?@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__12/OProp_C6LUT_SLICEL_I1_O JLUT4XhzrA`> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhj<> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__13/OProp_B6LUT_SLICEM_I3_O JLUT5Xhzrj= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh$@X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh>ta>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhV@ ( !gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!)y@1y @9Ay@Iy @eD>@hq} 0g< >/ rise - rise rise - rise  +'SFP_GEN[14].rx_data_ngccm_reg[14][28]/C0,SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[28]/D"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuUb>} b=rh??0g<@D=v=>E6?X9> \?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR)y +'SFP_GEN[14].rx_data_ngccm_reg[14][28]/QProp_FFF2_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[83]_0[16] Jnet (fo=1, routed)Xhv=b 0,SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[28]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_44 Jnet (fo=674, routed)XhM?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[14].rx_data_ngccm_reg[14][28]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[14].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZd?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXh@y .*SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[28]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh ; J arrival timeXht?/ JXh4 JslackXh0g<g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu^d;>}ȣ=أ?? = )=E=>k4?X9> \?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__13/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__13/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[0] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZd?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh ) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhȣ; J arrival timeXhd?/ JXh4 JslackXh =g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuC>})󭿭D=V??3 =ߦ[==>h-?X9>PW?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)Xh ף= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__13/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__13/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrj<= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhl{?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԘ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXhߦ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh); J arrival timeXh?/ JXh4 JslackXh3 =g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[14].rx_data_ngccm_reg[14][73]/D"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu>}ҭSws=V?ҭ?ώ = ?9H==> 0?X9>KW?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[14][73] Jnet (fo=1, routed)Xh=] +'SFP_GEN[14].rx_data_ngccm_reg[14][73]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhv~?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_44 Jnet (fo=674, routed)Xh:?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[14].rx_data_ngccm_reg[14][73]/C JFDCEXhzr> Jclock pessimismXh ?s )%SFP_GEN[14].rx_data_ngccm_reg[14][73]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh8?/ JXh4 JslackXhώ =g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C+'SFP_GEN[14].rx_data_ngccm_reg[14][43]/D"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu5,>}m>=??=39H=F=>6?X9>Y?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[14][43] Jnet (fo=1, routed)XhF=] +'SFP_GEN[14].rx_data_ngccm_reg[14][43]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_44 Jnet (fo=674, routed)Xh#ۙ?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[14].rx_data_ngccm_reg[14][43]/C JFDCEXhzr> Jclock pessimismXh3s )%SFP_GEN[14].rx_data_ngccm_reg[14][43]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhm>; J arrival timeXh+?/ JXh4 JslackXh=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuC>}ȣ=أ??)= )=Q=>k4?X9> \?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__13/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__13/OProp_B6LUT_SLICEL_I2_O JLUT3XhzrY= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xhu< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZd?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh ) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhȣ; J arrival timeXh?/ JXh4 JslackXh)=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C+'SFP_GEN[14].rx_data_ngccm_reg[14][45]/D"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu433>}_=??6=0D=I >>6?X9>$Y?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_BFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[14][45] Jnet (fo=1, routed)XhI >] +'SFP_GEN[14].rx_data_ngccm_reg[14][45]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_44 Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[14].rx_data_ngccm_reg[14][45]/C JFDCEXhzr> Jclock pessimismXh0t )%SFP_GEN[14].rx_data_ngccm_reg[14][45]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh_; J arrival timeXhb?/ JXh4 JslackXh6=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu/>}h{X=|?{?b9=>=`P=>n2?X9>W?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__13/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__13/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr/]= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhNb?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhh; J arrival timeXh33?/ JXh4 JslackXhb9=H+'SFP_GEN[14].rx_data_ngccm_reg[14][56]/C0,SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[56]/D"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu/>}cE󭿭W=*\??9=>`=T=>-2?X9>PW?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR)x +'SFP_GEN[14].rx_data_ngccm_reg[14][56]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=w 40g_gbt_bank[1].gbtbank/RX_Word_rx40_reg[78]_0[32] Jnet (fo=1, routed)Xht=b 40g_gbt_bank[1].gbtbank/RX_Word_rx40[56]_i_1__0/I1 JXhzr 3/g_gbt_bank[1].gbtbank/RX_Word_rx40[56]_i_1__0/OProp_D6LUT_SLICEL_I1_O JLUT3XhzrY=w 40SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[83]_0[32] Jnet (fo=1, routed)Xho<b 0,SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[56]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_44 Jnet (fo=674, routed)XhA?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[14].rx_data_ngccm_reg[14][56]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[14].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhԘ?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[56]/C JFDCEXhzr> Jclock pessimismXh>x .*SFP_GEN[14].ngCCM_gbt/RX_Word_rx40_reg[56]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhcE; J arrival timeXhp?/ JXh4 JslackXh9=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu>}>Nbi5=rh?Nb?I:;=~tJ=T=>E6?X9>j\?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_9_in Jnet (fo=2, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__13/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__13/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhM?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhC?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh~tJ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh>; J arrival timeXh?/ JXh4 JslackXhI:;=!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuZ@}AX1A8)b>l/@8)@A=А=D>@Od>33?o@.??v?a?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh"C@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhn> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr(> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13_n_0 Jnet (fo=1, routed)Xhw= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13_n_0 Jnet (fo=2, routed)XhA`> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh%@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc@X4Y7 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhX1A; J arrival timeXh1/ JXh4 JslackXhD>@ !g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuZ@}AX1A8)b>l/@8)@A=А=D>@Od>33?o@.??v?a?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh"C@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhn> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr(> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__13_n_0 Jnet (fo=1, routed)Xhw= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__13_n_0 Jnet (fo=2, routed)XhA`> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh%@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc@X4Y7 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhX1A; J arrival timeXh1/ JXh4 JslackXhD>@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuĨ@}A1A#)9 >l/@#)@A=А=-E@Od>㥻?Ds@.??v?8?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh"C@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzf֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh ? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh%@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhNb@X4Y7 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXhq=/ JXh4 JslackXh-E@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsų@}A1A-*W>l/@-*@A=А=E@Od>㥻?s@.??v?-?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh"C@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzf֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh%@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh:@X4Y7 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh1A; J arrival timeXhA/ JXh4 JslackXhE@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsų@}A1A-*W>l/@-*@A=А=E@Od>㥻?s@.??v?-?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh"C@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzf֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh%@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh:@X4Y7 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_GFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh1A; J arrival timeXhA/ JXh4 JslackXhE@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu9@}A61A-*W>l/@-*@A=А=#F@Od>㥻?s@.??v?-?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh"C@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzf֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh-? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh%@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh:@X4Y7 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh61A; J arrival timeXh@5/ JXh4 JslackXh#F@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu9@}A61A-*W>l/@-*@A=А=#F@Od>㥻?s@.??v?-?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh"C@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzf֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__14/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh-? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh%@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh:@X4Y7 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh61A; J arrival timeXh@5/ JXh4 JslackXh#F@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuK7@}AK1ANb(W=l/@Nb(@A=А=RK@Od>> ?xf@.??v??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh"C@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh9H> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/OProp_A6LUT_SLICEL_I3_O JLUT5Xhzrq> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh#۹> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh%@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy@X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhK1A; J arrival timeXh/ JXh4 JslackXhRK@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu@}AO1ANb(W=l/@Nb(@A=А=K@Od>> ?f@.??v??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh"C@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh9H> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/OProp_A6LUT_SLICEL_I3_O JLUT5Xhzrq> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhη> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh%@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy@X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhO1A; J arrival timeXh/ JXh4 JslackXhK@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu@}AO1ANb(W=l/@Nb(@A=А=K@Od>> ?f@.??v??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh"C@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__13/OProp_C6LUT_SLICEL_I3_O JLUT4Xhzr֣p> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh9H> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__14/OProp_A6LUT_SLICEL_I3_O JLUT5Xhzrq> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhη> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh%@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy@X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhO1A; J arrival timeXh/ JXh4 JslackXhK@ ( !gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!)y@1y @9Ay@Iy @eCO@hq} =  >3 rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C+'SFP_GEN[15].rx_data_ngccm_reg[15][72]/D"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuX->}釿`=im??=0ZD==>M?>8!?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/QProp_BFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[15][72] Jnet (fo=1, routed)Xh=] +'SFP_GEN[15].rx_data_ngccm_reg[15][72]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh)\O?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)Xhy?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][72]/C JFDCEXhzr> Jclock pessimismXh0Zt )%SFP_GEN[15].rx_data_ngccm_reg[15][72]Hold_CFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh釿; J arrival timeXhj?/ JXh4 JslackXh=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu)>}=D%t=im?%?{~=Lgv=X9=>M?>A ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__14/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__14/OProp_C6LUT_SLICEL_I2_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh)\O?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhLg g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh=D; J arrival timeXh1?/ JXh4 JslackXh{~=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[15].rx_data_ngccm_reg[15][31]/D"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuUb>}σm?=Om??=G)(D=v=>J ?>8!?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_HFF_SLICEL_C_Q JFDREXhzrD=V rx_data[15][31] Jnet (fo=1, routed)Xhv=] +'SFP_GEN[15].rx_data_ngccm_reg[15][31]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)Xhy?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][31]/C JFDCEXhzr> Jclock pessimismXhG)(t )%SFP_GEN[15].rx_data_ngccm_reg[15][31]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhσ; J arrival timeXh:?/ JXh4 JslackXh=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C+'SFP_GEN[15].rx_data_ngccm_reg[15][27]/D"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuxh>}σm?=Om??: =G)(D==>J ?>8!?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[15][27] Jnet (fo=1, routed)Xh=] +'SFP_GEN[15].rx_data_ngccm_reg[15][27]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)Xhy?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][27]/C JFDCEXhzr> Jclock pessimismXhG)(s )%SFP_GEN[15].rx_data_ngccm_reg[15][27]Hold_GFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhσ; J arrival timeXhԈ?/ JXh4 JslackXh: =g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuX->}=D%t=im?%?B$=Lg ==>M?>A ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__14/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__14/OProp_C5LUT_SLICEL_I0_O JLUT3Xhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[6] Jnet (fo=1, routed)XhX94< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh)\O?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXhLg g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh=D; J arrival timeXhj?/ JXh4 JslackXhB$=$eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[39]/D"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu'>}̇8E=أp?8?_0=:9H==>B`?>G!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[39] Jnet (fo=1, routed)Xh= eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhnR?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[39]/C JFDCEXhzr> Jclock pessimismXh: c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[39]Hold_GFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXḣ; J arrival timeXhO?/ JXh4 JslackXh_0=$eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[25]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[25]/D"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuS>}?  `=Nbp? ?9=0Z9H==>?>v?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[25]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[25] Jnet (fo=1, routed)Xh= eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[25]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-R?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[25]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[25]/C JFDCEXhzr> Jclock pessimismXh0Z c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[25]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh?; J arrival timeXh1?/ JXh4 JslackXh9=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu,>}q!MV=Vn?!?;=&=`P=>o?>#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_19_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__14/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__14/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr/]= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh P?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh"{?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXh& g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhq; J arrival timeXhH?/ JXh4 JslackXh;=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C+'SFP_GEN[15].rx_data_ngccm_reg[15][51]/D"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuD>}v33q2=im?33?<=:9H=n>>M?>$?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H=V rx_data[15][51] Jnet (fo=1, routed)Xhn>] +'SFP_GEN[15].rx_data_ngccm_reg[15][51]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh)\O?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_54 Jnet (fo=674, routed)Xh(|?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[15].rx_data_ngccm_reg[15][51]/C JFDCEXhzr> Jclock pessimismXh:s )%SFP_GEN[15].rx_data_ngccm_reg[15][51]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhv; J arrival timeXh*\?/ JXh4 JslackXh<=p0,SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30]/CHDSFP_GEN[15].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/D"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuZd;>}n-(={n?-?A=uJ9H=L7 >>?>]"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR)} 0,SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H=q .*SFP_GEN[15].ngCCM_gbt/gbt_rx_checker/Q[14] Jnet (fo=2, routed)XhL7 >z HDSFP_GEN[15].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[15].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh GCSFP_GEN[15].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhz?X4Y7 (CLOCK_ROOT)z HDSFP_GEN[15].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C JFDREXhzr> Jclock pessimismXhuJ FBSFP_GEN[15].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]Hold_AFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhn; J arrival timeXhv?/ JXh4 JslackXhA="eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/D"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT6=3)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuM@}Afa-A}cG)@@A=А=CO@}]>zt?|@)???43?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrO > \Xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/Q[35] Jnet (fo=9, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___105_i_34__14/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___105_i_34__14/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzrjt> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___105_i_34__14_n_0 Jnet (fo=1, routed)Xhe;> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___105_i_19__14/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/syndromes/i___105_i_19__14/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/s3_from_syndromes[3] Jnet (fo=29, routed)Xh@ plg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_2__30/I3 JXhzr okg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_2__30/OProp_C6LUT_SLICEM_I3_O JLUT4XhzrQ= qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_i_2__30_n_0 Jnet (fo=1, routed)XhNb? xtg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__30/I0 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__30/OProp_D6LUT_SLICEM_I0_O JLUT6Xhzr"y> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg_3 Jnet (fo=1, routed)Xh*\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhH @X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[86]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/CLK Jnet (fo=674, routed)XhA?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_reg/C JFDREXhzr> Jclock pessimismXh}]>@ Jclock uncertaintyXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder0to50/ERROR_DETECT_O_regSetup_DFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXhfa-A; J arrival timeXh/ JXh4 JslackXhCO@}!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuʡ@}AGK+Aa,x?5.@a@A=А=Hc@\>?6@)???ʡ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh333> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__14/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__14/OProp_G6LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__14_n_0 Jnet (fo=1, routed)XhP= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__14/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__14/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzrv= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__14_n_0 Jnet (fo=2, routed)Xh~> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhGK+A; J arrival timeXhj/ JXh4 JslackXhHc@ }!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuʡ@}AGK+Aa,x?5.@a@A=А=Hc@\>?6@)???ʡ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh333> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__14/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__14/OProp_G6LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__14_n_0 Jnet (fo=1, routed)XhP= okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__14/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__14/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzrv= plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__14_n_0 Jnet (fo=2, routed)Xh~> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhGK+A; J arrival timeXhj/ JXh4 JslackXhHc@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu~@}Ac+A'1 ?5.@'1@A=А=Yi@+\>ʡ?-:@)???Mb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^:> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhl> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhp?X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh+\>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXhc+A; J arrival timeXh/ JXh4 JslackXhYi@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuff@}A+A'1 ?5.@'1@A=А=xi@+\>ʡ?9@)???Mb?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^:> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhT> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhp?X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXh+\>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhxi@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuE@}A6+A6z?5.@@A=А=j@\>ʡ?^9@)???8?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^:> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh > tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh6+A; J arrival timeXhA`/ JXh4 JslackXhj@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu-@}A+C+A6z?5.@@A=А=P}j@\>ʡ?79@)???8?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^:> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhM> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh+C+A; J arrival timeXhG/ JXh4 JslackXhP}j@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu-@}A+C+A6z?5.@@A=А=P}j@\>ʡ?79@)???8?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^:> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhM> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh+C+A; J arrival timeXhG/ JXh4 JslackXhP}j@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuh@}A.+Ar?5.@r@A=А=ck@!\>ʡ?Q8@)???`?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^:> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhu> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh!\>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh.+A; J arrival timeXh/ JXh4 JslackXhck@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuh@}A^O+Aa,x?5.@a@A=А=jk@\>ʡ?Q8@)???ʡ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__14/OProp_D6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^:> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__15/OProp_A6LUT_SLICEM_I3_O JLUT5XhzrE= ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhu> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh\>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh^O+A; J arrival timeXh/ JXh4 JslackXhjk@ ( !gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!)y@1y @9Ay@Iy @eIK@hq} .b< >5 rise - rise rise - rise  8g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu>}w2c̶=?c?.b<mGo=-=̌>k4?Ġ>U?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/O84[1] Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__15/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__15/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzru< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh"{?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXhmG g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhw2; J arrival timeXh?/ JXh4 JslackXh.b<g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C+'SFP_GEN[16].rx_data_ngccm_reg[16][78]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu433>}y鞿&=??=aD=J >̌>k4?Ġ>HZ?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/QProp_GFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[16][78] Jnet (fo=1, routed)XhJ >] +'SFP_GEN[16].rx_data_ngccm_reg[16][78]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh"{?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_64 Jnet (fo=674, routed)Xhˡ?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[16].rx_data_ngccm_reg[16][78]/C JFDCEXhzr> Jclock pessimismXhat )%SFP_GEN[16].rx_data_ngccm_reg[16][78]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhy鞿; J arrival timeXho?/ JXh4 JslackXh=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[16].rx_data_ngccm_reg[16][39]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuY%>}؜:c=?:?g,=5D=x=̌>}?5?Ġ>V?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[16][39] Jnet (fo=1, routed)Xhx=] +'SFP_GEN[16].rx_data_ngccm_reg[16][39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh{?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_64 Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[16].rx_data_ngccm_reg[16][39]/C JFDCEXhzr> Jclock pessimismXh5t )%SFP_GEN[16].rx_data_ngccm_reg[16][39]Hold_BFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh؜; J arrival timeXh?/ JXh4 JslackXhg,=hsog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[32]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu}&>}刺ȍ=1??=)W%==̌>t3?Ġ>~?U?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_BFF2_SLICEL_C_Q JFDCEXhzfD= qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)Xh1= jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[32]_i_1__21/I1 JXhzf ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[32]_i_1__21/OProp_C6LUT_SLICEM_I1_O JLUT5Xhzru< `\g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg00[32] Jnet (fo=1, routed)Xho< eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[32]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh$y?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[32]/C JFDCEXhzr> Jclock pessimismXh)W c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[32]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXha?/ JXh4 JslackXh=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C+'SFP_GEN[16].rx_data_ngccm_reg[16][37]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu'>}؜:c=?:?]"=5D=i=̌>}?5?Ġ>V?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=V rx_data[16][37] Jnet (fo=1, routed)Xhi=] +'SFP_GEN[16].rx_data_ngccm_reg[16][37]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh{?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_64 Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[16].rx_data_ngccm_reg[16][37]/C JFDCEXhzr> Jclock pessimismXh5t )%SFP_GEN[16].rx_data_ngccm_reg[16][37]Hold_AFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh؜; J arrival timeXh?/ JXh4 JslackXh]"=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu!>}﬙xE|=?x?%=<7A`=j<=̌>أ0?Ġ>QX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__15/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__15/OProp_C5LUT_SLICEM_I2_O JLUT3Xhzr%= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)XhX94< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh? w?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZ?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr> Jclock pessimismXh<7 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]Hold_CFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh﬙; J arrival timeXhٞ?/ JXh4 JslackXh%=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuX9>}H~=?~?7%==-=̌>k4?Ġ>6^Z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xhrh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__15/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__15/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh"{?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhB`?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhH; J arrival timeXh ף?/ JXh4 JslackXh7%=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C+'SFP_GEN[16].rx_data_ngccm_reg[16][64]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu>}4K=̌??[)=Ή69H==̌>4?Ġ>XY?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[16][64] Jnet (fo=1, routed)Xh=] +'SFP_GEN[16].rx_data_ngccm_reg[16][64]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh[d{?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_64 Jnet (fo=674, routed)Xh/ݔ?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[16].rx_data_ngccm_reg[16][64]/C JFDCEXhzr> Jclock pessimismXhΉ6t )%SFP_GEN[16].rx_data_ngccm_reg[16][64]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh4; J arrival timeXh|?/ JXh4 JslackXh[)=hsog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[27]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu +>}刺ȍ=1??+=)Wo==̌>t3?Ġ>~?U?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_BFF2_SLICEL_C_Q JFDCEXhzfD= qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)Xh-= jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[27]_i_1__21/I1 JXhzf ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[27]_i_1__21/OProp_D6LUT_SLICEM_I1_O JLUT5Xhzro< `\g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg00[27] Jnet (fo=1, routed)Xho< eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[27]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh$y?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[27]/C JFDCEXhzr> Jclock pessimismXh)W c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[27]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhrh?/ JXh4 JslackXh+=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C+'SFP_GEN[16].rx_data_ngccm_reg[16][35]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu(>}ur=?r?22=7D==̌>}?5?Ġ>EV?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[16][35] Jnet (fo=1, routed)Xh=] +'SFP_GEN[16].rx_data_ngccm_reg[16][35]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh{?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_64 Jnet (fo=674, routed)XhS?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[16].rx_data_ngccm_reg[16][35]/C JFDCEXhzr> Jclock pessimismXh7t )%SFP_GEN[16].rx_data_ngccm_reg[16][35]Hold_FFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhu; J arrival timeXhI ?/ JXh4 JslackXh22=!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu@}A0AB`%}-!>rh)@B`%@A=А=IK@a>?|_@I "??n??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhO> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15_n_0 Jnet (fo=1, routed)XhK7> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15/OProp_B6LUT_SLICEM_I5_O JLUT6Xhzrx> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15_n_0 Jnet (fo=2, routed)Xh33> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh  @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhm @X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXh(\/ JXh4 JslackXhIK@ !g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu@}A0AB`%}-!>rh)@B`%@A=А=IK@a>?|_@I "??n??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhO> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__15_n_0 Jnet (fo=1, routed)XhK7> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15/OProp_B6LUT_SLICEM_I5_O JLUT6Xhzrx> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__15_n_0 Jnet (fo=2, routed)Xh33> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh  @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhm @X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXh(\/ JXh4 JslackXhIK@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu@}Ag0A$>rh)@$@A=А=`\@a>C?V]@I "??n??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh#۹> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhl? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh  @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhg0A; J arrival timeXh5^/ JXh4 JslackXh`\@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuh@}A l0A$>rh)@$@A=А=$]@a>C?/\@I "??n??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh#۹> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh  @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh l0A; J arrival timeXhE/ JXh4 JslackXh$]@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuh@}A l0A$>rh)@$@A=А=$]@a>C?/\@I "??n??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh#۹> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh  @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh l0A; J arrival timeXhE/ JXh4 JslackXh$]@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuW9@}A#p0AO%S' >rh)@O%@A=А=kg@a>C?-R@I "??n?v?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh#۹> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhη> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh  @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh#p0A; J arrival timeXh/ JXh4 JslackXhkg@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuW9@}A#p0AO%S' >rh)@O%@A=А=kg@a>C?-R@I "??n?v?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh#۹> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhη> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh  @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh#p0A; J arrival timeXh/ JXh4 JslackXhkg@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu @}Am|0AO%S' >rh)@O%@A=А=Gh@a>C?Q@I "??n?v?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh#۹> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhE> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh  @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhm|0A; J arrival timeXh/ JXh4 JslackXhGh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu @}Am|0AO%S' >rh)@O%@A=А=Gh@a>C?Q@I "??n?v?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/I1 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh#۹> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__16/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhE> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh  @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhm|0A; J arrival timeXh/ JXh4 JslackXhGh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu䥓@}A l0A}?%(!>rh)@}?%@A=А=p@a>C?$I@I "??n?V?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/I1 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__15/OProp_D6LUT_SLICEL_I1_O JLUT4XhzfZd> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhҍ> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__16/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__16/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh  @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh l0A; J arrival timeXhZ/ JXh4 JslackXhp@ ( !gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!)y@1y @9Ay@Iy @e?K@hq} = >6 rise - rise rise - rise  7g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu>}Kek=:h??=U"o=X9=̌>?w>T%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_EFF2_SLICEM_C_Q JFDCEXhzrD= ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/O84[1] Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__16/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__16/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzro< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] Jnet (fo=1, routed)Xhu< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~J?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhu?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXhU" g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhK; J arrival timeXh·?/ JXh4 JslackXh=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu/>}dS|$\r=+g?|?` =X"`=T=̌>]?w>/$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__16/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__16/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrY= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhH?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhjt?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXhX" g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhdS; J arrival timeXhK?/ JXh4 JslackXh` =Bxtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/D"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuIb>}q;ߏgi5=L7i?;ߏ?&=S,=@=̌>?w>ˡ%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/QProp_EFF_SLICEL_C_Q JFDPEXhzr9H= {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg_n_0_[0] Jnet (fo=5, routed)Xh)\= b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_i_1__16/I1 JXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_i_1__16/OProp_A6LUT_SLICEL_I1_O JLUT3XhzrQ8= c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_i_1__16_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh K?X4Y8 (CLOCK_ROOT) xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y8 (CLOCK_ROOT) ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXhS, [Wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/READY_o_regHold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhq; J arrival timeXh阮?/ JXh4 JslackXh&=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu">}dS|$\r=+g?|?A3=X"A`=@=̌>]?w>/$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__16/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__16/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr%= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] Jnet (fo=1, routed)XhX94< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhH?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhjt?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr> Jclock pessimismXhX" g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhdS; J arrival timeXh?/ JXh4 JslackXhA3=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuˡE>}C| K=f?|?8='"=j=̌>I ?w>/$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__16/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__16/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrY= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhrH?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhjt?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh'" g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhC; J arrival timeXh1?/ JXh4 JslackXh8=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu,>}m>)\#S=h?)\?CW>=E"=`P=̌>Z?w>$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__16/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__16/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr/]= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhJ?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhzt?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXhE" g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhm>; J arrival timeXh'1?/ JXh4 JslackXhCW>=?+'SFP_GEN[17].rx_data_ngccm_reg[17][59]/C0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]/D"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu">};ߏ-g=:h?;ߏ?˵>=]"A`=@=̌>?w>ˡ%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR)x +'SFP_GEN[17].rx_data_ngccm_reg[17][59]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[83]_0[51] Jnet (fo=1, routed)Xht=_ 1-SFP_GEN[17].ngCCM_gbt/RX_Word_rx40[58]_i_1/I0 JXhzr 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40[58]_i_1/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr%=u 2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40[58]_i_1_n_0 Jnet (fo=1, routed)XhX94<b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_74 Jnet (fo=674, routed)Xh~J?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[17].rx_data_ngccm_reg[17][59]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]/C JFDCEXhzr> Jclock pessimismXh]"y .*SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh:?/ JXh4 JslackXh˵>=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C*&SFP_GEN[17].rx_data_ngccm_reg[17][7]/D"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu&1>}4p@='1h?p?+A=`<9H==̌>?w> ?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_AFF2_SLICEM_C_Q JFDREXhzr9H=U rx_data[17][7] Jnet (fo=1, routed)Xh=\ *&SFP_GEN[17].rx_data_ngccm_reg[17][7]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhI?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_74 Jnet (fo=674, routed)Xh֣p?X4Y8 (CLOCK_ROOT)\ *&SFP_GEN[17].rx_data_ngccm_reg[17][7]/C JFDCEXhzr> Jclock pessimismXh`<s ($SFP_GEN[17].rx_data_ngccm_reg[17][7]Hold_CFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh4; J arrival timeXhq=?/ JXh4 JslackXh+A=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu>}쀿|B,=:h?|?|C=1-=T=̌>?w>/$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)Xht= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__16/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__16/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~J?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhjt?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXh1- g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh쀿; J arrival timeXh= ?/ JXh4 JslackXh|C=wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/Cwsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsua;=}yw)ף;i?w?D=^Po=Q8=̌>B`?w>B`%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[4] Jnet (fo=2, routed)Xh+= |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__17/I5 JXhzr {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__17/OProp_A6LUT_SLICEM_I5_O JLUT6Xhzru< }yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__17_n_0 Jnet (fo=1, routed)XhD< wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhK?X4Y8 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh}?u?X4Y8 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh^P uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhy; J arrival timeXh?/ JXh4 JslackXhD=}!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu@}A*A|8ף(@|@A=А=?K@oY>X?~J@G!? ?-??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_C6LUT_SLICEM_I3_O JLUT4XhzrA`e> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhSc> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16_n_0 Jnet (fo=1, routed)XhE6> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16_n_0 Jnet (fo=2, routed)Xh\? kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1?X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhoY>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh*A; J arrival timeXhk/ JXh4 JslackXh?K@ }!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuw@}A*Alh:ף(@l@A=А=i[@PrY>X?:@G!? ?-?Т?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_C6LUT_SLICEM_I3_O JLUT4XhzrA`e> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhSc> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__16_n_0 Jnet (fo=1, routed)XhE6> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__16_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl?X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhPrY>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh*A; J arrival timeXhb/ JXh4 JslackXhi[@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu@}A*AS3ף(@@A=А=?o@bY>?6@G!? ?-??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_C6LUT_SLICEM_I3_O JLUT4XhzrA`e> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh^I> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh`> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhbY>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh*A; J arrival timeXhV/ JXh4 JslackXh?o@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu@}A*AS3ף(@@A=А=?o@bY>?6@G!? ?-??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_C6LUT_SLICEM_I3_O JLUT4XhzrA`e> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh^I> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh`> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhbY>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh*A; J arrival timeXhV/ JXh4 JslackXh?o@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuU@}A *AS3ף(@@A=А=o@bY>?R6@G!? ?-??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_C6LUT_SLICEM_I3_O JLUT4XhzrA`e> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh^I> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__17/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhbY>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh *A; J arrival timeXh@5/ JXh4 JslackXho@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu@}A- +Ac0/ף(@c@A=А=܈s@XY>?"2@G!? ?-??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_C6LUT_SLICEM_I3_O JLUT4XhzrA`e> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^= xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh/> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhXY>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh- +A; J arrival timeXhQ/ JXh4 JslackXh܈s@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu@}A- +Ac0/ף(@c@A=А=܈s@XY>?"2@G!? ?-??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_C6LUT_SLICEM_I3_O JLUT4XhzrA`e> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^= xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh/> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhXY>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh- +A; J arrival timeXhQ/ JXh4 JslackXh܈s@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsum@}AE+Ac0/ף(@c@A=А=cs@XY>?~2@G!? ?-??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_C6LUT_SLICEM_I3_O JLUT4XhzrA`e> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^= xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhS> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhXY>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhE+A; J arrival timeXhX9/ JXh4 JslackXhcs@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsum@}AE+Ac0/ף(@c@A=А=cs@XY>?~2@G!? ?-??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_C6LUT_SLICEM_I3_O JLUT4XhzrA`e> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^= xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhS> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhXY>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhE+A; J arrival timeXhX9/ JXh4 JslackXhcs@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsum@}AE+Ac0/ף(@c@A=А=cs@XY>?~2@G!? ?-??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhA@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/I3 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__16/OProp_C6LUT_SLICEM_I3_O JLUT4XhzrA`e> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh5^= xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__17/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhS> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhp= @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhXY>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhE+A; J arrival timeXhX9/ JXh4 JslackXhcs@ ( !gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!)y@1y @9Ay@Iy @eyQ@hq} 77= >9 rise - rise rise - rise  eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuQb>}}jē$=A`e?j?77=$D=v=̌>?w>S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[32] Jnet (fo=1, routed)Xhv= eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh+G?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhn?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]/C JFDCEXhzr> Jclock pessimismXh$ c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[32]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh}; J arrival timeXhk?/ JXh4 JslackXh77==+'SFP_GEN[18].rx_data_ngccm_reg[18][52]/C0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[52]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuT94>}m狿)= c?m?>:=v=9=̌>v>w>.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR)y +'SFP_GEN[18].rx_data_ngccm_reg[18][52]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[83]_0[44] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[18].ngCCM_gbt/RX_Word_rx40[52]_i_1/I1 JXhzr 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40[52]_i_1/OProp_D6LUT_SLICEL_I1_O JLUT3Xhzr<u 2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40[52]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[52]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)XhˡE?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[18].rx_data_ngccm_reg[18][52]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhim?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr> Jclock pessimismXhx .*SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[52]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhr?/ JXh4 JslackXh>:=<+'SFP_GEN[18].rx_data_ngccm_reg[18][41]/C0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[40]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuIb>}IR~=:h?R?_C=,=@=̌>?w>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR)x +'SFP_GEN[18].rx_data_ngccm_reg[18][41]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[83]_0[33] Jnet (fo=1, routed)Xh)\=_ 1-SFP_GEN[18].ngCCM_gbt/RX_Word_rx40[40]_i_1/I0 JXhzr 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40[40]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT3XhzrQ8=u 2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 Jnet (fo=1, routed)XhD<b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[40]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xh~J?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[18].rx_data_ngccm_reg[18][41]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33s?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzr> Jclock pessimismXh,x .*SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[40]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhI; J arrival timeXhff?/ JXh4 JslackXh_C=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C+'SFP_GEN[18].rx_data_ngccm_reg[18][72]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu/$>}ё󍿭8g=Zd??lF=8g$9H=A`=̌>|>w>!?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=V rx_data[18][72] Jnet (fo=1, routed)XhA`=] +'SFP_GEN[18].rx_data_ngccm_reg[18][72]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh$F?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xhq?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[18].rx_data_ngccm_reg[18][72]/C JFDCEXhzr> Jclock pessimismXh8g$t )%SFP_GEN[18].rx_data_ngccm_reg[18][72]Hold_AFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhё; J arrival timeXhȆ?/ JXh4 JslackXhlF=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[18].rx_data_ngccm_reg[18][52]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuIb>}:|㥋x=0d?㥋?M=%9H=j=̌>A?w>/?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[18][52] Jnet (fo=1, routed)Xhj=] +'SFP_GEN[18].rx_data_ngccm_reg[18][52]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)XhVm?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[18].rx_data_ngccm_reg[18][52]/C JFDCEXhzr> Jclock pessimismXh%t )%SFP_GEN[18].rx_data_ngccm_reg[18][52]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh:|; J arrival timeXhz?/ JXh4 JslackXhM=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[18].rx_data_ngccm_reg[18][73]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu?5>}jŐ=gff??N=c9H=o>̌>?w>d;?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[18][73] Jnet (fo=1, routed)Xho>] +'SFP_GEN[18].rx_data_ngccm_reg[18][73]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1H?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xho?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[18].rx_data_ngccm_reg[18][73]/C JFDCEXhzr> Jclock pessimismXhct )%SFP_GEN[18].rx_data_ngccm_reg[18][73]Hold_DFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhj; J arrival timeXh#ۉ?/ JXh4 JslackXhN=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu>} p@1=f?p?kO=~$o= =̌>I ?w> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xhrh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__17/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__17/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xhu< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhrH?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh֣p?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh~$ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXh+?/ JXh4 JslackXhkO=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C+'SFP_GEN[18].rx_data_ngccm_reg[18][65]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuQ8>}@j̒=$f??MV=VfD=+>̌>8?w>d;?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/QProp_HFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[18][65] Jnet (fo=1, routed)Xh+>] +'SFP_GEN[18].rx_data_ngccm_reg[18][65]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xho?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[18].rx_data_ngccm_reg[18][65]/C JFDCEXhzr> Jclock pessimismXhVft )%SFP_GEN[18].rx_data_ngccm_reg[18][65]Hold_AFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh@j; J arrival timeXh?/ JXh4 JslackXhMV=-sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu>}d;`,=g?d;?@%X=T.=xi=̌>S?w>Z$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_FFF_SLICEL_C_Q JFDCEXhzf9H= qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)Xh'= jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[24]_i_1__19/I1 JXhzf ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[24]_i_1__19/OProp_C6LUT_SLICEL_I1_O JLUT5XhzrQ8= `\g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg00[24] Jnet (fo=1, routed)Xho< eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh^I?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhX9t?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]/C JFDCEXhzr> Jclock pessimismXhT. c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[24]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhK?/ JXh4 JslackXh@%X=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C+'SFP_GEN[18].rx_data_ngccm_reg[18][51]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuK7>}傿(#=ˡe?(?Z=ns9H=>̌>&?w>?5?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=V rx_data[18][51] Jnet (fo=1, routed)Xh>] +'SFP_GEN[18].rx_data_ngccm_reg[18][51]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhlG?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xhzn?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[18].rx_data_ngccm_reg[18][51]/C JFDCEXhzr> Jclock pessimismXhnss )%SFP_GEN[18].rx_data_ngccm_reg[18][51]Hold_FFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh傿; J arrival timeXh_?/ JXh4 JslackXhZ=D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C/+SFP_GEN[18].ngccm_status_reg_reg[18][21]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsur@}A@0A{&?>'1(@{&@A=А=yQ@a>>X9@!?!? ?;?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_HFF_SLICEL_C_Q JFDCEXhzrO >l '#SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh-@s EASFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/I1 JXhzr D@SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/OProp_C6LUT_SLICEM_I1_O JLUT2Xhzr"y>_ rx_test_comm_cnt271_out Jnet (fo=18, routed)Xh>a /+SFP_GEN[18].ngccm_status_reg_reg[18][21]/CE JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)` .*SFP_GEN[18].ngccm_status_reg_reg[18][21]/C JFDPEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXhy ,(SFP_GEN[18].ngccm_status_reg_reg[18][21]Setup_DFF2_SLICEL_C_CE JFDPEXhGa/ JXh< J required timeXh@0A; J arrival timeXhD/ JXh4 JslackXhyQ@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C.*SFP_GEN[18].ngccm_status_reg_reg[18][7]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsur@}A@0A{&?>'1(@{&@A=А=yQ@a>>X9@!?!? ?;?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_HFF_SLICEL_C_Q JFDCEXhzrO >l '#SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh-@s EASFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/I1 JXhzr D@SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/OProp_C6LUT_SLICEM_I1_O JLUT2Xhzr"y>_ rx_test_comm_cnt271_out Jnet (fo=18, routed)Xh>` .*SFP_GEN[18].ngccm_status_reg_reg[18][7]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)_ -)SFP_GEN[18].ngccm_status_reg_reg[18][7]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXhx +'SFP_GEN[18].ngccm_status_reg_reg[18][7]Setup_AFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh@0A; J arrival timeXhD/ JXh4 JslackXhyQ@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C/+SFP_GEN[18].ngccm_status_reg_reg[18][23]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuQ@}AX0A{&?>'1(@{&@A=А=cQ@a>>@!?!? ?;?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_HFF_SLICEL_C_Q JFDCEXhzrO >l '#SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh-@s EASFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/I1 JXhzr D@SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/OProp_C6LUT_SLICEM_I1_O JLUT2Xhzr"y>_ rx_test_comm_cnt271_out Jnet (fo=18, routed)XhR>a /+SFP_GEN[18].ngccm_status_reg_reg[18][23]/CE JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)` .*SFP_GEN[18].ngccm_status_reg_reg[18][23]/C JFDPEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXhx ,(SFP_GEN[18].ngccm_status_reg_reg[18][23]Setup_DFF_SLICEL_C_CE JFDPEXh/]/ JXh< J required timeXhX0A; J arrival timeXhj/ JXh4 JslackXhcQ@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C/+SFP_GEN[18].ngccm_status_reg_reg[18][24]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuQ@}AX0A{&?>'1(@{&@A=А=cQ@a>>@!?!? ?;?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_HFF_SLICEL_C_Q JFDCEXhzrO >l '#SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh-@s EASFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/I1 JXhzr D@SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/OProp_C6LUT_SLICEM_I1_O JLUT2Xhzr"y>_ rx_test_comm_cnt271_out Jnet (fo=18, routed)XhR>a /+SFP_GEN[18].ngccm_status_reg_reg[18][24]/CE JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)` .*SFP_GEN[18].ngccm_status_reg_reg[18][24]/C JFDPEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXhx ,(SFP_GEN[18].ngccm_status_reg_reg[18][24]Setup_CFF_SLICEL_C_CE JFDPEXh/]/ JXh< J required timeXhX0A; J arrival timeXhj/ JXh4 JslackXhcQ@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C.*SFP_GEN[18].ngccm_status_reg_reg[18][5]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuQ@}AX0A{&?>'1(@{&@A=А=cQ@a>>@!?!? ?;?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_HFF_SLICEL_C_Q JFDCEXhzrO >l '#SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh-@s EASFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/I1 JXhzr D@SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/OProp_C6LUT_SLICEM_I1_O JLUT2Xhzr"y>_ rx_test_comm_cnt271_out Jnet (fo=18, routed)XhR>` .*SFP_GEN[18].ngccm_status_reg_reg[18][5]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)_ -)SFP_GEN[18].ngccm_status_reg_reg[18][5]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXhw +'SFP_GEN[18].ngccm_status_reg_reg[18][5]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhX0A; J arrival timeXhj/ JXh4 JslackXhcQ@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C.*SFP_GEN[18].ngccm_status_reg_reg[18][8]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuQ@}AX0A{&?>'1(@{&@A=А=cQ@a>>@!?!? ?;?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_HFF_SLICEL_C_Q JFDCEXhzrO >l '#SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh-@s EASFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/I1 JXhzr D@SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/OProp_C6LUT_SLICEM_I1_O JLUT2Xhzr"y>_ rx_test_comm_cnt271_out Jnet (fo=18, routed)XhR>` .*SFP_GEN[18].ngccm_status_reg_reg[18][8]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)_ -)SFP_GEN[18].ngccm_status_reg_reg[18][8]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXhw +'SFP_GEN[18].ngccm_status_reg_reg[18][8]Setup_BFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhX0A; J arrival timeXhj/ JXh4 JslackXhcQ@0D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C62g_clock_rate_din[18].ngccm_status_cnt_reg[18][7]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsue;@}AT[2A}?%2>'1(@}?%@A=А=bR@a><>q=@!?!? ??5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_HFF_SLICEL_C_Q JFDCEXhzrO >l '#SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh-@{ MISFP_GEN[18].ngCCM_gbt/g_clock_rate_din[18].ngccm_status_cnt[18][7]_i_1/I2 JXhzr LHSFP_GEN[18].ngCCM_gbt/g_clock_rate_din[18].ngccm_status_cnt[18][7]_i_1/OProp_C5LUT_SLICEM_I2_O JLUT4XhzrL7>b SFP_GEN[18].ngCCM_gbt_n_392 Jnet (fo=1, routed)Xh?h 62g_clock_rate_din[18].ngccm_status_cnt_reg[18][7]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)h 62g_clock_rate_din[18].ngccm_status_cnt_reg[18][7]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh 40g_clock_rate_din[18].ngccm_status_cnt_reg[18][7]Setup_HFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXhT[2A; J arrival timeXhS/ JXh4 JslackXhbR@0D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C62g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu&@}AT[2A}?%2>'1(@}?%@A=А=YV@a>l> @!?!? ??5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_HFF_SLICEL_C_Q JFDCEXhzrO >l '#SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)XhȊ@{ MISFP_GEN[18].ngCCM_gbt/g_clock_rate_din[18].ngccm_status_cnt[18][2]_i_1/I2 JXhzr LHSFP_GEN[18].ngCCM_gbt/g_clock_rate_din[18].ngccm_status_cnt[18][2]_i_1/OProp_H5LUT_SLICEL_I2_O JLUT4Xhzr7A>b SFP_GEN[18].ngCCM_gbt_n_417 Jnet (fo=1, routed)Xhv>h 62g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)h 62g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh 40g_clock_rate_din[18].ngccm_status_cnt_reg[18][2]Setup_FFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXhT[2A; J arrival timeXh|?/ JXh4 JslackXhYV@2D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C62g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]/D""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu@}Ac2A}?%2>'1(@}?%@A=А=%X@a>V>E@!?!? ??5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_HFF_SLICEL_C_Q JFDCEXhzrO >l '#SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh5^@{ MISFP_GEN[18].ngCCM_gbt/g_clock_rate_din[18].ngccm_status_cnt[18][5]_i_1/I2 JXhzr LHSFP_GEN[18].ngCCM_gbt/g_clock_rate_din[18].ngccm_status_cnt[18][5]_i_1/OProp_D5LUT_SLICEM_I2_O JLUT4Xhzr>b SFP_GEN[18].ngCCM_gbt_n_412 Jnet (fo=1, routed)Xh>h 62g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)h 62g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]/C JFDREXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh 40g_clock_rate_din[18].ngccm_status_cnt_reg[18][5]Setup_GFF2_SLICEM_C_D JFDREXh=/ JXh< J required timeXhc2A; J arrival timeXh9/ JXh4 JslackXh%X@D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C/+SFP_GEN[18].ngccm_status_reg_reg[18][19]/CE""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu@}Aߜ0A&>>'1(@&@A=А=-Z@a>>;ߓ@!?!? ?w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/QProp_HFF_SLICEL_C_Q JFDCEXhzrO >l '#SFP_GEN[18].ngCCM_gbt/RX_CLKEN_O[0] Jnet (fo=137, routed)Xh-@s EASFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/I1 JXhzr D@SFP_GEN[18].ngCCM_gbt/SFP_GEN[18].ngccm_status_reg[18][24]_i_1/OProp_C6LUT_SLICEM_I1_O JLUT2Xhzr"y>_ rx_test_comm_cnt271_out Jnet (fo=18, routed)Xh">a /+SFP_GEN[18].ngccm_status_reg_reg[18][19]/CE JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[1].gbtbank_n_84 Jnet (fo=674, routed)XhD @X4Y8 (CLOCK_ROOT)` .*SFP_GEN[18].ngccm_status_reg_reg[18][19]/C JFDPEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXhy ,(SFP_GEN[18].ngccm_status_reg_reg[18][19]Setup_EFF2_SLICEL_C_CE JFDPEXhim/ JXh< J required timeXhߜ0A; J arrival timeXh'1/ JXh4 JslackXh-Z@( !gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!)y@1y @9Ay@Iy @eB@hq} d=  > rise - rise rise - rise  F+'SFP_GEN[19].rx_data_ngccm_reg[19][76]/C0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[76]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu +>} ד=r? ד?d=J)ʡ=X9=I>?A>O-?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR)x +'SFP_GEN[19].rx_data_ngccm_reg[19][76]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H=w 40g_gbt_bank[1].gbtbank/RX_Word_rx40_reg[78]_3[52] Jnet (fo=1, routed)Xht=b 40g_gbt_bank[1].gbtbank/RX_Word_rx40[76]_i_1__3/I1 JXhzr 3/g_gbt_bank[1].gbtbank/RX_Word_rx40[76]_i_1__3/OProp_D6LUT_SLICEL_I1_O JLUT3Xhzr<w 40SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[83]_0[42] Jnet (fo=1, routed)Xho<b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[76]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_94 Jnet (fo=674, routed)XhkT?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[19].rx_data_ngccm_reg[19][76]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhp}?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[76]/C JFDCEXhzr> Jclock pessimismXhJ)x .*SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[76]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhَ?/ JXh4 JslackXhd=$eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]/Ceag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[35]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuMb>}?:33;=Nbp?33?!f =)9H=j=I>1 ?A>0,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[35] Jnet (fo=1, routed)Xhj= eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[35]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-R?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[35]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(|?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[35]/C JFDCEXhzr> Jclock pessimismXh) c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[35]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh?:; J arrival timeXhp=?/ JXh4 JslackXh!f =H+'SFP_GEN[19].rx_data_ngccm_reg[19][74]/C0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu 0>}wt=q?t?-2,=;-={=I>O ?A>D,?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR)y +'SFP_GEN[19].rx_data_ngccm_reg[19][74]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD=w 40g_gbt_bank[1].gbtbank/RX_Word_rx40_reg[78]_3[50] Jnet (fo=1, routed)Xhrh=b 40g_gbt_bank[1].gbtbank/RX_Word_rx40[74]_i_1__3/I1 JXhzr 3/g_gbt_bank[1].gbtbank/RX_Word_rx40[74]_i_1__3/OProp_F5LUT_SLICEL_I1_O JLUT3Xhzrw=w 40SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[83]_0[41] Jnet (fo=1, routed)XhA`e<b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[1].gbtbank_n_94 Jnet (fo=674, routed)XhtS?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[19].rx_data_ngccm_reg[19][74]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh |?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]/C JFDCEXhzr> Jclock pessimismXh;y .*SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[74]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhw; J arrival timeXhَ?/ JXh4 JslackXh-2,=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C+'SFP_GEN[19].rx_data_ngccm_reg[19][38]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuX94>}>&ǝ=nr??/=&9H=J >I>|?A>-?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[19][38] Jnet (fo=1, routed)XhJ >] +'SFP_GEN[19].rx_data_ngccm_reg[19][38]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhY9T?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_94 Jnet (fo=674, routed)Xh}?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[19].rx_data_ngccm_reg[19][38]/C JFDCEXhzr> Jclock pessimismXh&t )%SFP_GEN[19].rx_data_ngccm_reg[19][38]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh>; J arrival timeXhw?/ JXh4 JslackXh/=6g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu^d;>}㊿k = -r?k?3==E=I> ?A>/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/O83[0] Jnet (fo=2, routed)XhP= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__18/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__18/OProp_B6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/I7[0] Jnet (fo=1, routed)Xhu< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh㊿; J arrival timeXh?/ JXh4 JslackXh3=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C+'SFP_GEN[19].rx_data_ngccm_reg[19][56]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsut>}[333=&q?33?>4=(D==I> ?A>0,?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[19][56] Jnet (fo=1, routed)Xh=] +'SFP_GEN[19].rx_data_ngccm_reg[19][56]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhR?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_94 Jnet (fo=674, routed)Xh(|?X4Y8 (CLOCK_ROOT)] +'SFP_GEN[19].rx_data_ngccm_reg[19][56]/C JFDCEXhzr> Jclock pessimismXh(t )%SFP_GEN[19].rx_data_ngccm_reg[19][56]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh[; J arrival timeXh ?/ JXh4 JslackXh>4=_[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]/C]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuE6>}\K=o?\? 5=jʡ==I> ?A>*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]/QProp_DFF2_SLICEL_C_Q JFDCEXhzf9H= YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress[2] Jnet (fo=8, routed)Xh= b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_i_1__18/I3 JXhzf a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_i_1__18/OProp_C6LUT_SLICEM_I3_O JLUT6Xhzr< WSg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd Jnet (fo=1, routed)Xho< ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhaP?X4Y8 (CLOCK_ROOT) _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/psAddress_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhGz?X4Y8 (CLOCK_ROOT) ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_reg/C JFDCEXhzr> Jclock pessimismXhj [Wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/bitSlipCmd_regHold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhV?/ JXh4 JslackXh 5=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C*&SFP_GEN[19].rx_data_ngccm_reg[19][1]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuS>}wX92S=shq?X9?oB=d'D="=I>V ?A>{.?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_HFF_SLICEL_C_Q JFDREXhzrD=U rx_data[19][1] Jnet (fo=1, routed)Xh"=\ *&SFP_GEN[19].rx_data_ngccm_reg[19][1]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh33S?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[1].gbtbank_n_94 Jnet (fo=674, routed)Xh@5~?X4Y8 (CLOCK_ROOT)\ *&SFP_GEN[19].rx_data_ngccm_reg[19][1]/C JFDCEXhzr> Jclock pessimismXhd'r ($SFP_GEN[19].rx_data_ngccm_reg[19][1]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhw; J arrival timeXhD?/ JXh4 JslackXhoB=]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/C]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsui;=}|\)ף; ?A>*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/ready_from_bitSlipCtrller_7 Jnet (fo=2, routed)Xh+= b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_i_1__18/I2 JXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_i_1__18/OProp_A6LUT_SLICEM_I2_O JLUT3Xhzru< c_g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_i_1__18_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y8 (CLOCK_ROOT) ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhGz?X4Y8 (CLOCK_ROOT) ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXh7O [Wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].rxBitSlipControl/READY_o_regHold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh|; J arrival timeXhU?/ JXh4 JslackXhD=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu^d;>}? ד=q? ד?SH=g6=E=I>O ?A>O-?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__18/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__18/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhtS?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp}?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXhg6 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh?; J arrival timeXhA?/ JXh4 JslackXhSH=}!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu[d@}A\W,A(@@A=А=B@b>}??(\@!?S?n?/?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh/@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/OProp_G6LUT_SLICEM_I0_O JLUT4Xhzr1,> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh\> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__18/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__18/OProp_H5LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__18_n_0 Jnet (fo=1, routed)Xhq> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__18/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__18/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__18_n_0 Jnet (fo=2, routed)Xh~j> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhff?X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh\W,A; J arrival timeXh/ JXh4 JslackXhB@ }!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu$@}Ag,A/x(@/@A=А=L@b>}??Q@!?S?n?h?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh/@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/OProp_G6LUT_SLICEM_I0_O JLUT4Xhzr1,> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh\> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__18/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__18/OProp_H5LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__18_n_0 Jnet (fo=1, routed)Xhq> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__18/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__18/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__18_n_0 Jnet (fo=2, routed)Xhr> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhg,A; J arrival timeXhgf/ JXh4 JslackXhL@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuW9@}A O,Ak(@k@A=А=F`@b>?&I@!?S?n?O?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh/@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/OProp_G6LUT_SLICEM_I0_O JLUT4Xhzr1,> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhA> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__19/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__19/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr֣p> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh|> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+?X4Y8 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh O,A; J arrival timeXhz/ JXh4 JslackXhF`@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu@}Aj[,Ak(@k@A=А=q`@b>?aH@!?S?n?O?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh/@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/OProp_G6LUT_SLICEM_I0_O JLUT4Xhzr1,> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhA> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__19/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__19/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr֣p> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhp> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+?X4Y8 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhj[,A; J arrival timeXhZ/ JXh4 JslackXhq`@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu@}Aj[,Ak(@k@A=А=q`@b>?aH@!?S?n?O?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh/@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/OProp_G6LUT_SLICEM_I0_O JLUT4Xhzr1,> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhA> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__19/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__19/OProp_E6LUT_SLICEL_I5_O JLUT6Xhzr֣p> `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhp> vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+?X4Y8 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhj[,A; J arrival timeXhZ/ JXh4 JslackXhq`@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu@}A6,AZ^(@Z@A=А=xh@b>پ?r@@!?S?n?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh/@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/OProp_G6LUT_SLICEM_I0_O JLUT4Xhzr1,> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhĠ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/OProp_B6LUT_SLICEL_I3_O JLUT5Xhzr!r> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhX> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh6,A; J arrival timeXh'1/ JXh4 JslackXhxh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuΏ@}A:,AX9qý(@X9@A=А=#h@b>پ?'1@@!?S?n?I?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh/@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/OProp_G6LUT_SLICEM_I0_O JLUT4Xhzr1,> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhĠ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/OProp_B6LUT_SLICEL_I3_O JLUT5Xhzr!r> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhK> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh:,A; J arrival timeXhb/ JXh4 JslackXh#h@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuΏ@}A:,AX9qý(@X9@A=А=#h@b>پ?'1@@!?S?n?I?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh/@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/OProp_G6LUT_SLICEM_I0_O JLUT4Xhzr1,> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhĠ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/OProp_B6LUT_SLICEL_I3_O JLUT5Xhzr!r> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhK> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh:,A; J arrival timeXhb/ JXh4 JslackXh#h@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu@}A?,AX9qý(@X9@A=А= i@b>پ??@!?S?n?I?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh/@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/OProp_G6LUT_SLICEM_I0_O JLUT4Xhzr1,> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhĠ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/OProp_B6LUT_SLICEL_I3_O JLUT5Xhzr!r> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh}?> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh?,A; J arrival timeXh/ JXh4 JslackXh i@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu@}A?,AX9qý(@X9@A=А= i@b>پ??@!?S?n?I?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh/@ qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/I0 JXhzf plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__18/OProp_G6LUT_SLICEM_I0_O JLUT4Xhzr1,> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhĠ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__19/OProp_B6LUT_SLICEL_I3_O JLUT5Xhzr!r> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh}?> tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh?,A; J arrival timeXh/ JXh4 JslackXh i@ ( !gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!)y@1y @9Ay@Iy @e6T@hq} &=  >  rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C+'SFP_GEN[20].rx_data_ngccm_reg[20][47]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuUb>}4,i5=jt?,?&=U3D=v=Ƌ>ף?Ġ>n2?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=V rx_data[20][47] Jnet (fo=1, routed)Xhv=] +'SFP_GEN[20].rx_data_ngccm_reg[20][47]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh+V?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_104 Jnet (fo=674, routed)Xhsh?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[20].rx_data_ngccm_reg[20][47]/C JFDCEXhzr> Jclock pessimismXhU3t )%SFP_GEN[20].rx_data_ngccm_reg[20][47]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh4; J arrival timeXhj?/ JXh4 JslackXh&=r0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]/CHDSFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu6$>}ף' {='1h?ף?i 3=P%D=l=Ƌ>?Ġ>&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR)~ 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]/QProp_CFF2_SLICEL_C_Q JFDCEXhzrD=q .*SFP_GEN[20].ngCCM_gbt/gbt_rx_checker/Q[10] Jnet (fo=2, routed)Xhl=z HDSFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhI?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[26]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[20].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh= w?X4Y9 (CLOCK_ROOT)z HDSFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]/C JFDREXhzr> Jclock pessimismXhP% FBSFP_GEN[20].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[10]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh:?/ JXh4 JslackXhi 3=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C+'SFP_GEN[20].rx_data_ngccm_reg[20][70]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu*\>}E$=u?E?(3= 2D=j=Ƌ>sh?Ġ>1?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_BFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[20][70] Jnet (fo=1, routed)Xhj=] +'SFP_GEN[20].rx_data_ngccm_reg[20][70]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhKW?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_104 Jnet (fo=674, routed)Xh&?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[20].rx_data_ngccm_reg[20][70]/C JFDCEXhzr> Jclock pessimismXh 2t )%SFP_GEN[20].rx_data_ngccm_reg[20][70]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh(3=+'SFP_GEN[20].rx_data_ngccm_reg[20][30]/C0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuZd;>}v=gff?v?C4=Z!9H=K7 >Ƌ>M?Ġ>M"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR)x +'SFP_GEN[20].rx_data_ngccm_reg[20][30]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[83]_0[22] Jnet (fo=1, routed)XhK7 >b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[1].gbtbank_n_104 Jnet (fo=674, routed)Xh'1H?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[20].rx_data_ngccm_reg[20][30]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh!r?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]/C JFDCEXhzr> Jclock pessimismXhZ!y .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[30]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhC4=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu^d;>}mŊˡ1=nr?ˡ?Q;=:=E=Ƌ>V?Ġ>ף0?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__19/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__19/OProp_H6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhY9T?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh: g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhmŊ; J arrival timeXhأ?/ JXh4 JslackXhQ;=+'SFP_GEN[20].rx_data_ngccm_reg[20][27]/C0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsup=>}v=gff?v?t<=Z!9H=C >Ƌ>M?Ġ>M"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR)x +'SFP_GEN[20].rx_data_ngccm_reg[20][27]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[83]_0[19] Jnet (fo=1, routed)XhC >b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[1].gbtbank_n_104 Jnet (fo=674, routed)Xh'1H?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[20].rx_data_ngccm_reg[20][27]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh!r?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzr> Jclock pessimismXhZ!y .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[27]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhH?/ JXh4 JslackXht<=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu%>} َJi5=gff?َ?S?=/=Y=Ƌ>M?Ġ>n#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)XhP= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__19/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__19/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1H?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhts?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh/ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXh?/ JXh4 JslackXhS?=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuz>}oR?)=yf?R?1LC=/=`P=Ƌ>?Ġ>"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_19_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__19/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__19/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh:H?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh33s?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXh/ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXho; J arrival timeXh?/ JXh4 JslackXh1LC=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuz>}| R?)=+g?R?1LC=.=`P=Ƌ>o?Ġ>"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__19/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__19/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhH?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh33s?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh. g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh| ; J arrival timeXh$?/ JXh4 JslackXh1LC=B+'SFP_GEN[20].rx_data_ngccm_reg[20][67]/C0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]/D"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu">},p[=t?,?J=)A`=@=Ƌ>a?Ġ>n2?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR)x +'SFP_GEN[20].rx_data_ngccm_reg[20][67]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[83]_0[59] Jnet (fo=1, routed)Xht=_ 1-SFP_GEN[20].ngCCM_gbt/RX_Word_rx40[66]_i_1/I0 JXhzr 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40[66]_i_1/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr%=u 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40[66]_i_1_n_0 Jnet (fo=1, routed)XhX94<b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[1].gbtbank_n_104 Jnet (fo=674, routed)XhV?X4Y9 (CLOCK_ROOT)] +'SFP_GEN[20].rx_data_ngccm_reg[20][67]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhsh?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]/C JFDCEXhzr> Jclock pessimismXh)y .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[66]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhَ?/ JXh4 JslackXhJ=d!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu&@}A_,Aj5^*@j@A=А=6T@h>/?F;@ ?O?rh?/?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhy? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr֣p> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19_n_0 Jnet (fo=1, routed)Xhl> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19/OProp_B6LUT_SLICEL_I5_O JLUT6XhzrA`> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19_n_0 Jnet (fo=2, routed)Xh ? kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhT?X4Y9 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh_,A; J arrival timeXhV/ JXh4 JslackXh6T@ d!g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuQ@}AǓ,A~?!ҽ5^*@~?@A=А=Mg@h>/?J *@ ?O?rh?ٮ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhy? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19/I2 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr֣p> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__19_n_0 Jnet (fo=1, routed)Xhl> okg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19/I5 JXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19/OProp_B6LUT_SLICEL_I5_O JLUT6XhzrA`> plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__19_n_0 Jnet (fo=2, routed)Xh!> kgg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhP?X4Y9 (CLOCK_ROOT) jfg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh hdg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhǓ,A; J arrival timeXh/ JXh4 JslackXhMg@ rg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuҁ@}A,Ao5^*@@A=А=#f@ph>Q?|@ ?O?rh?A?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhy? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhC> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__20/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__20/OProp_G6LUT_SLICEL_I3_O JLUT5Xhzr)> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhd;? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhph>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh,A; J arrival timeXh / JXh4 JslackXh#f@ rg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu@}A},A{a5^*@{@A=А=*n@jh>Q?w@ ?O?rh??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhy? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhC> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__20/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__20/OProp_G6LUT_SLICEL_I3_O JLUT5Xhzr)> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhA ? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhK7?X4Y9 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhjh>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_BFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh},A; J arrival timeXh"/ JXh4 JslackXh*n@ qg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuҁ@}A,A{a5^*@{@A=А=@jh>Q?|@ ?O?rh??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhy? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhC> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__20/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__20/OProp_G6LUT_SLICEL_I3_O JLUT5Xhzr)> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhd;? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhK7?X4Y9 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhjh>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh,A; J arrival timeXh / JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu1@}A_,Aj5^*@j@A=А=ӆ@h>T?@ ?O?rh?/?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhy? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh ? xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhT?X4Y9 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh_,A; J arrival timeXhL7/ JXh4 JslackXhӆ@ rg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu~@}A,Ao5^*@@A=А=N@ph>Q?n@ ?O?rh?A?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhy? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhC> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__20/I3 JXhzr wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__20/OProp_G6LUT_SLICEL_I3_O JLUT5Xhzr)> ^Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh  ? tpg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhph>@ Jclock uncertaintyXh qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh,A; J arrival timeXhz/ JXh4 JslackXhN@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuI|@}A},A{a5^*@{@A=А==@jh>?|@ ?O?rh??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhy? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr`P= `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhˡ? vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhK7?X4Y9 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhjh>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_BFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh},A; J arrival timeXhS/ JXh4 JslackXh=@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu0|@}A,A{a5^*@{@A=А=e@jh>?d;@ ?O?rh??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhy? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/I5 JXhzr yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__20/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr`P= `\g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh? vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)XhK7?X4Y9 (CLOCK_ROOT) uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhjh>@ Jclock uncertaintyXh sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh,A; J arrival timeXh23/ JXh4 JslackXhe@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu$v@}A,g,AD 齵5^*@D@A=А=Ќ@h>T?43@ ?O?rh?p?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xhy? qmg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/I2 JXhzr plg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__19/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfFs> sog_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhˡ> |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/I0 JXhzf {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__20/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> b^g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhQ> xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh$?X4Y9 (CLOCK_ROOT) wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhh>@ Jclock uncertaintyXh uqg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,g,A; J arrival timeXhA/ JXh4 JslackXhЌ@ ( !gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!)y@1y @9Ay@Iy @e1@hq}  = > rise - rise rise - rise  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C+'SFP_GEN[21].rx_data_ngccm_reg[21][61]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuG>}߫¿nҿ=V?n? =m7D=+>-?I,?S#?KW?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=V rx_data[21][61] Jnet (fo=1, routed)Xh+>] +'SFP_GEN[21].rx_data_ngccm_reg[21][61]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhd;?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)XhO?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][61]/C JFDCEXhzr> Jclock pessimismXhm7t )%SFP_GEN[21].rx_data_ngccm_reg[21][61]Hold_AFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh߫¿; J arrival timeXhK?/ JXh4 JslackXh =g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuJ>}߫¿nҿ=V?n?F =m7==-?I,?S#?KW?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__20/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__20/OProp_B6LUT_SLICEM_I0_O JLUT3XhzrY= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xhu< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhd;?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhm7 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh߫¿; J arrival timeXh?/ JXh4 JslackXhF =g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuw>}ѮMҿ[=أ?M? =#PVo={=-?b0?S#?? W?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)XhO= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__20/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__20/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh#PV g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhѮ; J arrival timeXhG?/ JXh4 JslackXh =g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C+'SFP_GEN[21].rx_data_ngccm_reg[21][45]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu]B>}y@&ѿs=V?&?,=p7D=rh>-?I,?S#?kT?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[21][45] Jnet (fo=1, routed)Xhrh>] +'SFP_GEN[21].rx_data_ngccm_reg[21][45]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhd;?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xh1?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][45]/C JFDCEXhzr> Jclock pessimismXhp7t )%SFP_GEN[21].rx_data_ngccm_reg[21][45]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhy@; J arrival timeXh?/ JXh4 JslackXh,=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuM>}NJ¿Mҿ=V?M?0=tp7==-?I,?S#?? W?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xh1= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__20/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__20/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrY= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhd;?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXhtp7 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhNJ¿; J arrival timeXhd?/ JXh4 JslackXh0=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C*&SFP_GEN[21].rx_data_ngccm_reg[21][4]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu>}dϿM⿭ڢL=-?M?{8=nMD=a=-?S?S#?? w?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=U rx_data[21][4] Jnet (fo=1, routed)Xha=\ *&SFP_GEN[21].rx_data_ngccm_reg[21][4]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xho?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xh/?X4Y7 (CLOCK_ROOT)\ *&SFP_GEN[21].rx_data_ngccm_reg[21][4]/C JFDCEXhzr> Jclock pessimismXhnMs ($SFP_GEN[21].rx_data_ngccm_reg[21][4]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhdϿ; J arrival timeXhB`?/ JXh4 JslackXh{8=C+'SFP_GEN[21].rx_data_ngccm_reg[21][75]/C0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[74]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuE6>}P#aпx= ?a?-8=h7X9=Q=-?=/?S#?Z9T?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR)y +'SFP_GEN[21].rx_data_ngccm_reg[21][75]/QProp_CFF2_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[83]_0[67] Jnet (fo=1, routed)Xhw=_ 1-SFP_GEN[21].ngCCM_gbt/RX_Word_rx40[74]_i_1/I0 JXhzr 0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40[74]_i_1/OProp_D5LUT_SLICEM_I0_O JLUT3Xhzr #=u 2.SFP_GEN[21].ngCCM_gbt/RX_Word_rx40[74]_i_1_n_0 Jnet (fo=1, routed)XhD<b 0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[74]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xh%?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][75]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƻ?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[74]/C JFDCEXhzr> Jclock pessimismXhh7y .*SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[74]Hold_DFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhP#; J arrival timeXhy?/ JXh4 JslackXh-8=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C+'SFP_GEN[21].rx_data_ngccm_reg[21][71]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuxh>}? п1*=<߯? ?9=[WD==-?)\/?S#?#R?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[21][71] Jnet (fo=1, routed)Xh=] +'SFP_GEN[21].rx_data_ngccm_reg[21][71]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhĠ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xh ?X4Y7 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][71]/C JFDCEXhzr> Jclock pessimismXh[Wt )%SFP_GEN[21].rx_data_ngccm_reg[21][71]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh?; J arrival timeXhK ?/ JXh4 JslackXh9=Kg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuz>} ο濭>)=-??NLC=ht=`P=-?S?S#?v~?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/feedbackRegister[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__20/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__20/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xho?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh`?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXhht g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh ο; J arrival timeXhk?/ JXh4 JslackXhNLC=g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuR>}NJ¿Mҿ=V?M?.E=tp7S=\=-?I,?S#?? W?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xh1= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__20/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__20/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr%= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)XhX94< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhd;?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr> Jclock pessimismXhtp7 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhNJ¿; J arrival timeXh;?/ JXh4 JslackXh.E=g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuMb@}Aa?A"SX"{@"S@A=А=1@>?j@h?@?i?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[10]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[10] J GTHE3_CHANNELXhzr? \Xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[12] Jnet (fo=6, routed)Xhj@ fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhj\@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh9@X4Y7 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]Setup_EFF_SLICEL_C_D JFDCEXho=/ JXh< J required timeXha?A; J arrival timeXh/ JXh4 JslackXh1@g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[74]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuE@}AW?AS"{@S@A=А=I6@>+?z@h?@??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[12]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[12] J GTHE3_CHANNELXhzr+? \Xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[14] Jnet (fo=6, routed)Xhz@ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[74]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhj\@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM:@X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[74]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[74]Setup_CFF2_SLICEM_C_D JFDCEXh+=/ JXh< J required timeXhW?A; J arrival timeXh/ JXh4 JslackXhI6@g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]/D"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu7@}A?AjTP["{@jT@A=А=F8@ס>?ق@h?@??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[2] Jnet (fo=10, routed)Xhق@ eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhj\@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC;@X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]/C JFDCEXhzr> Jclock pessimismXhס>@ Jclock uncertaintyXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[82]Setup_HFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXh?A; J arrival timeXhO/ JXh4 JslackXhF8@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[21].rx_data_ngccm_reg[21][45]/CE"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu@}AT=AIT+@IT@A=А=}9@p>>@h? @?= ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p>Y rx_data_ngccm[21] Jnet (fo=76, routed)Xh/?^ ,(SFP_GEN[21].rx_data_ngccm_reg[21][45]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xh:@X4Y7 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][45]/C JFDCEXhzr> Jclock pessimismXhp>@ Jclock uncertaintyXhv )%SFP_GEN[21].rx_data_ngccm_reg[21][45]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXhT=A; J arrival timeXhX/ JXh4 JslackXh}9@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[21].rx_data_ngccm_reg[21][53]/CE"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu@}A)=AT+@T@A=А=N9@^>>@h? @??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p>Y rx_data_ngccm[21] Jnet (fo=76, routed)XhC?^ ,(SFP_GEN[21].rx_data_ngccm_reg[21][53]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xh:@X4Y7 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][53]/C JFDCEXhzr> Jclock pessimismXh^>@ Jclock uncertaintyXhv )%SFP_GEN[21].rx_data_ngccm_reg[21][53]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh)=A; J arrival timeXhC/ JXh4 JslackXhN9@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[21].rx_data_ngccm_reg[21][55]/CE"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu@}A)=AT+@T@A=А=N9@^>>@h? @??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p>Y rx_data_ngccm[21] Jnet (fo=76, routed)XhC?^ ,(SFP_GEN[21].rx_data_ngccm_reg[21][55]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xh:@X4Y7 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][55]/C JFDCEXhzr> Jclock pessimismXh^>@ Jclock uncertaintyXhv )%SFP_GEN[21].rx_data_ngccm_reg[21][55]Setup_FFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh)=A; J arrival timeXhC/ JXh4 JslackXhN9@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[21].rx_data_ngccm_reg[21][59]/CE"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu@}A)=AT+@T@A=А=N9@^>>@h? @??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p>Y rx_data_ngccm[21] Jnet (fo=76, routed)XhC?^ ,(SFP_GEN[21].rx_data_ngccm_reg[21][59]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xh:@X4Y7 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][59]/C JFDCEXhzr> Jclock pessimismXh^>@ Jclock uncertaintyXhv )%SFP_GEN[21].rx_data_ngccm_reg[21][59]Setup_GFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh)=A; J arrival timeXhC/ JXh4 JslackXhN9@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[21].rx_data_ngccm_reg[21][44]/CE"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu @}A=AIT+@IT@A=А=a9@p>> @h? @?= ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p>Y rx_data_ngccm[21] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[21].rx_data_ngccm_reg[21][44]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xh:@X4Y7 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][44]/C JFDCEXhzr> Jclock pessimismXhp>@ Jclock uncertaintyXhu )%SFP_GEN[21].rx_data_ngccm_reg[21][44]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh=A; J arrival timeXhK/ JXh4 JslackXha9@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[21].rx_data_ngccm_reg[21][46]/CE"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu @}A=AIT+@IT@A=А=a9@p>> @h? @?= ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p>Y rx_data_ngccm[21] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[21].rx_data_ngccm_reg[21][46]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xh:@X4Y7 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][46]/C JFDCEXhzr> Jclock pessimismXhp>@ Jclock uncertaintyXhu )%SFP_GEN[21].rx_data_ngccm_reg[21][46]Setup_FFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh=A; J arrival timeXhK/ JXh4 JslackXha9@Lg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[21].rx_data_ngccm_reg[21][52]/CE"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuО@}As=AT+@T@A=А=:@^>>В@h? @??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/@ wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/I0 JXhzr vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/SFP_GEN[21].rx_data_ngccm[21][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p>Y rx_data_ngccm[21] Jnet (fo=76, routed)Xh1?^ ,(SFP_GEN[21].rx_data_ngccm_reg[21][52]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[1].gbtbank_n_114 Jnet (fo=674, routed)Xh:@X4Y7 (CLOCK_ROOT)] +'SFP_GEN[21].rx_data_ngccm_reg[21][52]/C JFDCEXhzr> Jclock pessimismXh^>@ Jclock uncertaintyXhu )%SFP_GEN[21].rx_data_ngccm_reg[21][52]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhs=A; J arrival timeXh33/ JXh4 JslackXh:@L( !gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!)y@1y @9Ay@Iy @e](#@hq}  = vv?$ rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C+'SFP_GEN[24].rx_data_ngccm_reg[24][43]/D"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu+>}蟠󭿭f=w?? =~#9H==%>G!?>C?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[24][43] Jnet (fo=1, routed)Xh=] +'SFP_GEN[24].rx_data_ngccm_reg[24][43]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[2].gbtbank_n_0 Jnet (fo=674, routed)Xh~?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[24].rx_data_ngccm_reg[24][43]/C JFDCEXhzr> Jclock pessimismXh~#s )%SFP_GEN[24].rx_data_ngccm_reg[24][43]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh蟠; J arrival timeXh?/ JXh4 JslackXh =g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuX->}O;hZ=?h?w#=$ʡ=Q=%> ?>B?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__23/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__23/OProp_G6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhA?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXh$ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhO;; J arrival timeXhk?/ JXh4 JslackXhw#=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu/>}Y{=|?{? =#ʡ=j=%> ?> C?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xh-= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__23/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__23/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xhu< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh# g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhY; J arrival timeXhA`?/ JXh4 JslackXh =g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuv>},!Nb^=%?Nb?;=aC=Y=%> #?>rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__23/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__23/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr/]= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXhaC g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh,!; J arrival timeXh?/ JXh4 JslackXh;=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C+'SFP_GEN[24].rx_data_ngccm_reg[24][42]/D"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuK>}0L=َ??k@=%#D=>%>|?>{F?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/QProp_HFF_SLICEL_C_Q JFDREXhzrD=V rx_data[24][42] Jnet (fo=1, routed)Xh>] +'SFP_GEN[24].rx_data_ngccm_reg[24][42]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[2].gbtbank_n_0 Jnet (fo=674, routed)Xh(?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[24].rx_data_ngccm_reg[24][42]/C JFDCEXhzr> Jclock pessimismXh%#s )%SFP_GEN[24].rx_data_ngccm_reg[24][42]Hold_EFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh0L; J arrival timeXhQ?/ JXh4 JslackXhk@=]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/C]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/D"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsui;=}Ȗ/֣;?/?D=Dlo=Q8=%>x?>L B?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/ready_from_bitSlipCtrller_0 Jnet (fo=2, routed)Xh+= b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_i_1__23/I2 JXhzr a]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_i_1__23/OProp_A6LUT_SLICEM_I2_O JLUT3Xhzru< c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_i_1__23_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh ?X1Y2 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh_?X1Y2 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXhDl [Wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].rxBitSlipControl/READY_o_regHold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhȖ; J arrival timeXh?/ JXh4 JslackXhD=8g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuT>}񛿍vD?)=|?v?ٕO=M=/]=%> ?>D?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/O83[1] Jnet (fo=2, routed)Xh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__23/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__23/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/I7[1] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXhM g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh񛿐; J arrival timeXhn?/ JXh4 JslackXhٕO=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuQ8>}xҭcG=?ҭ?XQ=#v=-=%>!?>SC?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xhrh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__23/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__23/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh&?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh6^?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh# g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhx; J arrival timeXh= ?/ JXh4 JslackXhXQ=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu}&>}B8b=%?? T=8YCʡ=1=%> #?>;H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)XhC= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__23/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__23/OProp_C6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh8YC g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhB; J arrival timeXhU?/ JXh4 JslackXh T=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuzj<>};hL=)\?h?$U=$[=E=%> ?>B?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xh-= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__23/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__23/OProp_F6LUT_SLICEM_I2_O JLUT3Xhzrj<= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh$ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_FFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh;; J arrival timeXhx?/ JXh4 JslackXh$U=Y!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu֣@}A}01A֣(,'=Q0@֣(@A=А=](#@tY> ?@CK??5?E?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhO_@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__23/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__23/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__23_n_0 Jnet (fo=1, routed)Xh㥛= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__23/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__23/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__23_n_0 Jnet (fo=2, routed)Xhff> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xht@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhtY>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh}01A; J arrival timeXhff/ JXh4 JslackXh](#@ Y!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu֣@}A}01A֣(,'=Q0@֣(@A=А=](#@tY> ?@CK??5?E?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhO_@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__23/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__23/OProp_C6LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_7__23_n_0 Jnet (fo=1, routed)Xh㥛= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__23/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__23/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state[1]_i_1__23_n_0 Jnet (fo=2, routed)Xhff> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xht@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhtY>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh}01A; J arrival timeXhff/ JXh4 JslackXh](#@ fg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu=߳@}A 1AQ(=Q0@Q(@A=А=p,@tY>µ?n@CK??5?ɡ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhO_@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/OProp_E6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhgf> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)XhA@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhtY>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_AFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh 1A; J arrival timeXh/ JXh4 JslackXhp,@ fg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu=߳@}A 1AQ(=Q0@Q(@A=А=p,@tY>µ?n@CK??5?ɡ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhO_@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/OProp_E6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhgf> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)XhA@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhtY>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh 1A; J arrival timeXh/ JXh4 JslackXhp,@ fg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu$@}A0Ay&ۅ=Q0@y&@A=А=k.@tY>µ?:@CK??5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhO_@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/OProp_E6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhtY>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh&/ JXh4 JslackXhk.@ gg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuM@}A 1AA(ݰ=Q0@A(@A=А=@/@tY>µ?/݄@CK??5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhO_@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/OProp_E6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhO> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh'1@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhtY>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh 1A; J arrival timeXhe;/ JXh4 JslackXh@/@ gg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuM@}A 1AA(ݰ=Q0@A(@A=А=@/@tY>µ?/݄@CK??5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhO_@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/OProp_E6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhO> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh'1@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhtY>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_GFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh 1A; J arrival timeXhe;/ JXh4 JslackXh@/@ fg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@5@}A1AA(ݰ=Q0@A(@A=А=µ?Ą@CK??5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhO_@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/OProp_E6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh'1@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhtY>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh// JXh4 JslackXhµ?Ą@CK??5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhO_@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/I0 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__24/OProp_E6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh'1@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhtY>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh// JXh4 JslackXhµ?{@CK??5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzr ? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_userdata_rx_out[1] Jnet (fo=10, routed)XhO_@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/I0 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__23/OProp_H6LUT_SLICEM_I0_O JLUT4Xhzf"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh1,> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__24/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__24/OProp_E6LUT_SLICEM_I0_O JLUT6XhzrQ= b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhO> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhtY>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh=0A; J arrival timeXh/ JXh4 JslackXh<@ ( !gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!)y@1y @9Ay@Iy @e7J@hq} f= uv?  ( rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu+>}ZGI=Nb?I?f=kʡ=X9=5^>U?>Z$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__33/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__33/OProp_G6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhoc?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԈ?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXhk g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhZG; J arrival timeXh•?/ JXh4 JslackXhf=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuv>>}ݓٞ=Ā?ٞ?>=e1=j=5^>?>x)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__33/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__33/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh c?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZd?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhe1 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhݓ; J arrival timeXhu?/ JXh4 JslackXh>=4fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[44]/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[44]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu #>}j=v~??&%=V9H=S=5^>?>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[44]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= `\g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[44] Jnet (fo=1, routed)XhS= fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[44]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh`?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[44]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh$?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[44]/C JFDCEXhzr> Jclock pessimismXhV d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[44]Hold_CFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhF?/ JXh4 JslackXh&%=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu-2>}ZGI=Nb?I?,=k-=-=5^>U?>Z$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__33/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__33/OProp_G5LUT_SLICEM_I0_O JLUT3Xhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[3] Jnet (fo=1, routed)XhT< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhoc?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԈ?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr> Jclock pessimismXhk g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]Hold_GFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhZG; J arrival timeXh?/ JXh4 JslackXh,=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C+'SFP_GEN[34].rx_data_ngccm_reg[34][55]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu>}ΏٞR=J ?ٞ?E6=19H==5^>L7 ?>x)?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[34][55] Jnet (fo=1, routed)Xh=] +'SFP_GEN[34].rx_data_ngccm_reg[34][55]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhgff?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_124 Jnet (fo=674, routed)XhZd?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[34].rx_data_ngccm_reg[34][55]/C JFDCEXhzr> Jclock pessimismXh1s )%SFP_GEN[34].rx_data_ngccm_reg[34][55]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhΏ; J arrival timeXh?/ JXh4 JslackXhE6=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C+'SFP_GEN[34].rx_data_ngccm_reg[34][67]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuX->}ϑ̜ᅉ=J ?̜?o;=#AD==5^>L7 ?>B`%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_CFF_SLICEM_C_Q JFDREXhzrD=V rx_data[34][67] Jnet (fo=1, routed)Xh=] +'SFP_GEN[34].rx_data_ngccm_reg[34][67]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhgff?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_124 Jnet (fo=674, routed)XhX?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[34].rx_data_ngccm_reg[34][67]/C JFDCEXhzr> Jclock pessimismXh#As )%SFP_GEN[34].rx_data_ngccm_reg[34][67]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhϑ; J arrival timeXh?/ JXh4 JslackXho;=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C+'SFP_GEN[34].rx_data_ngccm_reg[34][53]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuv>} W=J ??{B=19H="=5^>L7 ?>^)?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[34][53] Jnet (fo=1, routed)Xh"=] +'SFP_GEN[34].rx_data_ngccm_reg[34][53]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhgff?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_124 Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[34].rx_data_ngccm_reg[34][53]/C JFDCEXhzr> Jclock pessimismXh1s )%SFP_GEN[34].rx_data_ngccm_reg[34][53]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh{B=3fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[34]/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuT>}f-=??J=09H==5^>?>"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[34]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= `\g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[34] Jnet (fo=1, routed)Xh= fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhMb?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[34]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhb?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]/C JFDCEXhzr> Jclock pessimismXh0 d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[34]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhJ=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsut>}K󝿭=G??>UM=ژ>=L=5^>?>'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__33/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__33/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh0d?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXhژ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhK; J arrival timeXhG?/ JXh4 JslackXh>UM=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu@>} ޥ= ??P=k[=v=5^>B`?>%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xh-= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__33/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__33/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrj<= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\b?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhk g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh'1?/ JXh4 JslackXhP=!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuԜ@}A#,Ay-/,@@A=А=7J@yP>H?Y9T@MB?-?{.?Т?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn @ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33/I2 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33/OProp_D5LUT_SLICEL_I2_O JLUT4Xhzr1,> qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33_n_0 Jnet (fo=1, routed)XhZ> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33/I5 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33/OProp_G6LUT_SLICEL_I5_O JLUT6XhzrE= qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33_n_0 Jnet (fo=2, routed)Xh~> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"?X1Y4 (CLOCK_ROOT) kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhyP>@ Jclock uncertaintyXh ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh#,A; J arrival timeXhC/ JXh4 JslackXh7J@ !g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuԜ@}A#,Ay-/,@@A=А=7J@yP>H?Y9T@MB?-?{.?Т?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn @ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33/I2 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33/OProp_D5LUT_SLICEL_I2_O JLUT4Xhzr1,> qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__33_n_0 Jnet (fo=1, routed)XhZ> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33/I5 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33/OProp_G6LUT_SLICEL_I5_O JLUT6XhzrE= qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__33_n_0 Jnet (fo=2, routed)Xh~> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"?X1Y4 (CLOCK_ROOT) kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhyP>@ Jclock uncertaintyXh ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh#,A; J arrival timeXhC/ JXh4 JslackXh7J@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu"@}A,A.//,@.@A=А=IU@#P>b?q=J@MB?-?{.?[?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn @ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzf"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p> c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh5? yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh#P>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXhh/ JXh4 JslackXhIU@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu@}A ,Ab}./,@@A=А=l@|P>b? 3@MB?-?{.?!?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn @ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzf"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p> c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh&> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^?X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh|P>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh ,A; J arrival timeXh/ JXh4 JslackXhl@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu@}A ,Ab}./,@@A=А=l@|P>b? 3@MB?-?{.?!?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn @ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzf"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p> c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh&> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^?X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh|P>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh ,A; J arrival timeXh/ JXh4 JslackXhl@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsul@}A"#,Ab}./,@@A=А=Dl@|P>b?2@MB?-?{.?!?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn @ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzf"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p> c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^?X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh|P>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh"#,A; J arrival timeXh"/ JXh4 JslackXhDl@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsul@}A"#,Ab}./,@@A=А=Dl@|P>b?2@MB?-?{.?!?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn @ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzf"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xht> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__34/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr֣p> c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^?X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh|P>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh"#,A; J arrival timeXh"/ JXh4 JslackXhDl@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuԈ@}A+A 4?/,@ @A=А=Ap@P>?sh9@MB?-?{.??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn @ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhC> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/I3 JXhzr xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/OProp_C6LUT_SLICEL_I3_O JLUT5Xhzr`P= _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhC> uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhP?X1Y4 (CLOCK_ROOT) tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh+A; J arrival timeXhC/ JXh4 JslackXhAp@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsuԈ@}A+A 4?/,@ @A=А=Ap@P>?sh9@MB?-?{.??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn @ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhC> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/I3 JXhzr xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/OProp_C6LUT_SLICEL_I3_O JLUT5Xhzr`P= _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhC> uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhP?X1Y4 (CLOCK_ROOT) tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh+A; J arrival timeXhC/ JXh4 JslackXhAp@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu9@}A3+A 4?/,@ @A=А=+3q@P>?&9@MB?-?{.??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhn @ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/I3 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__33/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhC> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/I3 JXhzr xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__34/OProp_C6LUT_SLICEL_I3_O JLUT5Xhzr`P= _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh~> uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhP?X1Y4 (CLOCK_ROOT) tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhP>@ Jclock uncertaintyXh rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh3+A; J arrival timeXh"/ JXh4 JslackXh+3q@ ( !gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!)y@1y @9Ay@Iy @eQ@hq} .h= uv?!!+ rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C+'SFP_GEN[35].rx_data_ngccm_reg[35][59]/D"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuE6>},-'=\?-?.h=Z!D=>>'?A>OM?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/QProp_CFF_SLICEM_C_Q JFDREXhzrD=V rx_data[35][59] Jnet (fo=1, routed)Xh>] +'SFP_GEN[35].rx_data_ngccm_reg[35][59]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_134 Jnet (fo=674, routed)XhR?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[35].rx_data_ngccm_reg[35][59]/C JFDCEXhzr> Jclock pessimismXhZ!s )%SFP_GEN[35].rx_data_ngccm_reg[35][59]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh,; J arrival timeXhX?/ JXh4 JslackXh.h=Ng_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuz>}Þ<߯-^=ף?<߯?9 =3B%==>$?A>;H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O83[1] Jnet (fo=2, routed)XhC= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__34/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__34/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/I7[1] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhʁ?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXh3B g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhÞ; J arrival timeXh43?/ JXh4 JslackXh9 =Ng_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuX9>}Ͻİ=rh?İ?=t!v=X9=>ˡ%?A>~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_GFF2_SLICEL_C_Q JFDCEXhzrD= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O84[1] Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__34/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__34/OProp_A6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXht! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhϽ; J arrival timeXht?/ JXh4 JslackXh=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu^d;>}{=rh??!+=!v=Q=>ˡ%?A>I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__34/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__34/OProp_G6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh{; J arrival timeXhԨ?/ JXh4 JslackXh!+=8fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[34]/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[34]/D"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu #>}^%6o=rh?%?>:=J@9H=S=>ˡ%?A>K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[34]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= `\g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[34] Jnet (fo=1, routed)XhS= fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[34]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh\?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[34]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhi?X1Y4 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[34]/C JFDCEXhzr> Jclock pessimismXhJ@ d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[34]Hold_HFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh^; J arrival timeXhT?/ JXh4 JslackXh>:=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuph>} { o=rh? ?LC=5N=D=>ˡ%?A>L7I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xht= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__34/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__34/OProp_F6LUT_SLICEM_I2_O JLUT3Xhzrj<= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[5] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh5N g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_FFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh {; J arrival timeXh?/ JXh4 JslackXhLC=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuph>} { o=rh? ?LC=5N=D=>ˡ%?A>L7I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xht= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__34/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__34/OProp_E6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXh5N g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_EFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh {; J arrival timeXh?/ JXh4 JslackXhLC=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C+'SFP_GEN[35].rx_data_ngccm_reg[35][68]/D"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu*\>}Ɵв;=?в?,C=eQ9H=5^=>*?A>N?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_AFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[35][68] Jnet (fo=1, routed)Xh5^=] +'SFP_GEN[35].rx_data_ngccm_reg[35][68]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_134 Jnet (fo=674, routed)Xh)\?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[35].rx_data_ngccm_reg[35][68]/C JFDCEXhzr> Jclock pessimismXheQt )%SFP_GEN[35].rx_data_ngccm_reg[35][68]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhƟ; J arrival timeXhT?/ JXh4 JslackXh,C=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[35].rx_data_ngccm_reg[35][52]/D"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuw>}B;=I ??#E=D9H==>y&?A>I?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[35][52] Jnet (fo=1, routed)Xh=] +'SFP_GEN[35].rx_data_ngccm_reg[35][52]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh33?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_134 Jnet (fo=674, routed)XhV?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[35].rx_data_ngccm_reg[35][52]/C JFDCEXhzr> Jclock pessimismXhDt )%SFP_GEN[35].rx_data_ngccm_reg[35][52]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh#E=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[35].rx_data_ngccm_reg[35][39]/D"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu@H>}I1= ??o`H=Ƶ!D=P>>o#?A>H?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[35][39] Jnet (fo=1, routed)XhP>] +'SFP_GEN[35].rx_data_ngccm_reg[35][39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_134 Jnet (fo=674, routed)XhD?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[35].rx_data_ngccm_reg[35][39]/C JFDCEXhzr> Jclock pessimismXhƵ!s )%SFP_GEN[35].rx_data_ngccm_reg[35][39]Hold_HFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhI; J arrival timeXhL7?/ JXh4 JslackXho`H=g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu-@}AD1A(+=0@(@A=А=Q@4[>$?Q`@G?ˡ?n2?Q?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhJ *@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr!r> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh\> {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/I5 JXhzr zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr> a]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh4[>@ Jclock uncertaintyXh tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhD1A; J arrival timeXh-/ JXh4 JslackXhQ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu@}AI1A(+=0@(@A=А=Q@4[>$? `@G?ˡ?n2?Q?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhJ *@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr!r> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh\> {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/I5 JXhzr zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr> a]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh{> wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh4[>@ Jclock uncertaintyXh tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhI1A; J arrival timeXh/ JXh4 JslackXhQ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu~?@}A<1A9(=0@9(@A=А= tR@4[>$?l_@G?ˡ?n2?b?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhJ *@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr!r> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh\> {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/I5 JXhzr zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__35/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzr> a]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhr> wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhף@X1Y4 (CLOCK_ROOT) vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh4[>@ Jclock uncertaintyXh tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh<1A; J arrival timeXh~?/ JXh4 JslackXh tR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu@}A1A'I=0@'@A=А=cZ@4[>Q?~Z@G?ˡ?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhJ *@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzf!r> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh+> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/OProp_B6LUT_SLICEM_I0_O JLUT6Xhzrj= c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xhj> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh4[>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhcZ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu@}A1A'I=0@'@A=А=cZ@4[>Q?~Z@G?ˡ?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhJ *@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzf!r> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh+> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/OProp_B6LUT_SLICEM_I0_O JLUT6Xhzrj= c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xhj> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh4[>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_BFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhcZ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu̜@}A1A'I=0@'@A=А=Z@4[>Q?p=Z@G?ˡ?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhJ *@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzf!r> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh+> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/OProp_B6LUT_SLICEM_I0_O JLUT6Xhzrj= c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh5^> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh4[>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhZ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu̜@}A1A'I=0@'@A=А=Z@4[>Q?p=Z@G?ˡ?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhJ *@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzf!r> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh+> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/OProp_B6LUT_SLICEM_I0_O JLUT6Xhzrj= c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh5^> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh4[>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhZ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu @}A1A<'=0@<'@A=А=[@4[>Q?`X@G?ˡ?n2?ff?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhJ *@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzf!r> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh+> }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/I0 JXhzf |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__35/OProp_B6LUT_SLICEM_I0_O JLUT6Xhzrj= c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh4[>@ Jclock uncertaintyXh vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_GFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh / JXh4 JslackXh[@ !g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu"@}A1A'I=0@'@A=А= ^@4[>C?P@G?ˡ?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhJ *@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr!r> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhX9> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34/I2 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34/OProp_H6LUT_SLICEL_I2_O JLUT4Xhzr+> qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34_n_0 Jnet (fo=1, routed)Xh'> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34/I5 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34/OProp_H6LUT_SLICEL_I5_O JLUT6XhzrY= qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34_n_0 Jnet (fo=2, routed)Xh}> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh4[>@ Jclock uncertaintyXh ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh1A; J arrival timeXh"/ JXh4 JslackXh ^@ !g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu"@}A1A'I=0@'@A=А= ^@4[>C?P@G?ˡ?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)XhJ *@ rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/I2 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__34/OProp_B6LUT_SLICEL_I2_O JLUT4Xhzr!r> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhX9> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34/I2 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34/OProp_H6LUT_SLICEL_I2_O JLUT4Xhzr+> qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__34_n_0 Jnet (fo=1, routed)Xh'> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34/I5 JXhzr okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34/OProp_H6LUT_SLICEL_I5_O JLUT6XhzrY= qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__34_n_0 Jnet (fo=2, routed)Xh}> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> lhg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh4[>@ Jclock uncertaintyXh ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh1A; J arrival timeXh"/ JXh4 JslackXh ^@ ( !gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!)y@1y @9Ay@Iy @e};@hq} B< uv?"". rise - rise rise - rise  E+'SFP_GEN[25].rx_data_ngccm_reg[25][69]/C0,SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[68]/D"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuK7>}r|=|?|?B<!={=>$!?G>lG?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR)y +'SFP_GEN[25].rx_data_ngccm_reg[25][69]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD=u 2.g_gbt_bank[2].gbtbank/RX_Word_rx40_reg[78][45] Jnet (fo=1, routed)Xh=b 40g_gbt_bank[2].gbtbank/RX_Word_rx40[68]_i_1__4/I0 JXhzr 3/g_gbt_bank[2].gbtbank/RX_Word_rx40[68]_i_1__4/OProp_F6LUT_SLICEM_I0_O JLUT3Xhzrj<=w 40SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[83]_0[38] Jnet (fo=1, routed)XhD<b 0,SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[68]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)Xhף?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][69]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[68]/C JFDCEXhzr> Jclock pessimismXh!x .*SFP_GEN[25].ngCCM_gbt/RX_Word_rx40_reg[68]Hold_FFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhr; J arrival timeXhff?/ JXh4 JslackXhB<:,(SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg/C,(SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_reg/D"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu9H>}LM=A?M?o=a!o=+>>]"?G>WM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR)y ,(SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H=i &"SFP_GEN[25].ngCCM_gbt/pwr_good_pre Jnet (fo=1, routed)Xhi=^ 0,SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_i_1__4/I1 JXhzr /+SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_i_1__4/OProp_C6LUT_SLICEM_I1_O JLUT4Xhzru<t 1-SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_i_1__4_n_0 Jnet (fo=1, routed)Xho<^ ,(SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_reg/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhsh?X1Y2 (CLOCK_ROOT)^ ,(SFP_GEN[25].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[25].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhٞ?X1Y2 (CLOCK_ROOT)^ ,(SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_reg/C JFDREXhzr> Jclock pessimismXha!t *&SFP_GEN[25].ngCCM_gbt/pwr_good_cnt_regHold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhL; J arrival timeXhX?/ JXh4 JslackXho=$eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[93]/D"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsut>}J )_=\?J ?z=bC9H=[=>+'?G>CL?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[93] Jnet (fo=1, routed)Xh[= eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[93]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[93]/C JFDCEXhzr> Jclock pessimismXhbC c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[93]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhz=#eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]/D"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu(>} W=\? ?=G_!D==>+'?G>9H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[23] Jnet (fo=1, routed)Xh= eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[23]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]/C JFDCEXhzr> Jclock pessimismXhG_! c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[23]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh="rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]/Cb^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv/D"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu >}穞w x=w?w?0B=Ao=E=>8!?G>G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]/QProp_CFF2_SLICEM_C_Q JFDCEXhzfD= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnt[4] Jnet (fo=4, routed)XhP= gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_inv_i_1__25/I1 JXhzf fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_inv_i_1__25/OProp_B6LUT_SLICEM_I1_O JLUT6Xhzro< ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr3_out Jnet (fo=1, routed)Xhu< b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv/D JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X1Y2 (CLOCK_ROOT) rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/bitSlipCnter_proc.bitSlipCnt_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhI?X1Y2 (CLOCK_ROOT) b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_inv/C JFDPEXhzr> Jclock pessimismXhA `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/shiftPsAddr_reg_invHold_BFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXh穞; J arrival timeXhS?/ JXh4 JslackXh0B=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C+'SFP_GEN[25].rx_data_ngccm_reg[25][77]/D"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsun>}}Dp'%L=R?p?5=GBD=\=>|?G>SC?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[25][77] Jnet (fo=1, routed)Xh\=] +'SFP_GEN[25].rx_data_ngccm_reg[25][77]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][77]/C JFDCEXhzr> Jclock pessimismXhGBt )%SFP_GEN[25].rx_data_ngccm_reg[25][77]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh}D; J arrival timeXh%?/ JXh4 JslackXh5=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C+'SFP_GEN[25].rx_data_ngccm_reg[25][66]/D"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu~>}쨞w|=?w?ג=iBD=/=>G!?G>G?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_HFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[25][66] Jnet (fo=1, routed)Xh/=] +'SFP_GEN[25].rx_data_ngccm_reg[25][66]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhĀ?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_34 Jnet (fo=674, routed)XhI?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[25].rx_data_ngccm_reg[25][66]/C JFDCEXhzr> Jclock pessimismXhiBt )%SFP_GEN[25].rx_data_ngccm_reg[25][66]Hold_CFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh쨞; J arrival timeXh?/ JXh4 JslackXhג=#eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[76]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]/D"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuw>}wʱW=\?ʱ?E%=>C9H==>+'?G>2L?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[76]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[76] Jnet (fo=1, routed)Xh= eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[76]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhV?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]/C JFDCEXhzr> Jclock pessimismXh>C c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]Hold_GFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhw; J arrival timeXhˡ?/ JXh4 JslackXhE%=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu&1>}ܘ=??-=#! ף=v=>)?G>K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xh-= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__24/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__24/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh#! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh-=$eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[46]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[46]/D"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuz>}ϟ&}:=В?&? 2=DD==>'?G>J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[46]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[46] Jnet (fo=1, routed)Xh= eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[46]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[46]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[46]/C JFDCEXhzr> Jclock pessimismXhD c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[46]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhϟ; J arrival timeXhB`?/ JXh4 JslackXh 2=g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsup@}A91Aa(L =+.@a(@A=А=};@GW> ?A`u@I??}?5?> ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhsh9@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh:? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhV> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhGW>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh91A; J arrival timeXhZ/ JXh4 JslackXh};@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsup@}A91Aa(L =+.@a(@A=А=};@GW> ?A`u@I??}?5?> ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhsh9@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh:? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhV> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhGW>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh91A; J arrival timeXhZ/ JXh4 JslackXh};@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu@}AA1A$)#=+.@$)@A=А=>@GW> ?5^r@I??}?5?K?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhsh9@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh:? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhE> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhGW>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhA1A; J arrival timeXh/ JXh4 JslackXh>@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu ׫@}AE1A$)#=+.@$)@A=А=4>@GW> ? -r@I??}?5?K?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhsh9@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh:? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhj> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhGW>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhE1A; J arrival timeXhP/ JXh4 JslackXh4>@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuv@}A0A'O:=+.@'@A=А=[@@GW> ?lo@I??}?5?0?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhsh9@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh:? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhR> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhGW>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh// JXh4 JslackXh[@@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu5^@}A 0A'O:=+.@'@A=А=@@GW> ?e;o@I??}?5?0?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhsh9@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh:? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh/> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhGW>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh 0A; J arrival timeXh/ JXh4 JslackXh@@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu5^@}A 0A'O:=+.@'@A=А=@@GW> ?e;o@I??}?5?0?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhsh9@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh:? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__25/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh/> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw@X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhGW>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh 0A; J arrival timeXh/ JXh4 JslackXh@@ }!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu$@}A%1A(=+.@(@A=А=I@GW>p?ie@I??}?5?E?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhsh9@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xho> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24_n_0 Jnet (fo=1, routed)Xh1= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24_n_0 Jnet (fo=2, routed)Xh33> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhGW>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh%1A; J arrival timeXhrh/ JXh4 JslackXhI@ }!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu$@}A%1A(=+.@(@A=А=I@GW>p?ie@I??}?5?E?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xhsh9@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__24/OProp_D6LUT_SLICEL_I1_O JLUT4XhzrFs> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xho> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_7__24_n_0 Jnet (fo=1, routed)Xh1= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state[1]_i_1__24_n_0 Jnet (fo=2, routed)Xh33> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhGW>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].patternSearch/FSM_sequential_state_reg[1]Setup_CFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh%1A; J arrival timeXhrh/ JXh4 JslackXhI@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[116]/D"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu@}AF3Ao+V >+.@o+@A=А=K@GW>"?S@I??}?5?Zd?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[14]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[14] J GTHE3_CHANNELXhzr"? \Xg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/D[16] Jnet (fo=6, routed)XhS@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[116]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhS@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[116]/C JFDCEXhzr> Jclock pessimismXhGW>@ Jclock uncertaintyXh d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[116]Setup_EFF_SLICEL_C_D JFDCEXho=/ JXh< J required timeXhF3A; J arrival timeXh / JXh4 JslackXhK@( !gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!)y@1y @9Ay@Iy @e\@hq} p = vv?##2 rise - rise rise - rise  =+'SFP_GEN[26].rx_data_ngccm_reg[26][76]/C0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[76]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuX9>} 1ǯ=/}?1?p =K=-=j>G?/>]"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR)y +'SFP_GEN[26].rx_data_ngccm_reg[26][76]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[83]_0[68] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[76]_i_1/I1 JXhzr 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[76]_i_1/OProp_G6LUT_SLICEL_I1_O JLUT3XhzrQ8=u 2.SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[76]_i_1_n_0 Jnet (fo=1, routed)XhA`e<b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[76]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xh|_?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[26].rx_data_ngccm_reg[26][76]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[76]/C JFDCEXhzr> Jclock pessimismXhKx .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[76]Hold_GFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh ; J arrival timeXh•?/ JXh4 JslackXhp =g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu@>}!j=|?j?#,=={=j>%?/>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__25/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__25/OProp_C5LUT_SLICEL_I2_O JLUT3XhzrGa= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)XhX94< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;_?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh!; J arrival timeXh,?/ JXh4 JslackXh#,=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C+'SFP_GEN[26].rx_data_ngccm_reg[26][22]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuE6>}dSh=sh?h?z;=-H9H=>j>y?/>ˡ%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[26][22] Jnet (fo=1, routed)Xh>] +'SFP_GEN[26].rx_data_ngccm_reg[26][22]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[26].rx_data_ngccm_reg[26][22]/C JFDCEXhzr> Jclock pessimismXh-Ht )%SFP_GEN[26].rx_data_ngccm_reg[26][22]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhdS; J arrival timeXh(1?/ JXh4 JslackXhz;=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuϡE>}!j=|?j?+A==j=j>%?/>S#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh-= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__25/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__25/OProp_B6LUT_SLICEL_I0_O JLUT3XhzrY= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xhu< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;_?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh!; J arrival timeXh+?/ JXh4 JslackXh+A=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C+'SFP_GEN[26].rx_data_ngccm_reg[26][29]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuQ8>}p=&?p?D= P9H=$>j>ff?/>B`%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=V rx_data[26][29] Jnet (fo=1, routed)Xh$>] +'SFP_GEN[26].rx_data_ngccm_reg[26][29]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhd?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[26].rx_data_ngccm_reg[26][29]/C JFDCEXhzr> Jclock pessimismXh Pt )%SFP_GEN[26].rx_data_ngccm_reg[26][29]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXh'1?/ JXh4 JslackXhD=eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsui;=}hnv֣;…?n?ћD=A`o=Q8=j>?/>*\/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/rxslide_in[0] Jnet (fo=2, routed)Xh+= jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__25/I2 JXhzr ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__25/OProp_A6LUT_SLICEM_I2_O JLUT3Xhzru< kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__25_n_0 Jnet (fo=1, routed)XhD< eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/CLK Jnet (fo=674, routed)Xhm?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzr> Jclock pessimismXhA` c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/RX_BITSLIPCMD_o_regHold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhh; J arrival timeXhG?/ JXh4 JslackXhћD=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C+'SFP_GEN[26].rx_data_ngccm_reg[26][51]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu >}S-jH=a?-?FD=K4D== =j>U?/>T%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[26][51] Jnet (fo=1, routed)Xh= =] +'SFP_GEN[26].rx_data_ngccm_reg[26][51]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhd?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xhp=?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[26].rx_data_ngccm_reg[26][51]/C JFDCEXhzr> Jclock pessimismXhK4s )%SFP_GEN[26].rx_data_ngccm_reg[26][51]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhS; J arrival timeXhz?/ JXh4 JslackXhFD=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C+'SFP_GEN[26].rx_data_ngccm_reg[26][74]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu+>}Q򎿍q==|?q=?E= 9H==j>?/>?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[26][74] Jnet (fo=1, routed)Xh=] +'SFP_GEN[26].rx_data_ngccm_reg[26][74]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)XhȆ?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[26].rx_data_ngccm_reg[26][74]/C JFDCEXhzr> Jclock pessimismXh s )%SFP_GEN[26].rx_data_ngccm_reg[26][74]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhQ򎿐; J arrival timeXh?/ JXh4 JslackXhE=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C+'SFP_GEN[26].rx_data_ngccm_reg[26][67]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuz>}(Ћ( %=~?(?KG=z<9H==j>o?/>"?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_FFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[26][67] Jnet (fo=1, routed)Xh=] +'SFP_GEN[26].rx_data_ngccm_reg[26][67]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhGa?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xh:?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[26].rx_data_ngccm_reg[26][67]/C JFDCEXhzr> Jclock pessimismXhz<t )%SFP_GEN[26].rx_data_ngccm_reg[26][67]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh(Ћ; J arrival timeXhJ ?/ JXh4 JslackXhKG=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C+'SFP_GEN[26].rx_data_ngccm_reg[26][66]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu!>}bDSW=~?D??wJ=ʝ2D=G=j>o?/>#?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_GFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[26][66] Jnet (fo=1, routed)XhG=] +'SFP_GEN[26].rx_data_ngccm_reg[26][66]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhGa?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[26].rx_data_ngccm_reg[26][66]/C JFDCEXhzr> Jclock pessimismXhʝ2t )%SFP_GEN[26].rx_data_ngccm_reg[26][66]Hold_AFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhb; J arrival timeXhG?/ JXh4 JslackXh?wJ=[jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[45]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT3=1 LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsup@}A,AKk(4@K@A=А=\@N>Q>Q@ʡE??sh1?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/QProp_HFF_SLICEM_C_Q JFDCEXhzrO > QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/Q[0] Jnet (fo=22, routed)Xh(> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/I0 JXhzr _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/OProp_B5LUT_SLICEM_I0_O JLUT3Xhzf> jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/mgt_headerflag_s[0] Jnet (fo=40, routed)Xh$Y? jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24/I1 JXhzf ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24/OProp_B6LUT_SLICEL_I1_O JLUT4XhzrE= kgg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24_n_0 Jnet (fo=20, routed)Xh? fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[45]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[45]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[45]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh,A; J arrival timeXh~/ JXh4 JslackXh\@([jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT3=1 LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsup@}A,AKk(4@K@A=А=\@N>Q>Q@ʡE??sh1?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/QProp_HFF_SLICEM_C_Q JFDCEXhzrO > QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/Q[0] Jnet (fo=22, routed)Xh(> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/I0 JXhzr _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/OProp_B5LUT_SLICEM_I0_O JLUT3Xhzf> jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/mgt_headerflag_s[0] Jnet (fo=40, routed)Xh$Y? jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24/I1 JXhzf ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24/OProp_B6LUT_SLICEL_I1_O JLUT4XhzrE= kgg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24_n_0 Jnet (fo=20, routed)Xh? fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh,A; J arrival timeXh~/ JXh4 JslackXh\@([jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[52]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT3=1 LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsup@}A,AKk(4@K@A=А=\@N>Q>Q@ʡE??sh1?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/QProp_HFF_SLICEM_C_Q JFDCEXhzrO > QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/Q[0] Jnet (fo=22, routed)Xh(> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/I0 JXhzr _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/OProp_B5LUT_SLICEM_I0_O JLUT3Xhzf> jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/mgt_headerflag_s[0] Jnet (fo=40, routed)Xh$Y? jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24/I1 JXhzf ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24/OProp_B6LUT_SLICEL_I1_O JLUT4XhzrE= kgg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24_n_0 Jnet (fo=20, routed)Xh? fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[52]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[52]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[52]Setup_FFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh,A; J arrival timeXh~/ JXh4 JslackXh\@([jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT3=1 LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsup@}A,AKk(4@K@A=А=\@N>Q>Q@ʡE??sh1?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/QProp_HFF_SLICEM_C_Q JFDCEXhzrO > QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/Q[0] Jnet (fo=22, routed)Xh(> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/I0 JXhzr _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/OProp_B5LUT_SLICEM_I0_O JLUT3Xhzf> jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/mgt_headerflag_s[0] Jnet (fo=40, routed)Xh$Y? jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24/I1 JXhzf ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24/OProp_B6LUT_SLICEL_I1_O JLUT4XhzrE= kgg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[59]_i_1__24_n_0 Jnet (fo=20, routed)Xh? fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh,A; J arrival timeXh~/ JXh4 JslackXh\@(=jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT2=1 LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsul@}AV.A}?(4@}?@A=А=ʯ@`O> ?H@ʡE??sh1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/QProp_HFF_SLICEM_C_Q JFDCEXhzfO > QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/Q[0] Jnet (fo=22, routed)Xh(> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/I0 JXhzf _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/OProp_B5LUT_SLICEM_I0_O JLUT3Xhzr> jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]_0 Jnet (fo=40, routed)Xh ? `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/firstOut_i_1__24/I0 JXhzr _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/firstOut_i_1__24/OProp_C6LUT_SLICEM_I0_O JLUT2Xhzr +> eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg_0 Jnet (fo=1, routed)Xh>? eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh5^?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh`O>@ Jclock uncertaintyXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_regSetup_EFF_SLICEL_C_D JFDCEXho=/ JXh< J required timeXhV.A; J arrival timeXhz/ JXh4 JslackXhʯ@()%SFP_GEN[26].rx_data_valid_r_reg[26]/C1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[50]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu#Y@}Aa,Ap߬ھV>@p@A=А=@RX>rh>SK@ʡE?t?sh1?I ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)v )%SFP_GEN[26].rx_data_valid_r_reg[26]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>i &"SFP_GEN[26].ngCCM_gbt/p_2_in248_in Jnet (fo=2, routed)Xh$?c 51SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[83]_i_1__27/I0 JXhzr 40SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[83]_i_1__27/OProp_E6LUT_SLICEL_I0_O JLUT2Xhzr-=k '#SFP_GEN[26].ngCCM_gbt/RX_Word_rx400 Jnet (fo=48, routed)Xh?c 1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[50]/CE JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xh"#@X1Y2 (CLOCK_ROOT)[ )%SFP_GEN[26].rx_data_valid_r_reg[26]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[50]/C JFDCEXhzr> Jclock pessimismXhRX>@ Jclock uncertaintyXh{ .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[50]Setup_DFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXha,A; J arrival timeXh/ JXh4 JslackXh@0)%SFP_GEN[26].rx_data_valid_r_reg[26]/C1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[48]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuY@}Ae,Ap߬ھV>@p@A=А=ˌ@RX>rh>"K@ʡE?t?sh1?I ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)v )%SFP_GEN[26].rx_data_valid_r_reg[26]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>i &"SFP_GEN[26].ngCCM_gbt/p_2_in248_in Jnet (fo=2, routed)Xh$?c 51SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[83]_i_1__27/I0 JXhzr 40SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[83]_i_1__27/OProp_E6LUT_SLICEL_I0_O JLUT2Xhzr-=k '#SFP_GEN[26].ngCCM_gbt/RX_Word_rx400 Jnet (fo=48, routed)Xh ?c 1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[48]/CE JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xh"#@X1Y2 (CLOCK_ROOT)[ )%SFP_GEN[26].rx_data_valid_r_reg[26]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[48]/C JFDCEXhzr> Jclock pessimismXhRX>@ Jclock uncertaintyXhz .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[48]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhe,A; J arrival timeXh/ JXh4 JslackXhˌ@0)%SFP_GEN[26].rx_data_valid_r_reg[26]/C1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[70]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu.T@}A,AϾV>@@A=А=Ï@X>rh>VF@ʡE?t?sh1?/ݤ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)v )%SFP_GEN[26].rx_data_valid_r_reg[26]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>i &"SFP_GEN[26].ngCCM_gbt/p_2_in248_in Jnet (fo=2, routed)Xh$?c 51SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[83]_i_1__27/I0 JXhzr 40SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[83]_i_1__27/OProp_E6LUT_SLICEL_I0_O JLUT2Xhzr-=k '#SFP_GEN[26].ngCCM_gbt/RX_Word_rx400 Jnet (fo=48, routed)Xh+?c 1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[70]/CE JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xh"#@X1Y2 (CLOCK_ROOT)[ )%SFP_GEN[26].rx_data_valid_r_reg[26]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhi?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[70]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh{ .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[70]Setup_HFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXhÏ@0)%SFP_GEN[26].rx_data_valid_r_reg[26]/C1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[68]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuT@}A,AϾV>@@A=А=@X>rh>$F@ʡE?t?sh1?/ݤ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)v )%SFP_GEN[26].rx_data_valid_r_reg[26]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\>i &"SFP_GEN[26].ngCCM_gbt/p_2_in248_in Jnet (fo=2, routed)Xh$?c 51SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[83]_i_1__27/I0 JXhzr 40SFP_GEN[26].ngCCM_gbt/RX_Word_rx40[83]_i_1__27/OProp_E6LUT_SLICEL_I0_O JLUT2Xhzr-=k '#SFP_GEN[26].ngCCM_gbt/RX_Word_rx400 Jnet (fo=48, routed)Xh$?c 1-SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[68]/CE JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_44 Jnet (fo=674, routed)Xh"#@X1Y2 (CLOCK_ROOT)[ )%SFP_GEN[26].rx_data_valid_r_reg[26]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[26].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhi?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[68]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXhz .*SFP_GEN[26].ngCCM_gbt/RX_Word_rx40_reg[68]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXh@0jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CGCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZ(LUT2=1 LUT3=1 LUT6=2)j_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuY9d@}AK.AOS?(4@O@A=А=n@O>e;_?j,@ʡE??sh1?ʡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/QProp_HFF_SLICEM_C_Q JFDCEXhzfO > QMg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/Q[0] Jnet (fo=22, routed)Xh(> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/I0 JXhzf _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/reg0[99]_i_2__25/OProp_B5LUT_SLICEM_I0_O JLUT3Xhzr> jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]_0 Jnet (fo=40, routed)Xh? ~zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_3__1/I1 JXhzr }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_3__1/OProp_B6LUT_SLICEL_I1_O JLUT2Xhzr)> TPg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/cnt[2]1 Jnet (fo=1, routed)Xh-> ~zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_2__1/I3 JXhzr }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_2__1/OProp_F6LUT_SLICEL_I3_O JLUT6XhzrMb> {g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_2__1_n_0 Jnet (fo=1, routed)XhO= ~zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_1__1/I0 JXhzr }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i[2]_i_1__1/OProp_H6LUT_SLICEL_I0_O JLUT6XhzrE=m *&g_gbt_bank[2].gbtbank/i_gbt_bank_n_147 Jnet (fo=1, routed)Xh*\=y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)Xh~?X1Y2 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C JFDCEXhzr> Jclock pessimismXhO>@ Jclock uncertaintyXh EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]Setup_HFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXhK.A; J arrival timeXh'1/ JXh4 JslackXhn@(( !gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!)y@1y @9Ay@Iy @e|-@hq} Y= wv?$$4 rise - rise rise - rise  <+'SFP_GEN[27].rx_data_ngccm_reg[27][61]/C0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[60]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuX->}"?=%??Y=} v=5^=>U%? >9H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR)x +'SFP_GEN[27].rx_data_ngccm_reg[27][61]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[83]_0[53] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[27].ngCCM_gbt/RX_Word_rx40[60]_i_1/I0 JXhzr 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40[60]_i_1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzr<u 2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40[60]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[60]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_54 Jnet (fo=674, routed)Xh-?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[27].rx_data_ngccm_reg[27][61]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[60]/C JFDCEXhzr> Jclock pessimismXh} x .*SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[60]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh"; J arrival timeXh?/ JXh4 JslackXhY=eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/Cd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu>}şa尿XY=ʑ?a?'=ZBD=`=>l'? >EL?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/QProp_HFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut Jnet (fo=5, routed)Xh`= d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhp?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzr> Jclock pessimismXhZB b^g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_regHold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhş; J arrival timeXh?/ JXh4 JslackXh'=p0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[40]/CB>SFP_GEN[27].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuX->}mk=??[.=yk 9H==>'? >9H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR)} 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[40]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= EASFP_GEN[27].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[8] Jnet (fo=1, routed)Xh=t B>SFP_GEN[27].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xho?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> JFSFP_GEN[27].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)t B>SFP_GEN[27].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[40]/C JFDREXhzr> Jclock pessimismXhyk  @}𞿍A3=-?A?^5=C9H=\=>(1(? >CK?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[27][4] Jnet (fo=1, routed)Xh\=\ *&SFP_GEN[27].rx_data_ngccm_reg[27][4]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_54 Jnet (fo=674, routed)Xh̜?X1Y2 (CLOCK_ROOT)\ *&SFP_GEN[27].rx_data_ngccm_reg[27][4]/C JFDCEXhzr> Jclock pessimismXhCs ($SFP_GEN[27].rx_data_ngccm_reg[27][4]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh𞿐; J arrival timeXh?/ JXh4 JslackXh^5=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C+'SFP_GEN[27].rx_data_ngccm_reg[27][80]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuUb>}6$|x%=ʑ?|?Z6=DD=v=>l'? >^I?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[27][80] Jnet (fo=1, routed)Xhv=] +'SFP_GEN[27].rx_data_ngccm_reg[27][80]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_54 Jnet (fo=674, routed)Xh1?X1Y2 (CLOCK_ROOT)] +'SFP_GEN[27].rx_data_ngccm_reg[27][80]/C JFDCEXhzr> Jclock pessimismXhDt )%SFP_GEN[27].rx_data_ngccm_reg[27][80]Hold_GFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh6$; J arrival timeXh ף?/ JXh4 JslackXhZ6=2*&SFP_GEN[27].rx_data_ngccm_reg[27][2]/C/+SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[2]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu433>}ٮ\%=G?ٮ?!7=x X9=-=>ff&? >rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR)x *&SFP_GEN[27].rx_data_ngccm_reg[27][2]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD=v 3/SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[83]_0[2] Jnet (fo=1, routed)Xh=^ 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40[2]_i_1/I1 JXhzr /+SFP_GEN[27].ngCCM_gbt/RX_Word_rx40[2]_i_1/OProp_H5LUT_SLICEM_I1_O JLUT3Xhzr #=t 1-SFP_GEN[27].ngCCM_gbt/RX_Word_rx40[2]_i_1_n_0 Jnet (fo=1, routed)XhD<a /+SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[2]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_54 Jnet (fo=674, routed)Xhn?X1Y2 (CLOCK_ROOT)\ *&SFP_GEN[27].rx_data_ngccm_reg[27][2]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZd?X1Y2 (CLOCK_ROOT)a /+SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXhx x -)SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[2]Hold_HFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh!7=-sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuv>}u &e[N=n?&?3>K=+Bo=j=>:(? >WM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_BFF_SLICEL_C_Q JFDCEXhzf9H= qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)Xh㥛= jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[39]_i_2__34/I1 JXhzf ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[39]_i_2__34/OProp_D6LUT_SLICEL_I1_O JLUT5Xhzru< `\g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg00[39] Jnet (fo=1, routed)Xho< eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh.?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]/C JFDCEXhzr> Jclock pessimismXh+B c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[39]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhu ; J arrival timeXhff?/ JXh4 JslackXh3>K=eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[36]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[36]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuph>}ݰ =-??'U=&K9H=v=>(1(? >J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[36]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[36] Jnet (fo=1, routed)Xhv= eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[36]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhS?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[36]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhD?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[36]/C JFDCEXhzr> Jclock pessimismXh&K c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[36]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhݰ; J arrival timeXhZ?/ JXh4 JslackXh'U=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuş>},=&??R:X=dD%=X9=>$&? >H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__26/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__26/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xhu< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhM?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh䥛?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhdD g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhz?/ JXh4 JslackXhR:X=K.*SFP_GEN[27].ngccm_status_reg_reg[27][24]/C.*SFP_GEN[27].ngccm_status_reg_reg[27][24]/D""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsul=}#ۙ;-??vY=~jo=9H=>(1(? >J?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR){ .*SFP_GEN[27].ngccm_status_reg_reg[27][24]/QProp_FFF_SLICEL_C_Q JFDPEXhzr9H= GCSFP_GEN[27].ngCCM_gbt/SFP_GEN[27].ngccm_status_reg_reg[27][24]_0[8] Jnet (fo=2, routed)XhP=s EASFP_GEN[27].ngCCM_gbt/SFP_GEN[27].ngccm_status_reg[27][24]_i_2/I0 JXhzr D@SFP_GEN[27].ngCCM_gbt/SFP_GEN[27].ngccm_status_reg[27][24]_i_2/OProp_F6LUT_SLICEL_I0_O JLUT2Xhzru<b SFP_GEN[27].ngCCM_gbt_n_393 Jnet (fo=1, routed)XhD<` .*SFP_GEN[27].ngccm_status_reg_reg[27][24]/D JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_54 Jnet (fo=674, routed)XhS?X1Y2 (CLOCK_ROOT)` .*SFP_GEN[27].ngccm_status_reg_reg[27][24]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_54 Jnet (fo=674, routed)XhD?X1Y2 (CLOCK_ROOT)` .*SFP_GEN[27].ngccm_status_reg_reg[27][24]/C JFDPEXhzr> Jclock pessimismXh~jv ,(SFP_GEN[27].ngccm_status_reg_reg[27][24]Hold_FFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh#ۙ; J arrival timeXhף?/ JXh4 JslackXhvY=`!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuX@}A1A*r,>v.@*@A=А=|-@m~U>M?Ā@ffF?S?n2?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh2T@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh= > okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzrj= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26_n_0 Jnet (fo=1, routed)Xh= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK Jnet (fo=674, routed)XhH@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh1A; J arrival timeXhI/ JXh4 JslackXh|-@ `!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuX@}A1A*r,>v.@*@A=А=|-@m~U>M?Ā@ffF?S?n2?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh2T@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh= > okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzrj= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__26_n_0 Jnet (fo=1, routed)Xh= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__26_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK Jnet (fo=674, routed)XhH@X1Y2 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh1A; J arrival timeXhI/ JXh4 JslackXh|-@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu@}A~1A*>v.@*@A=А=3@m~U>*?I@ffF?S?n2?G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh2T@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzf"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|?> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/OProp_A6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhM? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK Jnet (fo=674, routed)XhI @X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh~1A; J arrival timeXht/ JXh4 JslackXh3@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuʱ@}A1A*>v.@*@A=А=|3@m~U>*?(@ffF?S?n2?G?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh2T@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzf"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|?> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/OProp_A6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhG? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK Jnet (fo=674, routed)XhI @X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh|3@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsut@}AI1Ax).>v.@x)@A=А=#7@m~U>*?{@ffF?S?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh2T@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzf"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|?> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/OProp_A6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh/> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK Jnet (fo=674, routed)Xhrh@X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXhI1A; J arrival timeXhX/ JXh4 JslackXh#7@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu(\@}AU1Ax).>v.@x)@A=А=s(8@m~U>*?t{@ffF?S?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh2T@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzf"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|?> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/OProp_A6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK Jnet (fo=674, routed)Xhrh@X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhU1A; J arrival timeXhK/ JXh4 JslackXhs(8@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu(\@}AU1Ax).>v.@x)@A=А=s(8@m~U>*?t{@ffF?S?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh2T@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzf"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh|?> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__27/OProp_A6LUT_SLICEM_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK Jnet (fo=674, routed)Xhrh@X1Y2 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhU1A; J arrival timeXhK/ JXh4 JslackXhs(8@ |g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu@}AY1A8)Y>v.@8)@A=А==@m~U>G?l{@ffF?S?n2?^?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh2T@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhC> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__27/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__27/OProp_F6LUT_SLICEM_I5_O JLUT6XhzrGa= `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh/> vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK Jnet (fo=674, routed)Xhx@X1Y2 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhY1A; J arrival timeXh/ JXh4 JslackXh=@ {g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsut@}A^1A8)Y>v.@8)@A=А==@m~U>G?F{@ffF?S?n2?^?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh2T@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhC> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__27/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__27/OProp_F6LUT_SLICEM_I5_O JLUT6XhzrGa= `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK Jnet (fo=674, routed)Xhx@X1Y2 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh^1A; J arrival timeXhl/ JXh4 JslackXh=@ {g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuC@}Av1A)I >v.@)@A=А=OM>@m~U>G?{@ffF?S?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh2T@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__26/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhC> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__27/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__27/OProp_F6LUT_SLICEM_I5_O JLUT6XhzrGa= `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh"> vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhv1A; J arrival timeXhT/ JXh4 JslackXhOM>@ ( !gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!)y@1y @9Ay@Iy @e0@hq}  = vv?%% rise - rise rise - rise  +'SFP_GEN[28].rx_data_ngccm_reg[28][21]/C0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]/D"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu}&>}Ɏ!ڕ=%?? =3!9H=x=>$?G>ˡE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)x +'SFP_GEN[28].rx_data_ngccm_reg[28][21]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H=v 3/SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[83]_0[9] Jnet (fo=1, routed)Xhx=b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_64 Jnet (fo=674, routed)Xh-?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[28].rx_data_ngccm_reg[28][21]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr> Jclock pessimismXh3!y .*SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[21]Hold_AFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhɎ; J arrival timeXhU?/ JXh4 JslackXh =Jg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuǡE>}h:Ad=?A?:/=!==>I "?G>H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H= jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/feedbackRegister[0] Jnet (fo=2, routed)Xh-= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__27/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__27/OProp_A6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh&?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh̜?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXh! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhh:; J arrival timeXh9?/ JXh4 JslackXh:/=esog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[20]/D"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuN>}b-e;=V?e;?x@=#![="=>S?G>yF?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0] Jnet (fo=29, routed)Xhj= jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[20]_i_1__33/I2 JXhzr ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[20]_i_1__33/OProp_B6LUT_SLICEM_I2_O JLUT5Xhzrj<= `\g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg00[20] Jnet (fo=1, routed)Xhu< eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[20]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~?X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƛ?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[20]/C JFDCEXhzr> Jclock pessimismXh#! c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[20]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhb-; J arrival timeXh'1?/ JXh4 JslackXhx@=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuMb>}Ri~= ?R?C=ӜN=@=>M"?G>TE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__27/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__27/OProp_F6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhC?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhӜN g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh-?/ JXh4 JslackXhC=F+'SFP_GEN[28].rx_data_ngccm_reg[28][37]/C0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]/D"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuX->}ޟk=Nb??KD=d! ף=E=>"?G>MB?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)x +'SFP_GEN[28].rx_data_ngccm_reg[28][37]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H=w 40g_gbt_bank[2].gbtbank/RX_Word_rx40_reg[78]_0[13] Jnet (fo=1, routed)Xh=b 40g_gbt_bank[2].gbtbank/RX_Word_rx40[36]_i_1__5/I0 JXhzr 3/g_gbt_bank[2].gbtbank/RX_Word_rx40[36]_i_1__5/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr<w 40SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[83]_0[22] Jnet (fo=1, routed)Xho<b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_64 Jnet (fo=674, routed)Xh8?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[28].rx_data_ngccm_reg[28][37]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXhd!x .*SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhޟ; J arrival timeXh?/ JXh4 JslackXhKD=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuxh>}Ri~= ?R?FG=ӜN=D=>M"?G>TE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__27/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__27/OProp_G6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhC?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXhӜN g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhM?/ JXh4 JslackXhFG=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsueB>}ﬡR+=;ߏ?R?-P=+!=E=>!?G>TE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__27/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__27/OProp_B6LUT_SLICEL_I2_O JLUT3XhzrY= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xhu< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhC?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh+! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhﬡ; J arrival timeXh(1?/ JXh4 JslackXh-P=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[28].rx_data_ngccm_reg[28][31]/D"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsut>}7wY=rh?w?bS=ЎMD==>/$?G>G?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_CFF_SLICEM_C_Q JFDREXhzrD=V rx_data[28][31] Jnet (fo=1, routed)Xh=] +'SFP_GEN[28].rx_data_ngccm_reg[28][31]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_64 Jnet (fo=674, routed)XhI?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[28].rx_data_ngccm_reg[28][31]/C JFDCEXhzr> Jclock pessimismXhЎMt )%SFP_GEN[28].rx_data_ngccm_reg[28][31]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh7; J arrival timeXh ף?/ JXh4 JslackXhbS=s0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]/CB>SFP_GEN[28].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/D"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuϡE>}Rc>=?R?5T=ɵ!9H=t>>G!?G>TE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR)} 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= EASFP_GEN[28].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[6] Jnet (fo=1, routed)Xht>t B>SFP_GEN[28].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[28].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhĀ?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[28].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> JFSFP_GEN[28].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X1Y3 (CLOCK_ROOT)t B>SFP_GEN[28].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C JFDREXhzr> Jclock pessimismXhɵ! @}=wh=A?w?p:X=!9H=,>>]"?G>G?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[28][22] Jnet (fo=1, routed)Xh,>] +'SFP_GEN[28].rx_data_ngccm_reg[28][22]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhsh?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_64 Jnet (fo=674, routed)XhI?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[28].rx_data_ngccm_reg[28][22]/C JFDCEXhzr> Jclock pessimismXh!t )%SFP_GEN[28].rx_data_ngccm_reg[28][22]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh=; J arrival timeXhX?/ JXh4 JslackXhp:X=g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuMb@}An0A<'?=|/@<'@A=А=0@zW>?H@I??}?5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I3 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhO> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrA`> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhv>? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhzW>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhn0A; J arrival timeXhb / JXh4 JslackXh0@ }!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuR@}AH0A'"=|/@'@A=А=+&@zW>S?T@I??}?5?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I3 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhT> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27_n_0 Jnet (fo=1, routed)Xh = okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27_n_0 Jnet (fo=2, routed)Xhr> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh= @X1Y3 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhzW>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhH0A; J arrival timeXhd;/ JXh4 JslackXh+&@ }!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuR@}AH0A'"=|/@'@A=А=+&@zW>S?T@I??}?5?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I3 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhT> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__27_n_0 Jnet (fo=1, routed)Xh = okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__27_n_0 Jnet (fo=2, routed)Xhr> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh= @X1Y3 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhzW>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhH0A; J arrival timeXhd;/ JXh4 JslackXh+&@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu@}An0Ab(td=|/@b(@A=А=^#*@zW>?@I??}?5?A`?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I3 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhO> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrA`> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhZ? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhzW>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXhn0A; J arrival timeXhn/ JXh4 JslackXh^#*@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[28].rx_data_ngccm_reg[28][51]/CE"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuj@}A0Al'cN(|7@l'@A=А=l*@V>xi>p@I??}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhIT@ wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/SFP_GEN[28].rx_data_ngccm[28][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/SFP_GEN[28].rx_data_ngccm[28][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrE=Y rx_data_ngccm[28] Jnet (fo=76, routed)Xh/?^ ,(SFP_GEN[28].rx_data_ngccm_reg[28][51]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_64 Jnet (fo=674, routed)Xh)\@X1Y3 (CLOCK_ROOT)] +'SFP_GEN[28].rx_data_ngccm_reg[28][51]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXhu )%SFP_GEN[28].rx_data_ngccm_reg[28][51]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXhp=/ JXh4 JslackXhl*@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu@}A1Ab(td=|/@b(@A=А= *@zW>?|@I??}?5?A`?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I3 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhO> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrA`> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhS? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhzW>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh5^/ JXh4 JslackXh *@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuQ@}A0Al'=|/@l'@A=А=z}.@zW>?L7@I??}?5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I3 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhO> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrA`> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhM> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh)\@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhzW>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXhd;/ JXh4 JslackXhz}.@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuA@}A1AA(u=|/@A(@A=А= @4@zW>?@I??}?5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I3 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh ף> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__28/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__28/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh/? vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1@X1Y3 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhzW>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_AFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh @4@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuA@}A1AA(u=|/@A(@A=А= @4@zW>?@I??}?5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I3 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh ף> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__28/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__28/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh/? vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1@X1Y3 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhzW>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh @4@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu @}A1A (p=|/@ (@A=А=`4@zW>?}?}@I??}?5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/I3 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__27/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhO> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__28/OProp_E6LUT_SLICEL_I3_O JLUT5XhzrA`> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhԸ> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhzW>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh`4@ ( !gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!)y@1y @9Ay@Iy @eyN@hq} Ң= uv?&&8 rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu&1>}9ACL=rh?A?Ң=#T=j=%>$?>)1H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__28/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__28/OProp_H6LUT_SLICEM_I2_O JLUT3Xhzro= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh̜?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh# g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_HFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh9; J arrival timeXhO?/ JXh4 JslackXhҢ=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu{?5>}9ACL=rh?A?&#=#E=X9=%>$?>)1H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__28/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__28/OProp_H5LUT_SLICEM_I0_O JLUT3Xhzr #= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh̜?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr> Jclock pessimismXh# g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]Hold_HFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh9; J arrival timeXhb?/ JXh4 JslackXh&#=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuX9>})N=ף??c#=5#=-=%>o#?>G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xhrh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__28/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__28/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhʁ?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhD?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXh5# g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhΧ?/ JXh4 JslackXhc#=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuv>>})N=ף??7=5#==%>o#?>G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in Jnet (fo=2, routed)Xhrh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__28/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__28/OProp_C5LUT_SLICEM_I0_O JLUT3XhzrGa= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)XhX94< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhʁ?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhD?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr> Jclock pessimismXh5# g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]Hold_CFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhr?/ JXh4 JslackXh7=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C+'SFP_GEN[29].rx_data_ngccm_reg[29][27]/D"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu">}!lj=\?!?Y;=cFD=S=%>y&?>WM?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_EFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[29][27] Jnet (fo=1, routed)XhS=] +'SFP_GEN[29].rx_data_ngccm_reg[29][27]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_74 Jnet (fo=674, routed)Xhd;?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[29].rx_data_ngccm_reg[29][27]/C JFDCEXhzr> Jclock pessimismXhcFt )%SFP_GEN[29].rx_data_ngccm_reg[29][27]Hold_GFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhy?/ JXh4 JslackXhY;=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuv>>}: j=rh??Ʀ?=#[=5^=%>$?>;H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] Jnet (fo=1, routed)Xh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__28/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__28/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrj<= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[0] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh# g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh:; J arrival timeXhK7?/ JXh4 JslackXhƦ?=pmig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[1]/Cmig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu>}Vy;B=v?V?F=-Do=X9=%>S?>A?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[1]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= XTg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/timer[1] Jnet (fo=6, routed)Xht= rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__29/I5 JXhzr qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__29/OProp_C6LUT_SLICEL_I5_O JLUT6Xhzru< sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__29_n_0 Jnet (fo=1, routed)Xho< mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X1Y3 (CLOCK_ROOT) mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[1]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) mig_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzr> Jclock pessimismXh-D kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].rxBitSlipControl/clkSlipProcess.timer_reg[5]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhF=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuj<>}ˡڡ=??ҔH=-#[=E=%>"?>VE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__28/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__28/OProp_B6LUT_SLICEM_I2_O JLUT3Xhzrj<= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xhu< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh䥛?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh-# g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhˡ; J arrival timeXhc?/ JXh4 JslackXhҔH=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[29].rx_data_ngccm_reg[29][39]/D"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu >}jA&=-?A?J=GD=:=%>$&?>)1H?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_GFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[29][39] Jnet (fo=1, routed)Xh:=] +'SFP_GEN[29].rx_data_ngccm_reg[29][39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_74 Jnet (fo=674, routed)Xh̜?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[29].rx_data_ngccm_reg[29][39]/C JFDCEXhzr> Jclock pessimismXhGs )%SFP_GEN[29].rx_data_ngccm_reg[29][39]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhj; J arrival timeXh0ݤ?/ JXh4 JslackXhJ=wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/Cwsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu=`=}'1󭿭֣;Nb??[P=lgo=D=%>]"?>C?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/QProp_BFF_SLICEM_C_Q JFDREXhzr9H= zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[2] Jnet (fo=4, routed)Xht= |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__29/I2 JXhzr {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__29/OProp_A6LUT_SLICEM_I2_O JLUT6Xhzru< }yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__29_n_0 Jnet (fo=1, routed)XhD< wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh8?X1Y3 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~?X1Y3 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhlg uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh'1; J arrival timeXhR?/ JXh4 JslackXh[P=!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuA@}A~1A)>)\/@)@A=А=yN@?Y>?5?shi@CK?!?5?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh.@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28_n_0 Jnet (fo=1, routed)Xh"> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^@X1Y3 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh?Y>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[0]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh~1A; J arrival timeXh/ JXh4 JslackXhyN@ !g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuA@}A~1A)>)\/@)@A=А=yN@?Y>?5?shi@CK?!?5?t?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh.@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28/OProp_C6LUT_SLICEM_I2_O JLUT4XhzrQ= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_7__28_n_0 Jnet (fo=1, routed)Xh"> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state[1]_i_1__28_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^@X1Y3 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh?Y>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh~1A; J arrival timeXh/ JXh4 JslackXhyN@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu@}An1A)t=)\/@)@A=А=bT@?Y>?c@CK?!?5?%1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh.@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I1 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzf> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhGa> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzrlg> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhZd? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh7@X1Y3 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh?Y>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhn1A; J arrival timeXh/ JXh4 JslackXhbT@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu@}An1A)t=)\/@)@A=А=bT@?Y>?c@CK?!?5?%1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh.@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I1 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzf> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhGa> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzrlg> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhZd? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh7@X1Y3 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh?Y>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhn1A; J arrival timeXh/ JXh4 JslackXhbT@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsua@}Ar1A)t=)\/@)@A=А=T@?Y>?Sc@CK?!?5?%1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh.@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I1 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzf> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhGa> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzrlg> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh7@X1Y3 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh?Y>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[0]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhr1A; J arrival timeXhv/ JXh4 JslackXhT@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsua@}Ar1A)t=)\/@)@A=А=T@?Y>?Sc@CK?!?5?%1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh.@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I1 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzf> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhGa> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzrlg> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh7@X1Y3 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh?Y>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhr1A; J arrival timeXhv/ JXh4 JslackXhT@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsua@}Ar1A)t=)\/@)@A=А=T@?Y>?Sc@CK?!?5?%1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzfO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh.@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I1 JXhzf plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzf> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhGa> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__29/OProp_F6LUT_SLICEM_I0_O JLUT6Xhzrlg> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh7@X1Y3 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh?Y>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_AFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhr1A; J arrival timeXhv/ JXh4 JslackXhT@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuE@}An1A)t=)\/@)@A=А=Y@?Y>̼?$^@CK?!?5?%1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh.@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh(\> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzrgff> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh+? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh7@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh?Y>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhn1A; J arrival timeXh/ JXh4 JslackXhY@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuE@}An1A)t=)\/@)@A=А=Y@?Y>̼?$^@CK?!?5?%1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh.@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh(\> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzrgff> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh+? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh7@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXh?Y>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhn1A; J arrival timeXh/ JXh4 JslackXhY@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu-@}Ar1A)t=)\/@)@A=А=GZ@?Y>̼?]@CK?!?5?%1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh.@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__28/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh(\> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__29/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzrgff> ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhff? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh(@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh7@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh?Y>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhr1A; J arrival timeXh#/ JXh4 JslackXhGZ@ ( !gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!)y@1y @9Ay@Iy @eb@hq} $-= wv?'' rise - rise rise - rise  "eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[26]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[26]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu(>}čL7b=(|?L7?$-=x9H=i=j>A?/>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[26]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[26] Jnet (fo=1, routed)Xhi= eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[26]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv^?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[26]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh…?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[26]/C JFDCEXhzr> Jclock pessimismXhx c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[26]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhč; J arrival timeXh43?/ JXh4 JslackXh$-="eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[11]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[11]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsudI>}ƑV\= |?V?8=6D=u>j>?/>$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[11]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[11] Jnet (fo=1, routed)Xhu> eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[11]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[11]/C JFDCEXhzr> Jclock pessimismXh6 c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[11]Hold_AFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhƑ; J arrival timeXhQ?/ JXh4 JslackXh8=q0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[32]/CB>SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuMb>}nƛ !=v~?ƛ?;=<9H=j=j>\?/>I "?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR)} 0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[32]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= EASFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[4] Jnet (fo=1, routed)Xhj=t B>SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[30].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh`?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> JFSFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X1Y3 (CLOCK_ROOT)t B>SFP_GEN[30].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[32]/C JFDREXhzr> Jclock pessimismXh< @}򘍿VY,=%?V?ay;=@?=L=j>$?/>+'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__29/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__29/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhZd?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhH?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh@? g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh򘍿; J arrival timeXht?/ JXh4 JslackXhay;=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C+'SFP_GEN[30].rx_data_ngccm_reg[30][37]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsun>}j%=|?j?S?=v<D=\=j>?/>S#?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/QProp_GFF_SLICEM_C_Q JFDREXhzrD=V rx_data[30][37] Jnet (fo=1, routed)Xh\=] +'SFP_GEN[30].rx_data_ngccm_reg[30][37]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][37]/C JFDCEXhzr> Jclock pessimismXhv<t )%SFP_GEN[30].rx_data_ngccm_reg[30][37]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhJ ?/ JXh4 JslackXhS?=D+'SFP_GEN[30].rx_data_ngccm_reg[30][72]/C0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[72]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu|?>}?5f=%??5?p?=E=v=j>$?/>y&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR)x +'SFP_GEN[30].rx_data_ngccm_reg[30][72]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H=w 40g_gbt_bank[2].gbtbank/RX_Word_rx40_reg[78]_1[48] Jnet (fo=1, routed)Xh-=b 40g_gbt_bank[2].gbtbank/RX_Word_rx40[72]_i_1__6/I1 JXhzr 3/g_gbt_bank[2].gbtbank/RX_Word_rx40[72]_i_1__6/OProp_C6LUT_SLICEL_I1_O JLUT3XhzrQ8=w 40SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[83]_0[40] Jnet (fo=1, routed)Xho<b 0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[72]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)XhZd?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][72]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[30].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)b 0,SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[72]/C JFDCEXhzr> Jclock pessimismXhEx .*SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[72]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhp?=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C+'SFP_GEN[30].rx_data_ngccm_reg[30][77]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuϡE>}VJ=Nb?V?v?= PD=z>j>/?/>+'?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[30][77] Jnet (fo=1, routed)Xhz>] +'SFP_GEN[30].rx_data_ngccm_reg[30][77]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhoc?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)XhH?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][77]/C JFDCEXhzr> Jclock pessimismXh Pt )%SFP_GEN[30].rx_data_ngccm_reg[30][77]Hold_CFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhv?=K.*SFP_GEN[30].ngccm_status_reg_reg[30][24]/C.*SFP_GEN[30].ngccm_status_reg_reg[30][24]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsui;=}<֣߯;ʑ?<߯?D=!ko=Q8=j>'?/>r=J?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR){ .*SFP_GEN[30].ngccm_status_reg_reg[30][24]/QProp_AFF_SLICEM_C_Q JFDPEXhzr9H= GCSFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg_reg[30][24]_0[8] Jnet (fo=2, routed)Xh+=s EASFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_2/I0 JXhzr D@SFP_GEN[30].ngCCM_gbt/SFP_GEN[30].ngccm_status_reg[30][24]_i_2/OProp_A6LUT_SLICEM_I0_O JLUT2Xhzru<b SFP_GEN[30].ngCCM_gbt_n_392 Jnet (fo=1, routed)XhD<` .*SFP_GEN[30].ngccm_status_reg_reg[30][24]/D JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)` .*SFP_GEN[30].ngccm_status_reg_reg[30][24]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xhj?X1Y3 (CLOCK_ROOT)` .*SFP_GEN[30].ngccm_status_reg_reg[30][24]/C JFDPEXhzr> Jclock pessimismXh!kv ,(SFP_GEN[30].ngccm_status_reg_reg[30][24]Hold_AFF_SLICEM_C_D JFDPEXhA`e=/ JXh< J required timeXh; J arrival timeXhw?/ JXh4 JslackXhD=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C+'SFP_GEN[30].rx_data_ngccm_reg[30][74]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu">}F󝿭`=Nb??E=S4D=S=j>/?/>gf&?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/QProp_HFF_SLICEL_C_Q JFDREXhzrD=V rx_data[30][74] Jnet (fo=1, routed)XhS=] +'SFP_GEN[30].rx_data_ngccm_reg[30][74]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhoc?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh~?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][74]/C JFDCEXhzr> Jclock pessimismXhS4s )%SFP_GEN[30].rx_data_ngccm_reg[30][74]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhF; J arrival timeXhk?/ JXh4 JslackXhE=4g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu 0>}m盿2=a?m?H=^wʡ=v=j>U?/>M"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/O84[0] Jnet (fo=2, routed)Xh-= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__29/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__29/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhd?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhr?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXh^w g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhy?/ JXh4 JslackXhH=g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][67]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsux~@}A8.A )MV6@ @A=А=b@pZ>xi>Qp@ʡE?t?sh1?ٮ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhn? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrE=Y rx_data_ngccm[30] Jnet (fo=76, routed)Xh@^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][67]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][67]/C JFDCEXhzr> Jclock pessimismXhpZ>@ Jclock uncertaintyXhu )%SFP_GEN[30].rx_data_ngccm_reg[30][67]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh8.A; J arrival timeXh/ JXh4 JslackXhb@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][73]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuw@}A,AKV6@K@A=А=A@bhN>xi>i@ʡE?t?sh1?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhn? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrE=Y rx_data_ngccm[30] Jnet (fo=76, routed)Xhw?^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][73]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xhv?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][73]/C JFDCEXhzr> Jclock pessimismXhbhN>@ Jclock uncertaintyXhv )%SFP_GEN[30].rx_data_ngccm_reg[30][73]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh,A; J arrival timeXh / JXh4 JslackXhA@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][64]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu|w@}A,Ad;V6@d;@A=А=dR@kN>xi>`h@ʡE?t?sh1?ʡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhn? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrE=Y rx_data_ngccm[30] Jnet (fo=76, routed)Xh(\?^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][64]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)XhV?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][64]/C JFDCEXhzr> Jclock pessimismXhkN>@ Jclock uncertaintyXhv )%SFP_GEN[30].rx_data_ngccm_reg[30][64]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh,A; J arrival timeXhy/ JXh4 JslackXhdR@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][72]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsulw@}AG,AKV6@K@A=А=F{@bhN>xi>h@ʡE?t?sh1?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhn? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrE=Y rx_data_ngccm[30] Jnet (fo=76, routed)Xhe;?^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][72]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xhv?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][72]/C JFDCEXhzr> Jclock pessimismXhbhN>@ Jclock uncertaintyXhu )%SFP_GEN[30].rx_data_ngccm_reg[30][72]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhG,A; J arrival timeXhH/ JXh4 JslackXhF{@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][74]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsulw@}AG,AKV6@K@A=А=F{@bhN>xi>h@ʡE?t?sh1?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhn? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrE=Y rx_data_ngccm[30] Jnet (fo=76, routed)Xhe;?^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][74]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xhv?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][74]/C JFDCEXhzr> Jclock pessimismXhbhN>@ Jclock uncertaintyXhu )%SFP_GEN[30].rx_data_ngccm_reg[30][74]Setup_FFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhG,A; J arrival timeXhH/ JXh4 JslackXhF{@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][56]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuKw@}A9,Ad;V6@d;@A=А=@kN>xi>:h@ʡE?t?sh1?ʡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhn? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrE=Y rx_data_ngccm[30] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][56]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)XhV?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][56]/C JFDCEXhzr> Jclock pessimismXhkN>@ Jclock uncertaintyXhu )%SFP_GEN[30].rx_data_ngccm_reg[30][56]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh9,A; J arrival timeXh/ JXh4 JslackXh@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][68]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu(t@}AU,A(\V6@(\@A=А=,%@eN>xi>ie@ʡE?t?sh1?S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhn? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrE=Y rx_data_ngccm[30] Jnet (fo=76, routed)Xh9?^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][68]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][68]/C JFDCEXhzr> Jclock pessimismXheN>@ Jclock uncertaintyXhv )%SFP_GEN[30].rx_data_ngccm_reg[30][68]Setup_AFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhU,A; J arrival timeXh}?/ JXh4 JslackXh,%@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][70]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu(t@}AU,A(\V6@(\@A=А=,%@eN>xi>ie@ʡE?t?sh1?S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhn? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrE=Y rx_data_ngccm[30] Jnet (fo=76, routed)Xh9?^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][70]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][70]/C JFDCEXhzr> Jclock pessimismXheN>@ Jclock uncertaintyXhv )%SFP_GEN[30].rx_data_ngccm_reg[30][70]Setup_BFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhU,A; J arrival timeXh}?/ JXh4 JslackXh,%@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][66]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsus@}Al,A(\V6@(\@A=А=E@eN>xi>B`e@ʡE?t?sh1?S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhn? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrE=Y rx_data_ngccm[30] Jnet (fo=76, routed)XhQ?^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][66]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][66]/C JFDCEXhzr> Jclock pessimismXheN>@ Jclock uncertaintyXhu )%SFP_GEN[30].rx_data_ngccm_reg[30][66]Setup_AFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhl,A; J arrival timeXh&/ JXh4 JslackXhE@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[30].rx_data_ngccm_reg[30][69]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsus@}Al,A(\V6@(\@A=А=E@eN>xi>B`e@ʡE?t?sh1?S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhn? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/SFP_GEN[30].rx_data_ngccm[30][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6XhzrE=Y rx_data_ngccm[30] Jnet (fo=76, routed)XhQ?^ ,(SFP_GEN[30].rx_data_ngccm_reg[30][69]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[2].gbtbank_n_84 Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[30].rx_data_ngccm_reg[30][69]/C JFDCEXhzr> Jclock pessimismXheN>@ Jclock uncertaintyXhu )%SFP_GEN[30].rx_data_ngccm_reg[30][69]Setup_BFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXhl,A; J arrival timeXh&/ JXh4 JslackXhE@L( !gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!)y@1y @9Ay@Iy @e-2@hq} "= wv?((  rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C+'SFP_GEN[31].rx_data_ngccm_reg[31][74]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu6$>}󭿭=8??"= D=l=>z&? >F?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/QProp_HFF_SLICEM_C_Q JFDREXhzrD=V rx_data[31][74] Jnet (fo=1, routed)Xhl=] +'SFP_GEN[31].rx_data_ngccm_reg[31][74]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh!?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_94 Jnet (fo=674, routed)Xh~?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[31].rx_data_ngccm_reg[31][74]/C JFDCEXhzr> Jclock pessimismXh s )%SFP_GEN[31].rx_data_ngccm_reg[31][74]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh$?/ JXh4 JslackXh"=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsut>}!$shoi5=M?sh?K 3=zK=L=>r(? >hM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__30/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__30/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[16] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xht?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXhzK g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh!$; J arrival timeXhk?/ JXh4 JslackXhK 3=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsut>}`尿oi5=?`?K 3=|tJ=L=>'? >CL?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__30/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__30/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xho?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh|tJ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhZ?/ JXh4 JslackXhK 3=1*&SFP_GEN[31].rx_data_ngccm_reg[31][7]/C/+SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[6]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuX94>}z)\C=?)\?">=c X9=X9=>'? >xI?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR)w *&SFP_GEN[31].rx_data_ngccm_reg[31][7]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD=v 3/SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[83]_0[7] Jnet (fo=1, routed)Xh㥛=^ 0,SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[6]_i_1/I0 JXhzr /+SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[6]_i_1/OProp_D5LUT_SLICEM_I0_O JLUT3Xhzr #=t 1-SFP_GEN[31].ngCCM_gbt/RX_Word_rx40[6]_i_1_n_0 Jnet (fo=1, routed)XhD<a /+SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[6]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[2].gbtbank_n_94 Jnet (fo=674, routed)Xho?X1Y3 (CLOCK_ROOT)\ *&SFP_GEN[31].rx_data_ngccm_reg[31][7]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[31].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhm?X1Y3 (CLOCK_ROOT)a /+SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[6]/C JFDCEXhzr> Jclock pessimismXhc x -)SFP_GEN[31].ngCCM_gbt/RX_Word_rx40_reg[6]Hold_DFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhz; J arrival timeXhr?/ JXh4 JslackXh">=Ig_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsui;=}A֣;-?A?D=ko=Q8=>(1(? >CK?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/error_detected_msb Jnet (fo=4, routed)Xh+= xtg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__61/I5 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__61/OProp_A6LUT_SLICEM_I5_O JLUT6Xhzru< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK Jnet (fo=674, routed)Xh̜?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C JFDREXhzr> Jclock pessimismXhk g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_regHold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh ?/ JXh4 JslackXhD=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuw>}!$shoi5=M?sh?-G=zK=Q8=>r(? >hM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__30/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__30/OProp_D5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[18] Jnet (fo=1, routed)XhX94< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xht?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXhzK g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh!$; J arrival timeXhB`?/ JXh4 JslackXh-G=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuw>}`尿oi5=?`?-G=|tJ=Q8=>'? >CL?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)XhC = g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__30/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__30/OProp_D5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)XhX94< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xho?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr> Jclock pessimismXh|tJ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh-G=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C+'SFP_GEN[31].rx_data_ngccm_reg[31][47]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuz>}Ӟ G'=\? ?\I=NBD==>(? > K?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[31][47] Jnet (fo=1, routed)Xh=] +'SFP_GEN[31].rx_data_ngccm_reg[31][47]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_94 Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[31].rx_data_ngccm_reg[31][47]/C JFDCEXhzr> Jclock pessimismXhNBt )%SFP_GEN[31].rx_data_ngccm_reg[31][47]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhӞ; J arrival timeXh?/ JXh4 JslackXh\I=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C+'SFP_GEN[31].rx_data_ngccm_reg[31][63]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsut>}睿e;S"=ʑ?e;?D8J=[B9H=[=>l'? >L7I?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[31][63] Jnet (fo=1, routed)Xh[=] +'SFP_GEN[31].rx_data_ngccm_reg[31][63]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[2].gbtbank_n_94 Jnet (fo=674, routed)Xhƛ?X1Y3 (CLOCK_ROOT)] +'SFP_GEN[31].rx_data_ngccm_reg[31][63]/C JFDCEXhzr> Jclock pessimismXh[Bt )%SFP_GEN[31].rx_data_ngccm_reg[31][63]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh睿; J arrival timeXhX9?/ JXh4 JslackXhD8J=<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/C<8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/D""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu>}pNbK7=-?Nb?M=C%=X9=>(1(? > K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD= rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gbtBank_Clk_gen[7].cnt_reg[7][7]_0[4] Jnet (fo=9, routed)Xh㥛= sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gbtBank_Clk_gen[7].cnt[7][5]_i_1__1/I4 JXhzr rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gbtBank_Clk_gen[7].cnt[7][5]_i_1__1/OProp_A6LUT_SLICEL_I4_O JLUT6Xhzru<m *&g_gbt_bank[2].gbtbank/i_gbt_bank_n_326 Jnet (fo=1, routed)XhD<n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 Jnet (fo=674, routed)XhS?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/C JFDCEXhzr> Jclock pessimismXhC :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhp; J arrival timeXh?/ JXh4 JslackXhM= {!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu@}A1A!*>v.@!*@A=А=-2@m~U>??5@ffF?S?n2?2?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhI@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzrj= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30_n_0 Jnet (fo=1, routed)Xh= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30_n_0 Jnet (fo=2, routed)Xh-? kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh-2@ {!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuE@}A1A*: >v.@*@A=А=3@m~U>?ҁ@ffF?S?n2?I?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhI@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzrj= plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_7__30_n_0 Jnet (fo=1, routed)Xh= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state[1]_i_1__30_n_0 Jnet (fo=2, routed)Xh? kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/FSM_sequential_state_reg[0]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh3@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsun@}A~1AM*>v.@M*@A=А=gR@m~U>{?m@ffF?S?n2?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhI@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhƋ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhq=@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh~1A; J arrival timeXh/ JXh4 JslackXhgR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsun@}A~1AM*>v.@M*@A=А=gR@m~U>{?m@ffF?S?n2?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhI@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhƋ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhq=@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh~1A; J arrival timeXh/ JXh4 JslackXhgR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsun@}A~1AM*>v.@M*@A=А=gR@m~U>{?m@ffF?S?n2?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhI@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhƋ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhq=@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_GFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh~1A; J arrival timeXh/ JXh4 JslackXhgR@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuV@}A"1AM*>v.@M*@A=А= S@m~U>{?ˡm@ffF?S?n2?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhI@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhƋ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhu> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhq=@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh"1A; J arrival timeXhh/ JXh4 JslackXh S@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuV@}A"1AM*>v.@M*@A=А= S@m~U>{?ˡm@ffF?S?n2?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhI@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhƋ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhu> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhq=@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh"1A; J arrival timeXhh/ JXh4 JslackXh S@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuV@}A"1AM*>v.@M*@A=А= S@m~U>{?ˡm@ffF?S?n2?C?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhI@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhƋ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhu> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhq=@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_GFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh"1A; J arrival timeXhh/ JXh4 JslackXh S@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu-@}Ak1An*W>v.@n*@A=А=T@m~U>{?Zl@ffF?S?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhI@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhƋ> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__31/OProp_C6LUT_SLICEM_I3_O JLUT5XhzrQ= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhV> tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^@X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhk1A; J arrival timeXh/ JXh4 JslackXhT@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu}@}A1AZd+W$>v.@Zd+@A=А=OT@m~U>?o@ffF?S?n2?p?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhI@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/I1 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__30/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ= zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__31/I5 JXhzr yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__31/OProp_E6LUT_SLICEL_I5_O JLUT6XhzrL= `\g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)XhS? vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhS@X1Y3 (CLOCK_ROOT) uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXhO/ JXh4 JslackXhOT@ ( !gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!)y@1y @9Ay@Iy @ew@hq} = uv?)) rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu>}$|c"l=-?|?=\v/o= =H>L7 ?> +?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__31/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__31/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzru< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhf?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh1?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh\v/ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh$; J arrival timeXhB`?/ JXh4 JslackXh=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C+'SFP_GEN[32].rx_data_ngccm_reg[32][52]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuX->}f񢿭.=Ȇ??3{ =09H==H>n?>1?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[32][52] Jnet (fo=1, routed)Xh=] +'SFP_GEN[32].rx_data_ngccm_reg[32][52]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)Xh|?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[32].rx_data_ngccm_reg[32][52]/C JFDCEXhzr> Jclock pessimismXh0s )%SFP_GEN[32].rx_data_ngccm_reg[32][52]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhf; J arrival timeXhj?/ JXh4 JslackXh3{ =g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C+'SFP_GEN[32].rx_data_ngccm_reg[32][56]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu&1>}f񢿭.=Ȇ??0=0D=>H>n?>1?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[32][56] Jnet (fo=1, routed)Xh>] +'SFP_GEN[32].rx_data_ngccm_reg[32][56]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)Xh|?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[32].rx_data_ngccm_reg[32][56]/C JFDCEXhzr> Jclock pessimismXh0s )%SFP_GEN[32].rx_data_ngccm_reg[32][56]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhf; J arrival timeXh?/ JXh4 JslackXh0=_[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress_reg[1]/C_[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_reg/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuQ8>}[d񢿭J`=U??&1=-=v=H>أ?>1?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress_reg[1]/QProp_DFF_SLICEM_C_Q JFDCEXhzf9H= YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress[1] Jnet (fo=8, routed)Xh= d`g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_i_1__32/I1 JXhzf c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_i_1__32/OProp_C5LUT_SLICEL_I1_O JLUT3Xhzr= eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_i_1__32_n_0 Jnet (fo=1, routed)XhX94< _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh{n?X1Y4 (CLOCK_ROOT) _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/psAddress_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh|?X1Y4 (CLOCK_ROOT) _[g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_reg/C JFDCEXhzr> Jclock pessimismXh ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/headerFlag_s_regHold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh[d; J arrival timeXh?/ JXh4 JslackXh&1=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C+'SFP_GEN[32].rx_data_ngccm_reg[32][46]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsut>}⎿)\ %=]?)\?kC=$=D==H> ?>*?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_HFF_SLICEM_C_Q JFDREXhzrD=V rx_data[32][46] Jnet (fo=1, routed)Xh=] +'SFP_GEN[32].rx_data_ngccm_reg[32][46]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhlg?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)Xhm?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[32].rx_data_ngccm_reg[32][46]/C JFDCEXhzr> Jclock pessimismXh$=t )%SFP_GEN[32].rx_data_ngccm_reg[32][46]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh⎿; J arrival timeXh?/ JXh4 JslackXhkC=csog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuX94>}1휿#=ʁ??D=t7%=l=H>r?>T%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/QProp_CFF_SLICEM_C_Q JFDCEXhzfD= qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1] Jnet (fo=28, routed)Xh= jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0[39]_i_2__29/I0 JXhzf ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0[39]_i_2__29/OProp_C6LUT_SLICEM_I0_O JLUT5Xhzru< `\g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg00[39] Jnet (fo=1, routed)Xho< eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhTe?X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]/C JFDCEXhzr> Jclock pessimismXht7 c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[39]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh1; J arrival timeXhQ?/ JXh4 JslackXhD=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuv>>}E=!??%G==j=H>q= ?>)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)Xh ף= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__31/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__31/OProp_F6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhg?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhE; J arrival timeXh~?/ JXh4 JslackXh%G=i0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[22]/CGCSFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuz>},ƛ#=a?ƛ?H=&.9H==H>?>#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR)} 0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[22]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H=p -)SFP_GEN[32].ngCCM_gbt/gbt_rx_checker/Q[6] Jnet (fo=5, routed)Xh=y GCSFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhd?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[22]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[32].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X1Y4 (CLOCK_ROOT)y GCSFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]/C JFDREXhzr> Jclock pessimismXh&. EASFP_GEN[32].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[6]Hold_HFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh,; J arrival timeXht?/ JXh4 JslackXhH=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu|?>}E=!??n>K==v=H>q= ?>)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)Xhʡ= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__31/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[10]_i_1__31/OProp_G6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[10] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhg?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[10]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhE; J arrival timeXh?/ JXh4 JslackXhn>K=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuv>>}Vb=M?V?fO="=j=H>x ?>9(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_3_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__31/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__31/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzrj<= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[0] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhyf?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhH?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh" g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhfO=g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[32].rx_data_ngccm_reg[32][53]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsux@}A/,A+Rw7@+@A=А=w@.N>(>lo@oC?P?/??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh&? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr)>Y rx_data_ngccm[32] Jnet (fo=76, routed)Xh-?^ ,(SFP_GEN[32].rx_data_ngccm_reg[32][53]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)Xh@5?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[32].rx_data_ngccm_reg[32][53]/C JFDCEXhzr> Jclock pessimismXh.N>@ Jclock uncertaintyXhu )%SFP_GEN[32].rx_data_ngccm_reg[32][53]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh/,A; J arrival timeXhX/ JXh4 JslackXhw@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[32].rx_data_ngccm_reg[32][80]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuA`@}A=,Ad;w7@d;@A=А=%x@,N>(>e;o@oC?P?/?Ȧ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh&? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr)>Y rx_data_ngccm[32] Jnet (fo=76, routed)XhO?^ ,(SFP_GEN[32].rx_data_ngccm_reg[32][80]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)XhV?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[32].rx_data_ngccm_reg[32][80]/C JFDCEXhzr> Jclock pessimismXh,N>@ Jclock uncertaintyXhu )%SFP_GEN[32].rx_data_ngccm_reg[32][80]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh=,A; J arrival timeXh}?/ JXh4 JslackXh%x@LD@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsut@}AXS,A2I,@@A=А=^@>@P>#۹>i@oC?֣?/? ף?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/QProp_AFF2_SLICEM_C_Q JFDCEXhzrV> lhg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhL7 @ okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__31/I1 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__31/OProp_C6LUT_SLICEM_I1_O JLUT2XhzrA`e> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xhsh? g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhYd?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr> Jclock pessimismXh>@P>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhXS,A; J arrival timeXhQ/ JXh4 JslackXh^@D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuz@}AoW,A2I,@@A=А=!@>@P>#۹>^i@oC?֣?/? ף?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/QProp_AFF2_SLICEM_C_Q JFDCEXhzrV> lhg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhL7 @ okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__31/I1 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__31/OProp_C6LUT_SLICEM_I1_O JLUT2XhzrA`e> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh$? g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhYd?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh>@P>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhoW,A; J arrival timeXh/ JXh4 JslackXh!@D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu{@}A8S,A'I,@@A=А=@[8P>#۹>Id@oC?֣?/?W9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/QProp_AFF2_SLICEM_C_Q JFDCEXhzrV> lhg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhL7 @ okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__31/I1 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__31/OProp_C6LUT_SLICEM_I1_O JLUT2XhzrA`e> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh$? g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXh[8P>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh8S,A; J arrival timeXhl/ JXh4 JslackXh@D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuC{@}A_,A'I,@@A=А=\@[8P>#۹>2d@oC?֣?/?W9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/QProp_AFF2_SLICEM_C_Q JFDCEXhzrV> lhg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)XhL7 @ okg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__31/I1 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__31/OProp_C6LUT_SLICEM_I1_O JLUT2XhzrA`e> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xhʡ? g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh[8P>@ Jclock uncertaintyXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh_,A; J arrival timeXh/ JXh4 JslackXh\@g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[32].rx_data_ngccm_reg[32][65]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsur@}AM.A/Mw7@/@A=А=Z@Z>(>e;_@oC?P?/?!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh&? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr)>Y rx_data_ngccm[32] Jnet (fo=76, routed)XhO?^ ,(SFP_GEN[32].rx_data_ngccm_reg[32][65]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)] +'SFP_GEN[32].rx_data_ngccm_reg[32][65]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXhv )%SFP_GEN[32].rx_data_ngccm_reg[32][65]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhM.A; J arrival timeXh}?/ JXh4 JslackXhZ@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[32].rx_data_ngccm_reg[32][67]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsur@}AM.A/Mw7@/@A=А=Z@Z>(>e;_@oC?P?/?!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh&? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr)>Y rx_data_ngccm[32] Jnet (fo=76, routed)XhO?^ ,(SFP_GEN[32].rx_data_ngccm_reg[32][67]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)] +'SFP_GEN[32].rx_data_ngccm_reg[32][67]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXhv )%SFP_GEN[32].rx_data_ngccm_reg[32][67]Setup_FFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhM.A; J arrival timeXh}?/ JXh4 JslackXhZ@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[32].rx_data_ngccm_reg[32][69]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsur@}AM.A/Mw7@/@A=А=Z@Z>(>e;_@oC?P?/?!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh&? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr)>Y rx_data_ngccm[32] Jnet (fo=76, routed)XhO?^ ,(SFP_GEN[32].rx_data_ngccm_reg[32][69]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)] +'SFP_GEN[32].rx_data_ngccm_reg[32][69]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXhv )%SFP_GEN[32].rx_data_ngccm_reg[32][69]Setup_GFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhM.A; J arrival timeXh}?/ JXh4 JslackXhZ@Lg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[32].rx_data_ngccm_reg[32][71]/CE""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsur@}AM.A/Mw7@/@A=А=Z@Z>(>e;_@oC?P?/?!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh&? wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/I0 JXhzr vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/SFP_GEN[32].rx_data_ngccm[32][83]_i_1/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr)>Y rx_data_ngccm[32] Jnet (fo=76, routed)XhO?^ ,(SFP_GEN[32].rx_data_ngccm_reg[32][71]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>x g_gbt_bank[2].gbtbank_n_104 Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)] +'SFP_GEN[32].rx_data_ngccm_reg[32][71]/C JFDCEXhzr> Jclock pessimismXhZ>@ Jclock uncertaintyXhv )%SFP_GEN[32].rx_data_ngccm_reg[32][71]Setup_HFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhM.A; J arrival timeXh}?/ JXh4 JslackXhZ@L( !gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!)y@1y @9Ay@Iy @eP: @hq} x= wv?**# rise - rise rise - rise  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C+'SFP_GEN[33].rx_data_ngccm_reg[33][67]/D"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu>}HٮCn=|?ٮ?x=^P?9H==v>I "?R>lG?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[33][67] Jnet (fo=1, routed)Xh=] +'SFP_GEN[33].rx_data_ngccm_reg[33][67]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_114 Jnet (fo=674, routed)XhZd?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[33].rx_data_ngccm_reg[33][67]/C JFDCEXhzr> Jclock pessimismXh^P?t )%SFP_GEN[33].rx_data_ngccm_reg[33][67]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhH; J arrival timeXh-?/ JXh4 JslackXhx=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuX->}ϡ3=Nb??=bʡ=Q=v> #?R>yF?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_7_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__32/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__32/OProp_G6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh8?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh"?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhb g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhϡ; J arrival timeXh?/ JXh4 JslackXh=?+'SFP_GEN[33].rx_data_ngccm_reg[33][40]/C0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[40]/D"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu^d;>}$] "̴=a? ?= u=E=v>0$?R>I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR)x +'SFP_GEN[33].rx_data_ngccm_reg[33][40]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[83]_0[32] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[40]_i_1/I1 JXhzr 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[40]_i_1/OProp_D6LUT_SLICEL_I1_O JLUT3XhzrQ8=u 2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[40]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[2].gbtbank_n_114 Jnet (fo=674, routed)XhJ ?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[33].rx_data_ngccm_reg[33][40]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzr> Jclock pessimismXh ux .*SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[40]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh$]; J arrival timeXhQ?/ JXh4 JslackXh=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C+'SFP_GEN[33].rx_data_ngccm_reg[33][70]/D"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuS>} ٮCn=|?ٮ?]='=^P?9H==v>I "?R>lG?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H=V rx_data[33][70] Jnet (fo=1, routed)Xh=] +'SFP_GEN[33].rx_data_ngccm_reg[33][70]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_114 Jnet (fo=674, routed)XhZd?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[33].rx_data_ngccm_reg[33][70]/C JFDCEXhzr> Jclock pessimismXh^P?s )%SFP_GEN[33].rx_data_ngccm_reg[33][70]Hold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh ; J arrival timeXhS?/ JXh4 JslackXh]='=?+'SFP_GEN[33].rx_data_ngccm_reg[33][49]/C0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[48]/D"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu>}橞)\'IW=Đ?)\?)=$>=9H=v>$?R>rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR)x +'SFP_GEN[33].rx_data_ngccm_reg[33][49]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[83]_0[41] Jnet (fo=1, routed)Xh+=_ 1-SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[48]_i_1/I0 JXhzr 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[48]_i_1/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrT=u 2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40[48]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[48]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[2].gbtbank_n_114 Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[33].rx_data_ngccm_reg[33][49]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhm?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[48]/C JFDCEXhzr> Jclock pessimismXh$>x .*SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[48]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh橞; J arrival timeXh?/ JXh4 JslackXh)=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C+'SFP_GEN[33].rx_data_ngccm_reg[33][54]/D"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuX9>}ue;gJ=%?e;?0k7=ȄD='1>v>%?R>'1H?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/QProp_CFF_SLICEM_C_Q JFDREXhzrD=V rx_data[33][54] Jnet (fo=1, routed)Xh'1>] +'SFP_GEN[33].rx_data_ngccm_reg[33][54]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[2].gbtbank_n_114 Jnet (fo=674, routed)Xhƛ?X1Y4 (CLOCK_ROOT)] +'SFP_GEN[33].rx_data_ngccm_reg[33][54]/C JFDCEXhzr> Jclock pessimismXhȄs )%SFP_GEN[33].rx_data_ngccm_reg[33][54]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhu; J arrival timeXh'1?/ JXh4 JslackXh0k7=g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu)>}]`尿Y,=ʑ?`? G=M=Y=v>&?R>K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[0] Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__32/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__32/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhM g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh]; J arrival timeXh?/ JXh4 JslackXh G=6g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu)>}]`尿Y,=ʑ?`? G=M=Y=v>&?R>K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/O85[0] Jnet (fo=2, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__32/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__32/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] Jnet (fo=1, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXhM g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh]; J arrival timeXh?/ JXh4 JslackXh G=$eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[35]/Ceag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[35]/D"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu #>}e=ʑ??@H=D=A`=v>&?R>C?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[35]/QProp_CFF_SLICEM_C_Q JFDCEXhzrD= _[g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[35] Jnet (fo=1, routed)XhA`= eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[35]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[35]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[35]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[35]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXhE?/ JXh4 JslackXh@H=]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg/C]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg/D"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuS=}T㕿㥫֣;{?㥫?L=lgo=@=v>d;?R>$A?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/ready_from_bitSlipCtrller_9 Jnet (fo=2, routed)Xh)\= b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_i_1__32/I2 JXhzr a]g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_i_1__32/OProp_A6LUT_SLICEL_I2_O JLUT3Xhzru< c_g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_i_1__32_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv~?X1Y4 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1?X1Y4 (CLOCK_ROOT) ]Yg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXhlg [Wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].rxBitSlipControl/READY_o_regHold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhT㕿; J arrival timeXhI?/ JXh4 JslackXhL=}!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu~@}A0A|'-=V.@|'@A=А=P: @jX>ʡ?@yF??-2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh}?e@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrQ= sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32/OProp_D6LUT_SLICEL_I2_O JLUT4Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32_n_0 Jnet (fo=1, routed)XhP= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32_n_0 Jnet (fo=2, routed)Xhu> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl@X1Y4 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhjX>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhP: @ }!g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu~@}A0A|'-=V.@|'@A=А=P: @jX>ʡ?@yF??-2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh}?e@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrQ= sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhQ> okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32/I2 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32/OProp_D6LUT_SLICEL_I2_O JLUT4Xhzr> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__32_n_0 Jnet (fo=1, routed)XhP= okg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32/I5 JXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__32_n_0 Jnet (fo=2, routed)Xhu> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl@X1Y4 (CLOCK_ROOT) jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhjX>@ Jclock uncertaintyXh hdg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhP: @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu'\@}Aj0Ay&^=V.@y&@A=А=U%@jX>в?流@yF??-2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh}?e@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfQ= sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh&1> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__33/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__33/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhjX>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXhj0A; J arrival timeXhC/ JXh4 JslackXhU%@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsud;@}A0Ay&^=V.@y&@A=А=.&@jX>в?+@yF??-2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh}?e@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfQ= sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh&1> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__33/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__33/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhjX>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[2]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh33/ JXh4 JslackXh.&@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsud;@}A0Ay&^=V.@y&@A=А=.&@jX>в?+@yF??-2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh}?e@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfQ= sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh&1> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__33/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__33/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh? xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhjX>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Setup_GFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh33/ JXh4 JslackXh.&@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu@}AQ0A& =V.@&@A=А=8(@jX>罹?A@yF??-2?z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh}?e@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrQ= sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhc? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhjX>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXhQ0A; J arrival timeXhC/ JXh4 JslackXh8(@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsu@}AQ0A& =V.@&@A=А=8(@jX>罹?A@yF??-2?z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh}?e@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrQ= sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhc? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhjX>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXhQ0A; J arrival timeXhC/ JXh4 JslackXh8(@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuʵ@}A0A& =V.@&@A=А=(@jX>罹? @yF??-2?z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh}?e@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrQ= sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh= ? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhjX>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXhz/ JXh4 JslackXh(@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuʵ@}A0A& =V.@&@A=А=(@jX>罹? @yF??-2?z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh}?e@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrQ= sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/I3 JXhzr wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__33/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr`P= ^Zg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh= ? tpg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhjX>@ Jclock uncertaintyXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXhz/ JXh4 JslackXh(@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuv@}A0A& =V.@&@A=А=ܦ/@jX>в?…@yF??-2?z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? rng_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][3] Jnet (fo=10, routed)Xh}?e@ qmg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/I2 JXhzr plg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__32/OProp_D6LUT_SLICEL_I2_O JLUT4XhzfQ= sog_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh&1> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__33/I0 JXhzf {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__33/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr> b^g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhjX>@ Jclock uncertaintyXh uqg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[1]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhܦ/@ ( !gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!)y@1y @9Ay@Iy @eK@hq} y= uv?,,' rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu:A>}+|c=?|?y=#=\=%>x?>F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xhʡ= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__35/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__35/OProp_D6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[13] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh1?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr> Jclock pessimismXh# g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh+; J arrival timeXh+?/ JXh4 JslackXhy=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C+'SFP_GEN[36].rx_data_ngccm_reg[36][24]/D"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuF>}ENb6= ?Nb?@=5#9H=z>%>I "?>rH?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H=V rx_data[36][24] Jnet (fo=1, routed)Xhz>] +'SFP_GEN[36].rx_data_ngccm_reg[36][24]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][24]/C JFDCEXhzr> Jclock pessimismXh5#t )%SFP_GEN[36].rx_data_ngccm_reg[36][24]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhE; J arrival timeXh?/ JXh4 JslackXh@=D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CGCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/D"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu>}e;F=ף?e;??B=lCo=X9=%>o#?>$F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H= }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]_1[5] Jnet (fo=7, routed)Xht= ~zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i[0]_i_1__2/I3 JXhzr }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i[0]_i_1__2/OProp_C6LUT_SLICEM_I3_O JLUT6Xhzru<m *&g_gbt_bank[3].gbtbank/i_gbt_bank_n_144 Jnet (fo=1, routed)Xho<y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhʁ?X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƛ?X1Y7 (CLOCK_ROOT)y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C JFDCEXhzr> Jclock pessimismXhlC EAg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh?B=n0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[21]/CGCSFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[5]/D"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuX9>}sw=rh?w?lC=#D='1>%>$?>+G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR)~ 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[21]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD=p -)SFP_GEN[36].ngCCM_gbt/gbt_rx_checker/Q[5] Jnet (fo=4, routed)Xh'1>y GCSFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[5]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh\?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[36].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhI?X1Y7 (CLOCK_ROOT)y GCSFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[5]/C JFDREXhzr> Jclock pessimismXh# EASFP_GEN[36].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[5]Hold_AFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhs; J arrival timeXhu?/ JXh4 JslackXhlC=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C+'SFP_GEN[36].rx_data_ngccm_reg[36][75]/D"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu+>}۟/̀=ף?/?E=#9H==%>o#?>L B?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[36][75] Jnet (fo=1, routed)Xh=] +'SFP_GEN[36].rx_data_ngccm_reg[36][75]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhʁ?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh_?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][75]/C JFDCEXhzr> Jclock pessimismXh#s )%SFP_GEN[36].rx_data_ngccm_reg[36][75]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh۟; J arrival timeXh?/ JXh4 JslackXhE=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu>}@hD;=d;?h?/E=C%=-=%>A ?>B?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xht= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__35/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__35/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xhu< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhNb?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhC g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh@; J arrival timeXhn?/ JXh4 JslackXh/E=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C+'SFP_GEN[36].rx_data_ngccm_reg[36][28]/D"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu\I>} Nb6= ?Nb?@H=5#9H=P>%>I "?>rH?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H=V rx_data[36][28] Jnet (fo=1, routed)XhP>] +'SFP_GEN[36].rx_data_ngccm_reg[36][28]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][28]/C JFDCEXhzr> Jclock pessimismXh5#t )%SFP_GEN[36].rx_data_ngccm_reg[36][28]Hold_GFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh ; J arrival timeXhX?/ JXh4 JslackXh@H=@+'SFP_GEN[36].rx_data_ngccm_reg[36][66]/C0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[66]/D"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu&1>}丟V'ވ=?V?'M=$-= =%>!?>A?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR)x +'SFP_GEN[36].rx_data_ngccm_reg[36][66]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[83]_0[58] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[36].ngCCM_gbt/RX_Word_rx40[66]_i_1/I1 JXhzr 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40[66]_i_1/OProp_D5LUT_SLICEL_I1_O JLUT3Xhzr=u 2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40[66]_i_1_n_0 Jnet (fo=1, routed)XhX94<b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[66]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh&?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][66]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[66]/C JFDCEXhzr> Jclock pessimismXh$y .*SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[66]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh丟; J arrival timeXh$?/ JXh4 JslackXh'M=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuT>} ?)=??O=5N=/]=%>"?>yF?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__35/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__35/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh(?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh5N g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXht?/ JXh4 JslackXhO=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C+'SFP_GEN[36].rx_data_ngccm_reg[36][38]/D"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu >}囝Ao=8?A?S=5ND=9=%>0$?>)1H?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/QProp_CFF_SLICEM_C_Q JFDREXhzrD=V rx_data[36][38] Jnet (fo=1, routed)Xh9=] +'SFP_GEN[36].rx_data_ngccm_reg[36][38]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh!?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh̜?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][38]/C JFDCEXhzr> Jclock pessimismXh5Nt )%SFP_GEN[36].rx_data_ngccm_reg[36][38]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh囝; J arrival timeXhY9?/ JXh4 JslackXhS=g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][17]/CE"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuMb@}A1A) i89@)@A=А=K@ϺX>> @CK?? ?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhw'@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh@^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][17]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][17]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXhv )%SFP_GEN[36].rx_data_ngccm_reg[36][17]Setup_AFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh1A; J arrival timeXh&/ JXh4 JslackXhK@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][16]/CE"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuI@}A1A) i89@)@A=А=L@ϺX>>1@CK?? ?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhw'@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[36] Jnet (fo=76, routed)XhQ@^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][16]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][16]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXhu )%SFP_GEN[36].rx_data_ngccm_reg[36][16]Setup_AFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh1A; J arrival timeXhW/ JXh4 JslackXhL@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][24]/CE"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu@}A,1A[*89@[*@A=А=L@ϺX>>F@CK?? ?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhw'@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh(\?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][24]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh~@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][24]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXhv )%SFP_GEN[36].rx_data_ngccm_reg[36][24]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh,1A; J arrival timeXhk/ JXh4 JslackXhL@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][26]/CE"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu@}A,1A[*89@[*@A=А=L@ϺX>>F@CK?? ?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhw'@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh(\?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][26]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh~@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][26]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXhv )%SFP_GEN[36].rx_data_ngccm_reg[36][26]Setup_FFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh,1A; J arrival timeXhk/ JXh4 JslackXhL@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][28]/CE"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu@}A,1A[*89@[*@A=А=L@ϺX>>F@CK?? ?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhw'@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh(\?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][28]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh~@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][28]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXhv )%SFP_GEN[36].rx_data_ngccm_reg[36][28]Setup_GFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh,1A; J arrival timeXhk/ JXh4 JslackXhL@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][33]/CE"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu@}A,1A[*89@[*@A=А=L@ϺX>>F@CK?? ?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhw'@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh(\?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][33]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh~@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][33]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXhv )%SFP_GEN[36].rx_data_ngccm_reg[36][33]Setup_HFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh,1A; J arrival timeXhk/ JXh4 JslackXhL@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][19]/CE"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu<ߟ@}Av1A[*89@[*@A=А=)ZM@ϺX>>@CK?? ?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhw'@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][19]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh~@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][19]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXhu )%SFP_GEN[36].rx_data_ngccm_reg[36][19]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhv1A; J arrival timeXhף/ JXh4 JslackXh)ZM@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][25]/CE"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu<ߟ@}Av1A[*89@[*@A=А=)ZM@ϺX>>@CK?? ?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhw'@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][25]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh~@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][25]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXhu )%SFP_GEN[36].rx_data_ngccm_reg[36][25]Setup_FFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhv1A; J arrival timeXhף/ JXh4 JslackXh)ZM@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][27]/CE"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu<ߟ@}Av1A[*89@[*@A=А=)ZM@ϺX>>@CK?? ?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhw'@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][27]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh~@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][27]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXhu )%SFP_GEN[36].rx_data_ngccm_reg[36][27]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhv1A; J arrival timeXhף/ JXh4 JslackXh)ZM@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[36].rx_data_ngccm_reg[36][29]/CE"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu<ߟ@}Av1A[*89@[*@A=А=)ZM@ϺX>>@CK?? ?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhw'@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/SFP_GEN[36].rx_data_ngccm[36][83]_i_1/OProp_E6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[36] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[36].rx_data_ngccm_reg[36][29]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank_n_0 Jnet (fo=674, routed)Xh~@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[36].rx_data_ngccm_reg[36][29]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXhu )%SFP_GEN[36].rx_data_ngccm_reg[36][29]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXhv1A; J arrival timeXhף/ JXh4 JslackXh)ZM@L( !gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!)y@1y @9Ay@Iy @e8@hq} .= vv?--* rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuv>>}(`п=?`?.=B'=j=V>+?+?FS?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_23_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__45/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__45/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh&?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXhB' g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh(; J arrival timeXhη?/ JXh4 JslackXh.=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C+'SFP_GEN[46].rx_data_ngccm_reg[46][29]/D"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu|.>} ౿_=%??=6E'9H==V>-?+?&Q?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=V rx_data[46][29] Jnet (fo=1, routed)Xh=] +'SFP_GEN[46].rx_data_ngccm_reg[46][29]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_124 Jnet (fo=674, routed)Xh(?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[46].rx_data_ngccm_reg[46][29]/C JFDCEXhzr> Jclock pessimismXh6E's )%SFP_GEN[46].rx_data_ngccm_reg[46][29]Hold_EFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh ౿; J arrival timeXhȶ?/ JXh4 JslackXh=fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[26]/Cfbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[26]/D"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuS>}ί-{=a?-?=&o'9H==V>j-?+?OM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[26]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= `\g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[26] Jnet (fo=1, routed)Xh= fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[26]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhJ ?X1Y8 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[26]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhq=?X1Y8 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[26]/C JFDCEXhzr> Jclock pessimismXh&o' d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[26]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhί; J arrival timeXhk?/ JXh4 JslackXh=J+'SFP_GEN[46].rx_data_ngccm_reg[46][44]/C0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[44]/D"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuǡE>}yn¿G=?n?4= '[=9=V>/?+?V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)y +'SFP_GEN[46].rx_data_ngccm_reg[46][44]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[83]_0[36] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[44]_i_1/I1 JXhzr 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[44]_i_1/OProp_D6LUT_SLICEM_I1_O JLUT3Xhzrj<=u 2.SFP_GEN[46].ngCCM_gbt/RX_Word_rx40[44]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[44]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[3].gbtbank_n_124 Jnet (fo=674, routed)XhВ?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[46].rx_data_ngccm_reg[46][44]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[46].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[44]/C JFDCEXhzr> Jclock pessimismXh 'x .*SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[44]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhy; J arrival timeXh5^?/ JXh4 JslackXh4=u0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[18]/CGCSFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuL>}!¿=%?!?74='9H=>V>-?+?KW?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)} 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[18]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H=p -)SFP_GEN[46].ngCCM_gbt/gbt_rx_checker/Q[2] Jnet (fo=5, routed)Xh>y GCSFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[46].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[46].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[46].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X1Y8 (CLOCK_ROOT)y GCSFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/C JFDREXhzr> Jclock pessimismXh' EASFP_GEN[46].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]Hold_AFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh74=Mg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu>})"M¿Y,=\?M?|C=]R=T=V>a0?+?+V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/O85[0] Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__45/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__45/OProp_B6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] Jnet (fo=1, routed)Xhu< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhٮ?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXh]R g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh)"; J arrival timeXh}??/ JXh4 JslackXh|C=fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg/Cfbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsui;=}刺h֣; ?h?D=iffo=Q8=V>1,?+?WM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/rxslide_in[0] Jnet (fo=2, routed)Xh+= kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__45/I2 JXhzr jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__45/OProp_A6LUT_SLICEM_I2_O JLUT3Xhzru< lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__45_n_0 Jnet (fo=1, routed)XhD< fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= TPg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/CLK Jnet (fo=674, routed)XhG?X1Y8 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> TPg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzr> Jclock pessimismXhiff d`g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/RX_BITSLIPCMD_o_regHold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh刺; J arrival timeXh{?/ JXh4 JslackXhD=fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[25]/Cfbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[25]/D"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu5,>}-=ף?-?wF=dt'D==V>W-?+?OM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[25]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD= `\g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0[25] Jnet (fo=1, routed)Xh= fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[25]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhʑ?X1Y8 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg0_reg[25]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhq=?X1Y8 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[25]/C JFDCEXhzr> Jclock pessimismXhdt' d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/reg1_reg[25]Hold_EFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh$?/ JXh4 JslackXhwF=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu)>}mݭ?)=rh??L}K=P[=T=V>.?+?tS?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)Xht= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__45/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__45/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzrj<= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[5] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXhP g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhmݭ; J arrival timeXhX9?/ JXh4 JslackXhL}K=^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/C^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/D"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuS=}h֣;<ߟ?h?L=rho=@=V> +?+?WM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= mig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/ready_from_bitSlipCtrller_10 Jnet (fo=2, routed)Xh)\= c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_i_1__45/I2 JXhzr b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_i_1__45/OProp_A6LUT_SLICEL_I2_O JLUT3Xhzru< d`g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_i_1__45_n_0 Jnet (fo=1, routed)XhD< ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= TPg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh%?X1Y8 (CLOCK_ROOT) ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> TPg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXhrh \Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].rxBitSlipControl/READY_o_regHold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh{?/ JXh4 JslackXhL=!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsur@}A6A>!/>q=B@>@A=А=8@SEj>p?-z@5^?F?l{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhp=@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I3 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrFs> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhL7> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45/I2 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45/OProp_D5LUT_SLICEL_I2_O JLUT4Xhzr= qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45_n_0 Jnet (fo=1, routed)Xhim> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45/I5 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45_n_0 Jnet (fo=2, routed)XhT> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= '@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)Xh+&@X1Y8 (CLOCK_ROOT) kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhSEj>@ Jclock uncertaintyXh ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh6A; J arrival timeXh/ JXh4 JslackXh8@ !g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsur@}A6A>!/>q=B@>@A=А=8@SEj>p?-z@5^?F?l{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhp=@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I3 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrFs> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhL7> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45/I2 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45/OProp_D5LUT_SLICEL_I2_O JLUT4Xhzr= qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_7__45_n_0 Jnet (fo=1, routed)Xhim> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45/I5 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state[1]_i_1__45_n_0 Jnet (fo=2, routed)XhT> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= '@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)Xh+&@X1Y8 (CLOCK_ROOT) kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhSEj>@ Jclock uncertaintyXh ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh6A; J arrival timeXh/ JXh4 JslackXh8@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuo@}AJ6AV>+>q=B@V>@A=А=C@SEj>K?~r@5^?F?l{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhp=@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I3 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrFs> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr֣p> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh{? uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= '@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)XhE&@X1Y8 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhSEj>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhJ6A; J arrival timeXh/ JXh4 JslackXhC@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu@}Ab6AV>+>q=B@V>@A=А=pC@SEj>K?p=r@5^?F?l{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhp=@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I3 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrFs> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr֣p> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhU ? uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= '@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)XhE&@X1Y8 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhSEj>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhb6A; J arrival timeXh2/ JXh4 JslackXhpC@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuK@}A6A>2>q=B@>@A=А=K@SEj>K?j@5^?F?l{?|?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhp=@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I3 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrFs> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr֣p> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhw> uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= '@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)XhR&@X1Y8 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhSEj>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh6A; J arrival timeXh@5/ JXh4 JslackXhK@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu+@}A 7A>2>q=B@>@A=А=pK@SEj>K?!j@5^?F?l{?|?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhp=@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I3 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrFs> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr֣p> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh.> uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= '@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)XhR&@X1Y8 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhSEj>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh 7A; J arrival timeXh$/ JXh4 JslackXhpK@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu+@}A 7A>2>q=B@>@A=А=pK@SEj>K?!j@5^?F?l{?|?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhp=@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I3 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrFs> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr֣p> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh.> uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= '@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)XhR&@X1Y8 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhSEj>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh 7A; J arrival timeXh$/ JXh4 JslackXhpK@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu6^@}A{6Av>->q=B@v>@A=А=L@SEj>K?i@5^?F?l{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhp=@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I3 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrFs> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr֣p> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xha> uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= '@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)Xhff&@X1Y8 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhSEj>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh{6A; J arrival timeXhw/ JXh4 JslackXhL@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu6^@}A{6Av>->q=B@v>@A=А=L@SEj>K?i@5^?F?l{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhp=@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I3 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEL_I3_O JLUT4XhzrFs> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhI> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__46/OProp_E6LUT_SLICEL_I3_O JLUT5Xhzr֣p> _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xha> uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= '@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)Xhff&@X1Y8 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhSEj>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh{6A; J arrival timeXhw/ JXh4 JslackXhL@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuj@}Al6A=%>q=B@=@A=А=n7W@SEj>1?tc@5^?F?l{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xhp=@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/I3 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__45/OProp_D6LUT_SLICEL_I3_O JLUT4XhzfFs> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhE= }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/I0 JXhzf |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__46/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr+> c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)XhG? yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh= '@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/CLK Jnet (fo=674, routed)XhT%@X1Y8 (CLOCK_ROOT) xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhSEj>@ Jclock uncertaintyXh vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXhl6A; J arrival timeXh/ JXh4 JslackXhn7W@ ( !gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!)y@1y @9Ay@Iy @ed@hq} = uv?..- rise - rise rise - rise  fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[27]/Cfbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu5,>}dV=G??=$?G>gfF?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[27]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD= `\g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0[27] Jnet (fo=1, routed)Xh= fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhn?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[27]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh ?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]/C JFDCEXhzr> Jclock pessimismXh}ԟ%W=?%?6p1=?B=`P=>T%?G>~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__46/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__46/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrT= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xho?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhi?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh?B g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhԟ; J arrival timeXhA`?/ JXh4 JslackXh6p1=H+'SFP_GEN[47].rx_data_ngccm_reg[47][41]/C0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[40]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuV>}w~=ʑ??ay;=Ov=j<=>ˡ%?G>xI?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR)y +'SFP_GEN[47].rx_data_ngccm_reg[47][41]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[83]_0[33] Jnet (fo=1, routed)XhC =_ 1-SFP_GEN[47].ngCCM_gbt/RX_Word_rx40[40]_i_1/I0 JXhzr 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40[40]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT3XhzrQ8=u 2.SFP_GEN[47].ngCCM_gbt/RX_Word_rx40[40]_i_1_n_0 Jnet (fo=1, routed)XhD<b 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[40]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[3].gbtbank_n_134 Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[47].rx_data_ngccm_reg[47][41]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhV?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzr> Jclock pessimismXhOx .*SFP_GEN[47].ngCCM_gbt/RX_Word_rx40_reg[40]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhay;=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsut>}shY,=I ?sh?ay;=O=L=>$&?G>CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__46/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__46/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh33?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXhO g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhz?/ JXh4 JslackXhay;=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu>}JC=??Y==vC=9H=>I "?G>ˡE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)Xh+= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__46/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__46/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrT= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh&?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh"?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXhvC g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhJ; J arrival timeXh33?/ JXh4 JslackXhY==Kg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu)>}O|7=rh?|?1==*B%=1=>/$?G>lG?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_GFF_SLICEL_C_Q JFDCEXhzrD= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/O85[0] Jnet (fo=2, routed)Xht= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__46/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__46/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh1?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXh*B g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhO; J arrival timeXhW9?/ JXh4 JslackXh1==g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[8]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu433>}ž|k=-?|?\>=hI  =E=>gf&?G>lG?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[8]/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_15_in Jnet (fo=2, routed)Xh-= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__46/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__46/OProp_G5LUT_SLICEL_I2_O JLUT3Xhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[6] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh1?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXhhI  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Hold_GFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhž; J arrival timeXhu?/ JXh4 JslackXh\>=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsut>}2a尿o=?a?L}K=P=L=>T%?G>r=J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_BFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__46/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__46/OProp_F6LUT_SLICEM_I0_O JLUT3Xhzrj<= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xho?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhP g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_FFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh2; J arrival timeXhZ?/ JXh4 JslackXhL}K=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsut>}`󭿭=)\?? UM=M=L=> ?G>ZD?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] Jnet (fo=1, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__46/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__46/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[1] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXhM g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh`; J arrival timeXhʡ?/ JXh4 JslackXh UM=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuw>}shY,=I ?sh?CO=O=Q8=>$&?G>CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__46/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__46/OProp_D5LUT_SLICEL_I0_O JLUT3XhzrGa= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[3] Jnet (fo=1, routed)XhX94< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh33?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr> Jclock pessimismXhO g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[3]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhCO=}!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu@}A0A|'=.@|'@A=А=d@nU>֣?@^I??4?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhR> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46/I2 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46/OProp_D5LUT_SLICEM_I2_O JLUT4XhzrˡE> qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46_n_0 Jnet (fo=1, routed)XhSc> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46/I5 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46/OProp_C6LUT_SLICEM_I5_O JLUT6Xhzr +> qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46_n_0 Jnet (fo=2, routed)XhԸ> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xhl@X1Y9 (CLOCK_ROOT) kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhnU>@ Jclock uncertaintyXh ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXhX / JXh4 JslackXhd@ }!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu@}A0A|'=.@|'@A=А=d@nU>֣?@^I??4?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhR> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46/I2 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46/OProp_D5LUT_SLICEM_I2_O JLUT4XhzrˡE> qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_7__46_n_0 Jnet (fo=1, routed)XhSc> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46/I5 JXhzr okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46/OProp_C6LUT_SLICEM_I5_O JLUT6Xhzr +> qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state[1]_i_1__46_n_0 Jnet (fo=2, routed)XhԸ> lhg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xhl@X1Y9 (CLOCK_ROOT) kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhnU>@ Jclock uncertaintyXh ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh0A; J arrival timeXhX / JXh4 JslackXhd@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu5^@}A.0A(\'8=.@(\'@A=А=6H0@nU>}??U@^I??4??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__47/I5 JXhzr zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__47/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> a]g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)XhK@X1Y9 (CLOCK_ROOT) vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhnU>@ Jclock uncertaintyXh tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_GFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh.0A; J arrival timeXh!/ JXh4 JslackXh6H0@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu5^@}A.0A(\'8=.@(\'@A=А=6H0@nU>}??U@^I??4??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__47/I5 JXhzr zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__47/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> a]g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh> wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)XhK@X1Y9 (CLOCK_ROOT) vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhnU>@ Jclock uncertaintyXh tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh.0A; J arrival timeXh!/ JXh4 JslackXh6H0@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuE@}Ax0A(\'8=.@(\'@A=А=0@nU>}??@^I??4??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__47/I5 JXhzr zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__47/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> a]g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xhq=> wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)XhK@X1Y9 (CLOCK_ROOT) vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhnU>@ Jclock uncertaintyXh tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhx0A; J arrival timeXhף/ JXh4 JslackXh0@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuR@}A0A&}=.@&@A=А=B?@nU>V?E~@^I??4?o?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/OProp_B6LUT_SLICEM_I3_O JLUT5Xhzrj= _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh > uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhnU>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh// JXh4 JslackXhB?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuR@}A0A&}=.@&@A=А=B?@nU>V?E~@^I??4?o?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/OProp_B6LUT_SLICEM_I3_O JLUT5Xhzrj= _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh > uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhnU>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh// JXh4 JslackXhB?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu-@}Aa0AK'=.@K'@A=А=K@@nU>V?/}@^I??4??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/OProp_B6LUT_SLICEM_I3_O JLUT5Xhzrj= _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh"> uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xhd;@X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhnU>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXha0A; J arrival timeXh/ JXh4 JslackXhK@@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuK @}Ax0AK'=.@K'@A=А=1A@nU>V?|@^I??4??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/OProp_B6LUT_SLICEM_I3_O JLUT5Xhzrj= _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)Xhd;@X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhnU>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhx0A; J arrival timeXh,/ JXh4 JslackXh1A@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuG@}A0A'=.@'@A=А=B@nU>V?[d{@^I??4??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)XhTU@ rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__46/OProp_D6LUT_SLICEL_I1_O JLUT4Xhzr)> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv>> yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/I3 JXhzr xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__47/OProp_B6LUT_SLICEM_I3_O JLUT5Xhzrj= _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> QMg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/CLK Jnet (fo=674, routed)XhP@X1Y9 (CLOCK_ROOT) tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhnU>@ Jclock uncertaintyXh rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh$/ JXh4 JslackXhB@ ( !gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!)y@1y @9Ay@Iy @ea@hq} 2 = uv?//1 rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C+'SFP_GEN[37].rx_data_ngccm_reg[37][33]/D"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuR%>}A}RV =o?R?2 =o*9H=l=>'1?G>T%?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[37][33] Jnet (fo=1, routed)Xhl=] +'SFP_GEN[37].rx_data_ngccm_reg[37][33]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhrh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)XhC?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][33]/C JFDCEXhzr> Jclock pessimismXho*t )%SFP_GEN[37].rx_data_ngccm_reg[37][33]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhA}; J arrival timeXhΗ?/ JXh4 JslackXh2 =g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuC>}[Ε`堿XX=M?`?E=:==>?G>p=*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)XhT= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__36/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__36/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhyf?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh[Ε; J arrival timeXh?/ JXh4 JslackXhE=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuQ8>}S蔿o=??r"=wʡ==>?G>r(?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/QProp_EFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_25_in Jnet (fo=2, routed)Xh{= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__36/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__36/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1h?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhD?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXhw g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhS蔿; J arrival timeXh?/ JXh4 JslackXhr"=p0,SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]/CHDSFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[18]/D"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuR%>}<vÇ=F?v?&="9H=l=>x ?G>B`%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)} 0,SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H=q .*SFP_GEN[37].ngCCM_gbt/gbt_rx_checker/Q[18] Jnet (fo=2, routed)Xhl=z HDSFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[18]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^i?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[37].ngCCM_gbt/RX_Word_rx40_reg[82]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[37].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y7 (CLOCK_ROOT)z HDSFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[18]/C JFDREXhzr> Jclock pessimismXh" FBSFP_GEN[37].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[18]Hold_FFF2_SLICEM_C_D JFDREXhGa=/ JXh< J required timeXh<; J arrival timeXhr?/ JXh4 JslackXh&=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu9H>}[Ε`堿XX=M?`?2=:=j=>?G>p=*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in Jnet (fo=2, routed)XhT= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__36/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__36/OProp_C5LUT_SLICEM_I0_O JLUT3XhzrGa= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[7] Jnet (fo=1, routed)XhX94< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhyf?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr> Jclock pessimismXh: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]Hold_CFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh[Ε; J arrival timeXhZd?/ JXh4 JslackXh2=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuS>}ψv`=Z?? 5=|a2o=5^=> ?G>+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_HFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh㥛= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__36/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__36/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzro< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xhu< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh k?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh|a2 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhψ; J arrival timeXh'1?/ JXh4 JslackXh 5=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[37].rx_data_ngccm_reg[37][39]/D"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsut>}{/=??c<=C4D==>?G>gf&?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[37][39] Jnet (fo=1, routed)Xh=] +'SFP_GEN[37].rx_data_ngccm_reg[37][39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1h?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][39]/C JFDCEXhzr> Jclock pessimismXhC4t )%SFP_GEN[37].rx_data_ngccm_reg[37][39]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh{; J arrival timeXhB`?/ JXh4 JslackXhc<=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuQ8>}g"d;C=43?d;?CaC=E=5^=>r?G>y&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xhʡ= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__36/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__36/OProp_D5LUT_SLICEM_I2_O JLUT3Xhzr #= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[14] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh:h?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhƋ?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]Hold_DFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhg"; J arrival timeXhq=?/ JXh4 JslackXhCaC=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C+'SFP_GEN[37].rx_data_ngccm_reg[37][69]/D"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuxh>}F%}?w=?}?? C=):D==>W9?G>2?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[37][69] Jnet (fo=1, routed)Xh=] +'SFP_GEN[37].rx_data_ngccm_reg[37][69]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhzt?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xhʑ?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][69]/C JFDCEXhzr> Jclock pessimismXh):t )%SFP_GEN[37].rx_data_ngccm_reg[37][69]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhF%; J arrival timeXhC?/ JXh4 JslackXh C=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[9]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu.>}m9K=b?K?0S=9 =1=>-?G>= 7?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[9]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_17_in Jnet (fo=2, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__36/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__36/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[9] Jnet (fo=1, routed)XhX94< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhnr?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ד?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr> Jclock pessimismXh9 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]Hold_DFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhm9; J arrival timeXhҝ?/ JXh4 JslackXh0S=g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[37].rx_data_ngccm_reg[37][69]/CE"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu:@}Ai.AF7<7@@A=А=a@2.\>>r@I?Z?}?5?\?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[37] Jnet (fo=76, routed)Xh @^ ,(SFP_GEN[37].rx_data_ngccm_reg[37][69]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][69]/C JFDCEXhzr> Jclock pessimismXh2.\>@ Jclock uncertaintyXhv )%SFP_GEN[37].rx_data_ngccm_reg[37][69]Setup_AFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhi.A; J arrival timeXhף/ JXh4 JslackXha@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[37].rx_data_ngccm_reg[37][68]/CE"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsut@}A.AF7<7@@A=А=a@2.\>>Q@I?Z?}?5?\?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[37] Jnet (fo=76, routed)Xh^ @^ ,(SFP_GEN[37].rx_data_ngccm_reg[37][68]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][68]/C JFDCEXhzr> Jclock pessimismXh2.\>@ Jclock uncertaintyXhu )%SFP_GEN[37].rx_data_ngccm_reg[37][68]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh.A; J arrival timeXh/ JXh4 JslackXha@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[37].rx_data_ngccm_reg[37][70]/CE"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsut@}A.AF7<7@@A=А=a@2.\>>Q@I?Z?}?5?\?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[37] Jnet (fo=76, routed)Xh^ @^ ,(SFP_GEN[37].rx_data_ngccm_reg[37][70]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][70]/C JFDCEXhzr> Jclock pessimismXh2.\>@ Jclock uncertaintyXhu )%SFP_GEN[37].rx_data_ngccm_reg[37][70]Setup_BFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh.A; J arrival timeXh/ JXh4 JslackXha@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[37].rx_data_ngccm_reg[37][65]/CE"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsum@}A.A+`*/<7@+@A=А=Pk@>\>>K@I?Z?}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[37] Jnet (fo=76, routed)XhNb@^ ,(SFP_GEN[37].rx_data_ngccm_reg[37][65]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][65]/C JFDCEXhzr> Jclock pessimismXh>\>@ Jclock uncertaintyXhv )%SFP_GEN[37].rx_data_ngccm_reg[37][65]Setup_AFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh.A; J arrival timeXh / JXh4 JslackXhPk@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[37].rx_data_ngccm_reg[37][71]/CE"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsum@}A.A+`*/<7@+@A=А=Pk@>\>>K@I?Z?}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[37] Jnet (fo=76, routed)XhNb@^ ,(SFP_GEN[37].rx_data_ngccm_reg[37][71]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][71]/C JFDCEXhzr> Jclock pessimismXh>\>@ Jclock uncertaintyXhv )%SFP_GEN[37].rx_data_ngccm_reg[37][71]Setup_BFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh.A; J arrival timeXh / JXh4 JslackXhPk@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[37].rx_data_ngccm_reg[37][73]/CE"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsum@}A.A+`*/<7@+@A=А=Pk@>\>>K@I?Z?}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[37] Jnet (fo=76, routed)XhNb@^ ,(SFP_GEN[37].rx_data_ngccm_reg[37][73]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][73]/C JFDCEXhzr> Jclock pessimismXh>\>@ Jclock uncertaintyXhv )%SFP_GEN[37].rx_data_ngccm_reg[37][73]Setup_CFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh.A; J arrival timeXh / JXh4 JslackXhPk@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[37].rx_data_ngccm_reg[37][75]/CE"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsum@}A.A+`*/<7@+@A=А=Pk@>\>>K@I?Z?}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[37] Jnet (fo=76, routed)XhNb@^ ,(SFP_GEN[37].rx_data_ngccm_reg[37][75]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][75]/C JFDCEXhzr> Jclock pessimismXh>\>@ Jclock uncertaintyXhv )%SFP_GEN[37].rx_data_ngccm_reg[37][75]Setup_DFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh.A; J arrival timeXh / JXh4 JslackXhPk@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[37].rx_data_ngccm_reg[37][64]/CE"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuƋ@}A.A+`*/<7@+@A=А=:l@>\>>= @I?Z?}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[37] Jnet (fo=76, routed)Xh @^ ,(SFP_GEN[37].rx_data_ngccm_reg[37][64]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][64]/C JFDCEXhzr> Jclock pessimismXh>\>@ Jclock uncertaintyXhu )%SFP_GEN[37].rx_data_ngccm_reg[37][64]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh.A; J arrival timeXhE/ JXh4 JslackXh:l@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[37].rx_data_ngccm_reg[37][66]/CE"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuƋ@}A.A+`*/<7@+@A=А=:l@>\>>= @I?Z?}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[37] Jnet (fo=76, routed)Xh @^ ,(SFP_GEN[37].rx_data_ngccm_reg[37][66]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][66]/C JFDCEXhzr> Jclock pessimismXh>\>@ Jclock uncertaintyXhu )%SFP_GEN[37].rx_data_ngccm_reg[37][66]Setup_BFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh.A; J arrival timeXhE/ JXh4 JslackXh:l@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[37].rx_data_ngccm_reg[37][72]/CE"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuƋ@}A.A+`*/<7@+@A=А=:l@>\>>= @I?Z?}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/SFP_GEN[37].rx_data_ngccm[37][83]_i_1/OProp_H6LUT_SLICEM_I0_O JLUT6Xhzr"y>Y rx_data_ngccm[37] Jnet (fo=76, routed)Xh @^ ,(SFP_GEN[37].rx_data_ngccm_reg[37][72]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_34 Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)] +'SFP_GEN[37].rx_data_ngccm_reg[37][72]/C JFDCEXhzr> Jclock pessimismXh>\>@ Jclock uncertaintyXhu )%SFP_GEN[37].rx_data_ngccm_reg[37][72]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXh.A; J arrival timeXhE/ JXh4 JslackXh:l@L( !gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!)y@1y @9Ay@Iy @e}@hq} = vv?00: rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuv>>}e9=|??=([=5^=>? >$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__37/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__37/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzrj<= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;_?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXh( g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhe; J arrival timeXhE?/ JXh4 JslackXh=<+'SFP_GEN[38].rx_data_ngccm_reg[38][64]/C0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[64]/D""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu>}(휿Ig=|??=?~/=9H=>S? >$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)x +'SFP_GEN[38].rx_data_ngccm_reg[38][64]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[83]_0[56] Jnet (fo=1, routed)Xh+=_ 1-SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[64]_i_1/I1 JXhzr 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[64]_i_1/OProp_C6LUT_SLICEM_I1_O JLUT3XhzrT=u 2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[64]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[64]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xha?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][64]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[64]/C JFDCEXhzr> Jclock pessimismXh?~/x .*SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[64]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh(; J arrival timeXh?/ JXh4 JslackXh=Hg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuT>}^Ҍ㥛Q=@5~?㥛?{='=5/%={=>J ? >I "?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_EFF2_SLICEM_C_Q JFDCEXhzrD= jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[1] Jnet (fo=2, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[20]_i_2__37/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[20]_i_2__37/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzru< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh`?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh'1?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXh5/ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh^Ҍ; J arrival timeXhJ ?/ JXh4 JslackXh{='=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C+'SFP_GEN[38].rx_data_ngccm_reg[38][70]/D""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuw>}yǍsW=??^)=`v/D==> ? >$?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_HFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[38][70] Jnet (fo=1, routed)Xh=] +'SFP_GEN[38].rx_data_ngccm_reg[38][70]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhMb?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)XhL7?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][70]/C JFDCEXhzr> Jclock pessimismXh`v/t )%SFP_GEN[38].rx_data_ngccm_reg[38][70]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhyǍ; J arrival timeXhp?/ JXh4 JslackXh^)=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuǡE>}e9=|??0=(=-=>? >$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__37/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__37/OProp_D5LUT_SLICEM_I2_O JLUT3Xhzrxi= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[9] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhe;_?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr> Jclock pessimismXh( g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]Hold_DFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhe; J arrival timeXh+?/ JXh4 JslackXh0=r0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/CB>SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu/>}Ԙd=Iz?Ԙ?9B2=D=l=>p> >j?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)~ 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= EASFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[5] Jnet (fo=1, routed)Xhl=t B>SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/]?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> JFSFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`?X1Y7 (CLOCK_ROOT)t B>SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C JFDREXhzr> Jclock pessimismXh @}u^M=z?u?W2= =1=>> >n?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)x +'SFP_GEN[38].rx_data_ngccm_reg[38][38]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[83]_0[30] Jnet (fo=1, routed)Xhrh=_ 1-SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[38]_i_1/I1 JXhzr 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[38]_i_1/OProp_G5LUT_SLICEM_I1_O JLUT3Xhzr=u 2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40[38]_i_1_n_0 Jnet (fo=1, routed)XhT<b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[3].gbtbank_n_44 Jnet (fo=674, routed)Xh\?X1Y7 (CLOCK_ROOT)] +'SFP_GEN[38].rx_data_ngccm_reg[38][38]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr> Jclock pessimismXhy .*SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]Hold_GFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhp?/ JXh4 JslackXhW2=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuD>}yXZd="{?Zd?9===>> >8!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_9_in Jnet (fo=2, routed)Xh ף= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__37/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__37/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzr@= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[5] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp]?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Hold_HFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhyX; J arrival timeXh$?/ JXh4 JslackXh9=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu/>} ̜W= ?̜?9=n/=`P=>? >Z$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_21_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__37/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__37/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr/]= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[11] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\b?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhX?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr> Jclock pessimismXhn/ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[11]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXh ד?/ JXh4 JslackXh9=r0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/CB>SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/D""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu&1>}Ԙd=Iz?Ԙ?Ts:=D=>>p> >j?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR)~ 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrD= EASFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[7] Jnet (fo=3, routed)Xh>t B>SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/]?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> JFSFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`?X1Y7 (CLOCK_ROOT)t B>SFP_GEN[38].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[38]/C JFDREXhzr> Jclock pessimismXh @̼?h%@ffF?-?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh+? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzrj= plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37_n_0 Jnet (fo=1, routed)Xhʡ= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37/OProp_F6LUT_SLICEM_I5_O JLUT6XhzrGa= plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh(1?X1Y7 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh1+A; J arrival timeXh/ JXh4 JslackXh}@ `!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu@}A1+A( MT-@(@A=А=}@N>̼?h%@ffF?-?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh+? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhS> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzrj= plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_7__37_n_0 Jnet (fo=1, routed)Xhʡ= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37/OProp_F6LUT_SLICEM_I5_O JLUT6XhzrGa= plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state[1]_i_1__37_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh(1?X1Y7 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh1+A; J arrival timeXh/ JXh4 JslackXh}@ ng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuO@}A#,Af=T-@@A=А=@bhN>K7?@ffF?-?n2?_?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh+? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh~j> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh?5> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhbhN>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh#,A; J arrival timeXhA/ JXh4 JslackXh@ ng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuO@}A#,Af=T-@@A=А=@bhN>K7?@ffF?-?n2?_?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh+? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh~j> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh?5> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhbhN>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh#,A; J arrival timeXhA/ JXh4 JslackXh@ ng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuO@}A#,Af=T-@@A=А=@bhN>K7?@ffF?-?n2?_?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh+? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh~j> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh?5> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhbhN>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_AFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh#,A; J arrival timeXhA/ JXh4 JslackXh@ mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuK7@}A',Af=T-@@A=А=B%@bhN>K7?@ffF?-?n2?_?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh+? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh~j> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhbhN>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh',A; J arrival timeXh(/ JXh4 JslackXhB%@ mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuK7@}A',Af=T-@@A=А=B%@bhN>K7?@ffF?-?n2?_?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh+? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh~j> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhbhN>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh',A; J arrival timeXh(/ JXh4 JslackXhB%@ mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuK7@}A',Af=T-@@A=А=B%@bhN>K7?@ffF?-?n2?_?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh+? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh~j> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhbhN>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_AFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh',A; J arrival timeXh(/ JXh4 JslackXhB%@ mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu.݀@}A,Aa?T-@@A=А=f@mN>K7?@ffF?-?n2?֣?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh+? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh~j> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__38/OProp_E6LUT_SLICEM_I3_O JLUT5Xhzr"y> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh= > tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh"?X1Y7 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhmN>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXhf@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuZ|@}A,A@T-@@A=А=@>pN>A`?!@ffF?-?n2??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh+? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__37/OProp_C6LUT_SLICEM_I3_O JLUT4Xhzf"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh)> |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__38/I0 JXhzf {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_1__38/OProp_A6LUT_SLICEM_I0_O JLUT6XhzrE= b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/consecCorrectHeaders0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/CLK Jnet (fo=674, routed)Xh^?X1Y7 (CLOCK_ROOT) wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh>pN>@ Jclock uncertaintyXh uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[3]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXh@ ( !gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!)y@1y @9Ay@Iy @e DK@hq} = tv?11 rise - rise rise - rise  v0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[34]/CB>SFP_GEN[39].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuz>}_yd=??=FD==V>/?+?}?U?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)~ 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[34]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= EASFP_GEN[39].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[5] Jnet (fo=1, routed)Xh=t B>SFP_GEN[39].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> JFSFP_GEN[39].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5?X1Y6 (CLOCK_ROOT)t B>SFP_GEN[39].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[34]/C JFDREXhzr> Jclock pessimismXhF @}]3ףŴ=-?ף?=T==V> ?+?433?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh{= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__38/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__38/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzro= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_HFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh]3; J arrival timeXhx?/ JXh4 JslackXh=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C+'SFP_GEN[39].rx_data_ngccm_reg[39][83]/D"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu-2>}Wİ=t?İ?_T = D=%>V>"?+?t3?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/QProp_GFF_SLICEM_C_Q JFDREXhzrD=V rx_data[39][83] Jnet (fo=1, routed)Xh%>] +'SFP_GEN[39].rx_data_ngccm_reg[39][83]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)XhO?X1Y6 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][83]/C JFDCEXhzr> Jclock pessimismXh s )%SFP_GEN[39].rx_data_ngccm_reg[39][83]Hold_FFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhW; J arrival timeXh_?/ JXh4 JslackXh_T =g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C+'SFP_GEN[39].rx_data_ngccm_reg[39][66]/D"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu #>}%RV`=?R?S=ZD=A`=V>?+?*\/?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_BFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[39][66] Jnet (fo=1, routed)XhA`=] +'SFP_GEN[39].rx_data_ngccm_reg[39][66]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhk?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)XhC?X1Y6 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][66]/C JFDCEXhzr> Jclock pessimismXhZt )%SFP_GEN[39].rx_data_ngccm_reg[39][66]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh%; J arrival timeXhc?/ JXh4 JslackXhS=8g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsut>}%D=F?%?9#=C9o= ף=V>43?+?3?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/O85[0] Jnet (fo=2, routed)XhC= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__38/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__38/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzru< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[0] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/݄?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhi?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXhC9 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh$?/ JXh4 JslackXh9#=@+'SFP_GEN[39].rx_data_ngccm_reg[39][77]/C0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[76]/D"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuX9>}P6ףfu=S?ף?P)=I=-=V>n?+?433?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)x +'SFP_GEN[39].rx_data_ngccm_reg[39][77]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H=w 40SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[83]_0[69] Jnet (fo=1, routed)Xh=_ 1-SFP_GEN[39].ngCCM_gbt/RX_Word_rx40[76]_i_1/I0 JXhzr 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40[76]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT3XhzrQ8=u 2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40[76]_i_1_n_0 Jnet (fo=1, routed)XhA`e<b 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[76]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhz?X1Y6 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][77]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[76]/C JFDCEXhzr> Jclock pessimismXhIx .*SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[76]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhP6; J arrival timeXh~?/ JXh4 JslackXhP)=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu]B>}=-??<-=!= =V> ?+?2?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__38/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__38/OProp_C5LUT_SLICEL_I2_O JLUT3XhzrGa= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] Jnet (fo=1, routed)XhX94< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr> Jclock pessimismXh! g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh~?/ JXh4 JslackXh<-=gsog_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/Ceag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/D"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuQ8>}bٮBϦ=ʑ?ٮ?H.=  ף==V>*\?+?/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) sog_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/QProp_BFF_SLICEL_C_Q JFDCEXhzf9H= qmg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2] Jnet (fo=27, routed)Xh1= jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[28]_i_1__46/I1 JXhzf ieg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[28]_i_1__46/OProp_D6LUT_SLICEM_I1_O JLUT5Xhzr< `\g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg00[28] Jnet (fo=1, routed)Xho< eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y6 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZd?X1Y6 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/C JFDCEXhzr> Jclock pessimismXh  c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhb; J arrival timeXhԨ?/ JXh4 JslackXhH.=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsut>}>`oi5=rh?`?K 3=N=L=V>.?+?FS?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__38/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__38/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out_0[4] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXhN g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh>; J arrival timeXh ׳?/ JXh4 JslackXhK 3=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C+'SFP_GEN[39].rx_data_ngccm_reg[39][76]/D"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsun>}ꟿ%1w-=S?%?6=3B9H==V>n?+?3?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_FFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[39][76] Jnet (fo=1, routed)Xh=] +'SFP_GEN[39].rx_data_ngccm_reg[39][76]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhz?X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_54 Jnet (fo=674, routed)Xhi?X1Y6 (CLOCK_ROOT)] +'SFP_GEN[39].rx_data_ngccm_reg[39][76]/C JFDCEXhzr> Jclock pessimismXh3Bt )%SFP_GEN[39].rx_data_ngccm_reg[39][76]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhꟿ; J arrival timeXhˡ?/ JXh4 JslackXh6=!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuJ @}Aa2A-F彵B@-@A=А= DK@Zb>O?pM@5^?/?l{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh( @ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__38/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__38/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__38/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__38/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr֣p> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__38_n_0 Jnet (fo=1, routed)Xhw= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__38/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__38/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__38_n_0 Jnet (fo=2, routed)Xh/? kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh'@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhp@X1Y6 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhZb>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXha2A; J arrival timeXht/ JXh4 JslackXh DK@ !g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuJ @}Aa2A-F彵B@-@A=А= DK@Zb>O?pM@5^?/?l{??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)Xh( @ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__38/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__38/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzr"y> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__38/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__38/OProp_C6LUT_SLICEL_I2_O JLUT4Xhzr֣p> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_7__38_n_0 Jnet (fo=1, routed)Xhw= okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__38/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__38/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state[1]_i_1__38_n_0 Jnet (fo=2, routed)Xh/? kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh'@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhp@X1Y6 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhZb>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXha2A; J arrival timeXht/ JXh4 JslackXh DK@ }D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/CE"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuv@}AG7A?Y>ʡE@?@A=А=َZ@\|j>>@5^?~?l{??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)XhQ@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/CE JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)Xhn*@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh<'@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C JFDREXhzr> Jclock pessimismXh\|j>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[2]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhG7A; J arrival timeXhף/ JXh4 JslackXhَZ@}D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuv@}AG7A?Y>ʡE@?@A=А=َZ@\|j>>@5^?~?l{??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)XhQ@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/CE JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)Xhn*@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh<'@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr> Jclock pessimismXh\|j>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]Setup_CFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhG7A; J arrival timeXhף/ JXh4 JslackXhَZ@|D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/CE"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuV@}AK7A?Y>ʡE@?@A=А=Z@\|j>>8@5^?~?l{??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xhb@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/CE JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)Xhn*@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh<'@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr> Jclock pessimismXh\|j>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhK7A; J arrival timeXht/ JXh4 JslackXhZ@|D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/CE"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuV@}AK7A?Y>ʡE@?@A=А=Z@\|j>>8@5^?~?l{??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xhb@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/CE JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)Xhn*@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh<'@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh\|j>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhK7A; J arrival timeXht/ JXh4 JslackXhZ@}D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuP@}AG7A @l>ʡE@ @@A=А= b@\|j>>@5^?~?l{? -?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/CE JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)Xhn*@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhb(@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr> Jclock pessimismXh\|j>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[3]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXhG7A; J arrival timeXh6/ JXh4 JslackXh b@}D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuP@}AG7A @l>ʡE@ @@A=А= b@\|j>>@5^?~?l{? -?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xh@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/CE JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)Xhn*@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhb(@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr> Jclock pessimismXh\|j>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]Setup_GFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXhG7A; J arrival timeXh6/ JXh4 JslackXh b@|D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/CE"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu@}AS7A @l>ʡE@ @@A=А=nb@\|j>>ҍ@5^?~?l{? -?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xhף@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/CE JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)Xhn*@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhb(@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh\|j>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhS7A; J arrival timeXhp/ JXh4 JslackXhnb@|D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/CE"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu@}AS7A @l>ʡE@ @@A=А=nb@\|j>>ҍ@5^?~?l{? -?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> lhg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/ERROR_DETECT_O_reg[0] Jnet (fo=137, routed)Xh @ okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/I1 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/RX_DATA_O[20]_i_1__38/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O0 Jnet (fo=76, routed)Xhף@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/CE JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)Xhn*@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhb(@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C JFDREXhzr> Jclock pessimismXh\|j>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhS7A; J arrival timeXhp/ JXh4 JslackXhnb@( !gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!)y@1y @9Ay@Iy @e]N@hq} ǔ= vv?227 rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu|.>}`lV{.=w?V?ǔ=( ʡ=5^=>S#? >lG?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)Xh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__39/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__39/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzr< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhH?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh(  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh`l; J arrival timeXh?/ JXh4 JslackXhǔ=5g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuw>}㽞<߯tv=;ߏ?<߯?x=bB%= =>#? >~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/O84[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__39/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[19]_i_1__39/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzru< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[0] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh%?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]/C JFDREXhzr> Jclock pessimismXhbB g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[19]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh㽞; J arrival timeXh?/ JXh4 JslackXhx=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuC>}<߯=|?<߯?= = = =>"? >~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/QProp_GFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_17_in Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__39/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__39/OProp_D5LUT_SLICEM_I0_O JLUT3Xhzrxi= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[9] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr> Jclock pessimismXh  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[9]Hold_DFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh=<,(SFP_GEN[40].ngCCM_gbt/pwr_good_pre_reg/C,(SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu/>}n=|??"=,/@=`P=>"? >9H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR)y ,(SFP_GEN[40].ngCCM_gbt/pwr_good_pre_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=i &"SFP_GEN[40].ngCCM_gbt/pwr_good_pre Jnet (fo=1, routed)Xh)\=_ 1-SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_i_1__12/I1 JXhzr 0,SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_i_1__12/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr/]=u 2.SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_i_1__12_n_0 Jnet (fo=1, routed)Xho<^ ,(SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhף?X1Y8 (CLOCK_ROOT)^ ,(SFP_GEN[40].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)^ ,(SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_reg/C JFDREXhzr> Jclock pessimismXh,/@t *&SFP_GEN[40].ngCCM_gbt/pwr_good_cnt_regHold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh33?/ JXh4 JslackXh"=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuC>}==|??t'= =-=>"? >I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/QProp_GFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_17_in Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__39/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__39/OProp_G5LUT_SLICEM_I2_O JLUT3XhzrA`e= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[7] Jnet (fo=1, routed)XhT< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhף?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh(?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr> Jclock pessimismXh  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]Hold_GFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXht'=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu^d;>}ekVC=)\?V?+= =E=>\"? >lG?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/QProp_GFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_5_in Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__39/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__39/OProp_B6LUT_SLICEM_I2_O JLUT3Xhzrj<= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[1] Jnet (fo=1, routed)Xhu< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhH?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr> Jclock pessimismXh  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhek; J arrival timeXhȦ?/ JXh4 JslackXh+=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C+'SFP_GEN[40].rx_data_ngccm_reg[40][53]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsut>}ٮ8=Đ?ٮ?3=jB9H=[=>A`%? >rH?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[40][53] Jnet (fo=1, routed)Xh[=] +'SFP_GEN[40].rx_data_ngccm_reg[40][53]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_64 Jnet (fo=674, routed)XhZd?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[40].rx_data_ngccm_reg[40][53]/C JFDCEXhzr> Jclock pessimismXhjBt )%SFP_GEN[40].rx_data_ngccm_reg[40][53]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh; J arrival timeXh33?/ JXh4 JslackXh3=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C+'SFP_GEN[40].rx_data_ngccm_reg[40][27]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu@>}*vh=?v?3= D=*\>>J "? >G?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[40][27] Jnet (fo=1, routed)Xh*\>] +'SFP_GEN[40].rx_data_ngccm_reg[40][27]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhA?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_64 Jnet (fo=674, routed)Xh ?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[40].rx_data_ngccm_reg[40][27]/C JFDCEXhzr> Jclock pessimismXh s )%SFP_GEN[40].rx_data_ngccm_reg[40][27]Hold_EFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh*; J arrival timeXh+?/ JXh4 JslackXh3= xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_reg/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsun>}񛿍?5&?)=|??5?;=rK=9H=>"? >+G?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/QProp_EFF_SLICEM_C_Q JFDPEXhzr9H= {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg_n_0_[0] Jnet (fo=5, routed)XhP= b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_i_1__39/I1 JXhzr a]g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_i_1__39/OProp_A6LUT_SLICEM_I1_O JLUT3XhzrQ8= c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_i_1__39_n_0 Jnet (fo=1, routed)XhD< ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/CLK Jnet (fo=674, routed)Xhף?X1Y8 (CLOCK_ROOT) xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXhrK [Wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].rxBitSlipControl/READY_o_regHold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh񛿐; J arrival timeXhʡ?/ JXh4 JslackXh;=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C+'SFP_GEN[40].rx_data_ngccm_reg[40][48]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuG>}< = ? ?f:;=x 9H=>>$? > K?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=V rx_data[40][48] Jnet (fo=1, routed)Xh>] +'SFP_GEN[40].rx_data_ngccm_reg[40][48]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhG?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_64 Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[40].rx_data_ngccm_reg[40][48]/C JFDCEXhzr> Jclock pessimismXhx t )%SFP_GEN[40].rx_data_ngccm_reg[40][48]Hold_AFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh<; J arrival timeXh?/ JXh4 JslackXhf:;=`!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuc@}AN=1A$)@=v.@$)@A=А=]N@m~U>&1?2\@ffF?S?n2?9?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh"@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_C6LUT_SLICEL_I0_O JLUT4XhzrA`> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhbX> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39_n_0 Jnet (fo=1, routed)Xh-2> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39_n_0 Jnet (fo=2, routed)Xh\? kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[0]Setup_BFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhN=1A; J arrival timeXhK/ JXh4 JslackXh]N@ `!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuc@}AN=1A$)@=v.@$)@A=А=]N@m~U>&1?2\@ffF?S?n2?9?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh"@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_C6LUT_SLICEL_I0_O JLUT4XhzrA`> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhbX> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrFs> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_7__39_n_0 Jnet (fo=1, routed)Xh-2> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state[1]_i_1__39_n_0 Jnet (fo=2, routed)Xh\? kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/FSM_sequential_state_reg[1]Setup_DFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhN=1A; J arrival timeXhK/ JXh4 JslackXh]N@ ng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu%@}A0A'=v.@'@A=А=Sj@m~U>gf?F@ffF?S?n2?E?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh"@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_C6LUT_SLICEL_I0_O JLUT4XhzrA`> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhM> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGz> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh#۹> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xhw@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh0A; J arrival timeXhA/ JXh4 JslackXhSj@ mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu@}Ac0A'=v.@'@A=А=[k@m~U>gf?F@ffF?S?n2?E?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh"@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_C6LUT_SLICEL_I0_O JLUT4XhzrA`> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhM> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGz> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhQ> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xhw@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhc0A; J arrival timeXh(/ JXh4 JslackXh[k@ ng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu.ݔ@}A0A'~=v.@'@A=А=,k@m~U>gf?,F@ffF?S?n2?+?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh"@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_C6LUT_SLICEL_I0_O JLUT4XhzrA`> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhM> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGz> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhK> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xh;@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh,k@ mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuĔ@}A0A'~=v.@'@A=А=k@m~U>gf?VF@ffF?S?n2?+?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh"@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_C6LUT_SLICEL_I0_O JLUT4XhzrA`> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhM> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGz> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhµ> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xh;@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhk@ mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuĔ@}A0A'~=v.@'@A=А=k@m~U>gf?VF@ffF?S?n2?+?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh"@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_C6LUT_SLICEL_I0_O JLUT4XhzrA`> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhM> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__40/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGz> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhµ> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xh;@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhk@ |g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsul@}A1A(%=v.@(@A=А=,n@m~U>I?I@ffF?S?n2?'1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh"@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_C6LUT_SLICEL_I0_O JLUT4XhzrA`> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv= zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__40/I5 JXhzr yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__40/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh ? vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xh:@X1Y8 (CLOCK_ROOT) uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh1A; J arrival timeXh"/ JXh4 JslackXh,n@ {g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuΓ@}A(1A(%=v.@(@A=А=֎n@m~U>I?xI@ffF?S?n2?'1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh"@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_C6LUT_SLICEL_I0_O JLUT4XhzrA`> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv= zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__40/I5 JXhzr yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__40/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xho? vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xh:@X1Y8 (CLOCK_ROOT) uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh(1A; J arrival timeXh> / JXh4 JslackXh֎n@ {g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuΓ@}A(1A(%=v.@(@A=А=֎n@m~U>I?xI@ffF?S?n2?'1?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xh"@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__39/OProp_C6LUT_SLICEL_I0_O JLUT4XhzrA`> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xhv= zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__40/I5 JXhzr yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__40/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xho? vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/CLK Jnet (fo=674, routed)Xh:@X1Y8 (CLOCK_ROOT) uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhm~U>@ Jclock uncertaintyXh sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh(1A; J arrival timeXh> / JXh4 JslackXh֎n@ ( !gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!)y@1y @9Ay@Iy @e}@hq} b= tv?33 rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C+'SFP_GEN[41].rx_data_ngccm_reg[41][46]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu5,>}0~=j|?~?b=?D==j>?/>|?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_CFF_SLICEL_C_Q JFDREXhzrD=V rx_data[41][46] Jnet (fo=1, routed)Xh=] +'SFP_GEN[41].rx_data_ngccm_reg[41][46]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhR^?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_74 Jnet (fo=674, routed)Xh= ?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[41].rx_data_ngccm_reg[41][46]/C JFDCEXhzr> Jclock pessimismXh?s )%SFP_GEN[41].rx_data_ngccm_reg[41][46]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh0; J arrival timeXhG?/ JXh4 JslackXhb=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C+'SFP_GEN[41].rx_data_ngccm_reg[41][37]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuxh>}R\j9[N=|?j?v=o19H=v=j>?/>S#?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[41][37] Jnet (fo=1, routed)Xhv=] +'SFP_GEN[41].rx_data_ngccm_reg[41][37]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_74 Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[41].rx_data_ngccm_reg[41][37]/C JFDCEXhzr> Jclock pessimismXho1t )%SFP_GEN[41].rx_data_ngccm_reg[41][37]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhR\; J arrival timeXh?/ JXh4 JslackXhv=_[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[0]/C]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuC>}󝿭=|??/=e[==j>?/>gf&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[0]/QProp_AFF2_SLICEL_C_Q JFDCEXhzf9H= YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress[0] Jnet (fo=9, routed)XhT= b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_i_1__40/I5 JXhzf a]g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_i_1__40/OProp_B6LUT_SLICEM_I5_O JLUT6Xhzrj<= WSg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd Jnet (fo=1, routed)Xhu< ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xha?X1Y8 (CLOCK_ROOT) _[g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/psAddress_reg[0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh~?X1Y8 (CLOCK_ROOT) ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_reg/C JFDCEXhzr> Jclock pessimismXhe [Wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/bitSlipCmd_regHold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh'1?/ JXh4 JslackXh/= .*SFP_GEN[41].ngCCM_gbt/RX_Clock_40MHz_reg/C<8SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuv>>}DZd={?Zd?P1= ף==j>|>/>G!?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR)| .*SFP_GEN[41].ngCCM_gbt/RX_Clock_40MHz_reg/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H=~ :6SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/RX_Clock_40MHz Jnet (fo=14, routed)XhQ=o A=SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_i_1__15/I2 JXhzr @SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_i_1__15_n_0 Jnet (fo=1, routed)Xho<n <8SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh]?X1Y8 (CLOCK_ROOT)` .*SFP_GEN[41].ngCCM_gbt/RX_Clock_40MHz_reg/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> JFSFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)n <8SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/C JFDREXhzr> Jclock pessimismXh :6SFP_GEN[41].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_regHold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhD; J arrival timeXhˡ?/ JXh4 JslackXhP1=4g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsun>}G5?)={??;=<=9H=j>|>/>x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/O84[1] Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__40/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__40/OProp_A6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/I8[1] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh]?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh+?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXh< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhG; J arrival timeXh ?/ JXh4 JslackXh;=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsut>}HᚿY,=l{?H?ay;=5.<=L=j>?/>A ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_11_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__40/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[4]_i_1__40/OProp_C6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[4] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5^?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhl?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr> Jclock pessimismXh5.< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhNb?/ JXh4 JslackXhay;=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsut>}DJ,=~?D?y;=\4==L=j>o?/>#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)XhC = g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__40/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__40/OProp_D6LUT_SLICEL_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhGa?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXh\4= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhy;=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C+'SFP_GEN[41].rx_data_ngccm_reg[41][76]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsun>}('~ !=l{?~?1LC=<9H==j>?/>|?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[41][76] Jnet (fo=1, routed)Xh=] +'SFP_GEN[41].rx_data_ngccm_reg[41][76]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5^?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_74 Jnet (fo=674, routed)Xh= ?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[41].rx_data_ngccm_reg[41][76]/C JFDCEXhzr> Jclock pessimismXh<t )%SFP_GEN[41].rx_data_ngccm_reg[41][76]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh('; J arrival timeXhA?/ JXh4 JslackXh1LC=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuz>}#ыI?)=S~?I?NLC===`P=j>?/>o#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in Jnet (fo=2, routed)Xh)\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__40/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__40/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh&a?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhԈ?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C JFDREXhzr> Jclock pessimismXh= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[12]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh#ы; J arrival timeXh?/ JXh4 JslackXhNLC=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[41].rx_data_ngccm_reg[41][39]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuS>}R\j9[N=|?j?%G=o19H==j>?/>S#?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=V rx_data[41][39] Jnet (fo=1, routed)Xh=] +'SFP_GEN[41].rx_data_ngccm_reg[41][39]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xha?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_74 Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[41].rx_data_ngccm_reg[41][39]/C JFDCEXhzr> Jclock pessimismXho1s )%SFP_GEN[41].rx_data_ngccm_reg[41][39]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhR\; J arrival timeXh?/ JXh4 JslackXh%G=g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[41].rx_data_ngccm_reg[41][55]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu{@}A+AZnV6@Z@A=А=}@N>Q>Cd@ʡE?t?sh1?;ߟ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[41].rx_data_ngccm[41][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[41].rx_data_ngccm[41][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[41] Jnet (fo=76, routed)Xh&?^ ,(SFP_GEN[41].rx_data_ngccm_reg[41][55]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_74 Jnet (fo=674, routed)Xht?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[41].rx_data_ngccm_reg[41][55]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXhu )%SFP_GEN[41].rx_data_ngccm_reg[41][55]Setup_AFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh}@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[41].rx_data_ngccm_reg[41][59]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu%y@}AL,A)]V6@@A=А=@N>Q>a@ʡE?t?sh1?&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[41].rx_data_ngccm[41][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[41].rx_data_ngccm[41][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[41] Jnet (fo=76, routed)Xh1?^ ,(SFP_GEN[41].rx_data_ngccm_reg[41][59]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_74 Jnet (fo=674, routed)Xh"?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[41].rx_data_ngccm_reg[41][59]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXhv )%SFP_GEN[41].rx_data_ngccm_reg[41][59]Setup_AFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhL,A; J arrival timeXh/ JXh4 JslackXh@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[41].rx_data_ngccm_reg[41][57]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsux@}Ad ,A)]V6@@A=А=w@N>Q>^a@ʡE?t?sh1?&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[41].rx_data_ngccm[41][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[41].rx_data_ngccm[41][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[41] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[41].rx_data_ngccm_reg[41][57]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_74 Jnet (fo=674, routed)Xh"?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[41].rx_data_ngccm_reg[41][57]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXhu )%SFP_GEN[41].rx_data_ngccm_reg[41][57]Setup_AFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhd ,A; J arrival timeXhP/ JXh4 JslackXhw@Lng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}AЀ,A+,@+@A=А= @MTO>\?q="@ʡE? ?sh1?X9?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I1 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr/> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhT> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGz> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh ? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhx@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhMTO>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_CFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhЀ,A; J arrival timeXh/ JXh4 JslackXh @ ng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A߄,A,@@A=А= @QO>\?I "@ʡE? ?sh1?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I1 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr/> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhT> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGz> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhd;? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhx@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)XhU?X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhQO>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_AFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh߄,A; J arrival timeXh/ JXh4 JslackXh @ ng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A߄,A,@@A=А= @QO>\?I "@ʡE? ?sh1?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I1 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr/> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhT> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGz> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhd;? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhx@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)XhU?X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhQO>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_BFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh߄,A; J arrival timeXh/ JXh4 JslackXh @ mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A,A+,@+@A=А= @MTO>\?I "@ʡE? ?sh1?X9?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I1 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr/> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhT> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGz> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhd;? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhx@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhMTO>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXh @ mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A,A+,@+@A=А= @MTO>\?I "@ʡE? ?sh1?X9?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I1 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr/> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhT> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGz> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhd;? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhx@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhMTO>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXh @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[41].rx_data_ngccm_reg[41][83]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuVv@}A̶+A탮V6@@A=А=@lO>Q>K_@ʡE?t?sh1?V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh @ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[41].rx_data_ngccm[41][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/SFP_GEN[41].rx_data_ngccm[41][83]_i_1/OProp_F6LUT_SLICEL_I0_O JLUT6XhzrMb>Y rx_data_ngccm[41] Jnet (fo=76, routed)Xh罹?^ ,(SFP_GEN[41].rx_data_ngccm_reg[41][83]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_74 Jnet (fo=674, routed)Xh= ?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[41].rx_data_ngccm_reg[41][83]/C JFDCEXhzr> Jclock pessimismXhlO>@ Jclock uncertaintyXhv )%SFP_GEN[41].rx_data_ngccm_reg[41][83]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh̶+A; J arrival timeXhV/ JXh4 JslackXh@Lmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu7@}A,A,@@A=А=2@QO>\?!@ʡE? ?sh1?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][0] Jnet (fo=10, routed)Xh#? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/I1 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__40/OProp_D6LUT_SLICEM_I1_O JLUT4Xhzr/> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhT> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__41/OProp_F6LUT_SLICEM_I3_O JLUT5XhzrGz> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh@5? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhx@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/CLK Jnet (fo=674, routed)XhU?X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhQO>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_AFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh,A; J arrival timeXh;/ JXh4 JslackXh2@ ( !gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!)y@1y @9Ay@Iy @e&1@hq} q = uv?44  rise - rise rise - rise  F+'SFP_GEN[42].rx_data_ngccm_reg[42][56]/C0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[56]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuX94>}Zף=&?ף?q =# ף==%>$?>H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR)x +'SFP_GEN[42].rx_data_ngccm_reg[42][56]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H=u 2.g_gbt_bank[3].gbtbank/RX_Word_rx40_reg[78][32] Jnet (fo=1, routed)XhT=b 40g_gbt_bank[3].gbtbank/RX_Word_rx40[56]_i_1__8/I1 JXhzr 3/g_gbt_bank[3].gbtbank/RX_Word_rx40[56]_i_1__8/OProp_B6LUT_SLICEM_I1_O JLUT3Xhzr<w 40SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[83]_0[32] Jnet (fo=1, routed)Xhu<b 0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[56]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[3].gbtbank_n_84 Jnet (fo=674, routed)XhM?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[42].rx_data_ngccm_reg[42][56]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[56]/C JFDCEXhzr> Jclock pessimismXh#x .*SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[56]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhZ; J arrival timeXh?/ JXh4 JslackXhq =w0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[74]/CB>SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu}&>}H-x=%??fU=-#D==%> #?>1D?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR)~ 0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[74]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= FBSFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]_0[25] Jnet (fo=6, routed)Xh=t B>SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[74]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> JFSFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh"?X1Y8 (CLOCK_ROOT)t B>SFP_GEN[42].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/C JFDREXhzr> Jclock pessimismXh-# @}X4=R??c0=ƓDD=[=%>d;?>8A?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[25]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[25] Jnet (fo=1, routed)Xh[= eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[25]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[25]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[25]/C JFDCEXhzr> Jclock pessimismXhƓD c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[25]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh%?/ JXh4 JslackXhc0=&eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]/Ceag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[33]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsun>}X4=R??c0=ƓD9H==%>d;?>8A?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0[33] Jnet (fo=1, routed)Xh= eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[33]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[33]/C JFDCEXhzr> Jclock pessimismXhƓD c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[33]Hold_BFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh%?/ JXh4 JslackXhc0=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuF>}t=)\??W0=n#==%> ?>G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in Jnet (fo=2, routed)Xh1= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__41/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__41/OProp_C6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhD?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXhn# g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXht; J arrival timeXh'1?/ JXh4 JslackXhW0=D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CD@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu]B>}ٮC=َ?ٮ?4=#==%>|?>B`E?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].cnt_reg[6][0]_0[0] Jnet (fo=1, routed)Xhw= {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].rx_clken_sr[6][1]_i_1__2/I0 JXhzr zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gbtBank_Clk_gen[6].rx_clken_sr[6][1]_i_1__2/OProp_H6LUT_SLICEM_I0_O JLUT2Xhzr@=m *&g_gbt_bank[3].gbtbank/i_gbt_bank_n_319 Jnet (fo=1, routed)Xho<v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)XhZd?X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/C JFDCEXhzr> Jclock pessimismXh# B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]Hold_HFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh+?/ JXh4 JslackXh4=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu)>}$z<߯oi5=ף?<߯?R?=ʀL=Y=%>o#?>lG?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)XhP= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__41/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__41/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhʁ?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXhʀL g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh$z; J arrival timeXht?/ JXh4 JslackXhR?=F+'SFP_GEN[42].rx_data_ngccm_reg[42][65]/C0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[64]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu>}ឿ oM=G? ?cr?=XQC=T=%>Z$?>G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR)x +'SFP_GEN[42].rx_data_ngccm_reg[42][65]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=u 2.g_gbt_bank[3].gbtbank/RX_Word_rx40_reg[78][41] Jnet (fo=1, routed)Xht=b 40g_gbt_bank[3].gbtbank/RX_Word_rx40[64]_i_1__8/I0 JXhzr 3/g_gbt_bank[3].gbtbank/RX_Word_rx40[64]_i_1__8/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrT=w 40SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[83]_0[36] Jnet (fo=1, routed)Xho<b 0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[64]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[3].gbtbank_n_84 Jnet (fo=674, routed)Xhn?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[42].rx_data_ngccm_reg[42][65]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[42].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[64]/C JFDCEXhzr> Jclock pessimismXhXQCx .*SFP_GEN[42].ngCCM_gbt/RX_Word_rx40_reg[64]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhឿ; J arrival timeXh/ݤ?/ JXh4 JslackXhcr?=wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/Cwsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsui;=}Ȗ֣;??D=~jo=Q8=%>x?>8A?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg_n_0_[4] Jnet (fo=2, routed)Xh+= |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__42/I5 JXhzr {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__42/OProp_A6LUT_SLICEM_I5_O JLUT6Xhzru< }yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders[4]_i_2__42_n_0 Jnet (fo=1, routed)XhD< wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y8 (CLOCK_ROOT) wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhx?X1Y8 (CLOCK_ROOT) wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh~j uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecCorrectHeaders_reg[4]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhȖ; J arrival timeXh?/ JXh4 JslackXhD=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C+'SFP_GEN[42].rx_data_ngccm_reg[42][60]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu~>}$<߯3xQ=a?<߯?!H=pCD=/=%>#?>lG?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[42][60] Jnet (fo=1, routed)Xh/=] +'SFP_GEN[42].rx_data_ngccm_reg[42][60]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhJ ?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_84 Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[42].rx_data_ngccm_reg[42][60]/C JFDCEXhzr> Jclock pessimismXhpCs )%SFP_GEN[42].rx_data_ngccm_reg[42][60]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh$; J arrival timeXh0ݤ?/ JXh4 JslackXh!H=!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuK @}AH51A9(]=e;/@9(@A=А=&1@|Y>?G@CK?n?5?ff?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__41/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__41/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzrj= plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__41_n_0 Jnet (fo=1, routed)Xh +> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__41/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__41/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__41_n_0 Jnet (fo=2, routed)Xhc> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhף@X1Y8 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXh|Y>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXhH51A; J arrival timeXh/ JXh4 JslackXh&1@ !g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu@}AA1A(*v=e;/@(@A=А=1@|Y>?@CK?n?5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__41/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__41/OProp_D6LUT_SLICEM_I2_O JLUT4Xhzrj= plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_7__41_n_0 Jnet (fo=1, routed)Xh +> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__41/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__41/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state[1]_i_1__41_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh|Y>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/FSM_sequential_state_reg[0]Setup_CFF_SLICEL_C_CE JFDCEXh/]/ JXh< J required timeXhA1A; J arrival timeXh/ JXh4 JslackXh1@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu1@}AA1Aa(=e;/@a(@A=А==@|Y>?~@CK?n?5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh+> zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__42/I5 JXhzr yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__42/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr1,> `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh/? vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh|Y>@ Jclock uncertaintyXh sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[1]Setup_BFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhA1A; J arrival timeXh/ JXh4 JslackXh=@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu1@}AA1Aa(=e;/@a(@A=А==@|Y>?~@CK?n?5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh+> zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__42/I5 JXhzr yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__42/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr1,> `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh/? vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh|Y>@ Jclock uncertaintyXh sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[2]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhA1A; J arrival timeXh/ JXh4 JslackXh=@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu@}AE1Aa(=e;/@a(@A=А= =@|Y>?ff~@CK?n?5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh+> zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__42/I5 JXhzr yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders[2]_i_1__42/OProp_G6LUT_SLICEM_I5_O JLUT6Xhzr1,> `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/consecFalseHeaders0 Jnet (fo=3, routed)Xh? vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) uqg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh|Y>@ Jclock uncertaintyXh sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.consecFalseHeaders_reg[0]Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXhE1A; J arrival timeXh/ JXh4 JslackXh =@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsų@}A-1Au(E=e;/@u(@A=А=^C@|Y> ?6y@CK?n?5?$?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh-> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXh|Y>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_DFF2_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh-1A; J arrival timeXh@5/ JXh4 JslackXh^C@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu;@}A011Au(E=e;/@u(@A=А= D@|Y> ?Xy@CK?n?5?$?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh(> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXh|Y>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh011A; J arrival timeXh(/ JXh4 JslackXh D@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu;@}A011Au(E=e;/@u(@A=А= D@|Y> ?Xy@CK?n?5?$?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh(> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXh|Y>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_CFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh011A; J arrival timeXh(/ JXh4 JslackXh D@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuV@}AH51A9(]=e;/@9(@A=А=H@|Y> ?t@CK?n?5?ff?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhE> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhף@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXh|Y>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXhH51A; J arrival timeXh/ JXh4 JslackXhH@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu@}Aa91A(i=e;/@(@A=А=PI@|Y> ?ls@CK?n?5?+?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[2]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[2] J GTHE3_CHANNELXhzr? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][2] Jnet (fo=10, routed)XhzL@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/I3 JXhzr plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__41/OProp_D6LUT_SLICEL_I3_O JLUT4Xhzr> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__42/OProp_G6LUT_SLICEM_I3_O JLUT5Xhzr> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xhף> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh1@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh:@X1Y8 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXh|Y>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_EFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXha91A; J arrival timeXh/ JXh4 JslackXhPI@ ( !gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!)y@1y @9Ay@Iy @eC)*@hq} O = wv?55 rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C*&SFP_GEN[43].rx_data_ngccm_reg[43][1]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsun>}d8"[=-?8?O =D9H==>gf&?G> K?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[43][1] Jnet (fo=1, routed)Xh=\ *&SFP_GEN[43].rx_data_ngccm_reg[43][1]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh|?X1Y8 (CLOCK_ROOT)\ *&SFP_GEN[43].rx_data_ngccm_reg[43][1]/C JFDCEXhzr> Jclock pessimismXhDs ($SFP_GEN[43].rx_data_ngccm_reg[43][1]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhd; J arrival timeXhz?/ JXh4 JslackXhO =F+'SFP_GEN[43].rx_data_ngccm_reg[43][37]/C0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuX->}\ܢ<߯Q=I ?<߯?6=o! ף=E=>$&?G>'1H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR)x +'SFP_GEN[43].rx_data_ngccm_reg[43][37]/QProp_BFF_SLICEL_C_Q JFDCEXhzr9H=w 40g_gbt_bank[3].gbtbank/RX_Word_rx40_reg[78]_0[13] Jnet (fo=1, routed)Xh=b 40g_gbt_bank[3].gbtbank/RX_Word_rx40[36]_i_1__9/I0 JXhzr 3/g_gbt_bank[3].gbtbank/RX_Word_rx40[36]_i_1__9/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr<w 40SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[83]_0[22] Jnet (fo=1, routed)Xho<b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh33?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][37]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXho!x .*SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh\ܢ; J arrival timeXh?/ JXh4 JslackXh6=#eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[37]/Ceag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[37]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuT>}ΞwS=%?w?&%=@9H==>$?G>G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[37]/QProp_FFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[37] Jnet (fo=1, routed)Xh= eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[37]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[37]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhI?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[37]/C JFDCEXhzr> Jclock pessimismXh@ c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[37]Hold_GFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhΞ; J arrival timeXh?/ JXh4 JslackXh&%=%eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[41]/Ceag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[41]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu>}2 7`=%? ?[)=9@D==>$?G>9H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[41]/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= _[g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[41] Jnet (fo=1, routed)Xh= eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[41]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[41]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[41]/C JFDCEXhzr> Jclock pessimismXh9@ c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[41]Hold_DFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh2; J arrival timeXhz?/ JXh4 JslackXh[)=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C+'SFP_GEN[43].rx_data_ngccm_reg[43][64]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuC>}0Mq=I ?M?m)=:!9H=rh>>$&?G>WM?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H=V rx_data[43][64] Jnet (fo=1, routed)Xhrh>] +'SFP_GEN[43].rx_data_ngccm_reg[43][64]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh33?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xhٞ?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][64]/C JFDCEXhzr> Jclock pessimismXh:!t )%SFP_GEN[43].rx_data_ngccm_reg[43][64]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh0; J arrival timeXh~?/ JXh4 JslackXhm)=E+'SFP_GEN[43].rx_data_ngccm_reg[43][32]/C0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[32]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu/>}rʱlg=I ?ʱ?)=D`=T=>$&?G>2L?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR)x +'SFP_GEN[43].rx_data_ngccm_reg[43][32]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=v 3/g_gbt_bank[3].gbtbank/RX_Word_rx40_reg[78]_0[8] Jnet (fo=1, routed)Xht=b 40g_gbt_bank[3].gbtbank/RX_Word_rx40[32]_i_1__9/I1 JXhzr 3/g_gbt_bank[3].gbtbank/RX_Word_rx40[32]_i_1__9/OProp_D6LUT_SLICEL_I1_O JLUT3XhzrY=w 40SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[83]_0[20] Jnet (fo=1, routed)Xho<b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[32]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh33?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][32]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhV?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXhDx .*SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[32]Hold_DFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhr; J arrival timeXh¥?/ JXh4 JslackXh)=$eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[21]/Ceag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[21]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuw>}ҮwbO=&?w?P1=@9H==>Z$?G>G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[21]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= _[g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0[21] Jnet (fo=1, routed)Xh= eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[21]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[21]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhI?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[21]/C JFDCEXhzr> Jclock pessimismXh@ c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[21]Hold_EFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXhҮ; J arrival timeXhX9?/ JXh4 JslackXhP1=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C+'SFP_GEN[43].rx_data_ngccm_reg[43][78]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuϡE>}J {=I ?J ?06=sB!9H=t>>$&?G>CL?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H=V rx_data[43][78] Jnet (fo=1, routed)Xht>] +'SFP_GEN[43].rx_data_ngccm_reg[43][78]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh33?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][78]/C JFDCEXhzr> Jclock pessimismXhsB!t )%SFP_GEN[43].rx_data_ngccm_reg[43][78]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh06=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C+'SFP_GEN[43].rx_data_ngccm_reg[43][59]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu/>}UoS=\??==CD==>+'?G>K?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=V rx_data[43][59] Jnet (fo=1, routed)Xh=] +'SFP_GEN[43].rx_data_ngccm_reg[43][59]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhF?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh@5?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][59]/C JFDCEXhzr> Jclock pessimismXhCs )%SFP_GEN[43].rx_data_ngccm_reg[43][59]Hold_EFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhU; J arrival timeXhE?/ JXh4 JslackXh==g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C+'SFP_GEN[43].rx_data_ngccm_reg[43][49]/D"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsun>} $J %=В?J ?/S?=_PD=[=>'?G>CL?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_GFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[43][49] Jnet (fo=1, routed)Xh[=] +'SFP_GEN[43].rx_data_ngccm_reg[43][49]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][49]/C JFDCEXhzr> Jclock pessimismXh_Pt )%SFP_GEN[43].rx_data_ngccm_reg[43][49]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh $; J arrival timeXh?/ JXh4 JslackXh/S?=g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][64]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuV@}A1AS+B;A8@S+@A=А=C)*@4V>>L7@I??}?5?m?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(l@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>Y rx_data_ngccm[43] Jnet (fo=76, routed)XhC?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][64]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][64]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXhv )%SFP_GEN[43].rx_data_ngccm_reg[43][64]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh1A; J arrival timeXhd;/ JXh4 JslackXhC)*@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][66]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuV@}A1AS+B;A8@S+@A=А=C)*@4V>>L7@I??}?5?m?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(l@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>Y rx_data_ngccm[43] Jnet (fo=76, routed)XhC?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][66]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][66]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXhv )%SFP_GEN[43].rx_data_ngccm_reg[43][66]Setup_FFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh1A; J arrival timeXhd;/ JXh4 JslackXhC)*@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][69]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuV@}A1AS+B;A8@S+@A=А=C)*@4V>>L7@I??}?5?m?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(l@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>Y rx_data_ngccm[43] Jnet (fo=76, routed)XhC?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][69]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][69]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXhv )%SFP_GEN[43].rx_data_ngccm_reg[43][69]Setup_GFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXh1A; J arrival timeXhd;/ JXh4 JslackXhC)*@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][63]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsur=@}A1AS+B;A8@S+@A=А=*@4V>>@I??}?5?m?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(l@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>Y rx_data_ngccm[43] Jnet (fo=76, routed)Xh(?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][63]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][63]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXhu )%SFP_GEN[43].rx_data_ngccm_reg[43][63]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh1A; J arrival timeXh// JXh4 JslackXh*@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][65]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsur=@}A1AS+B;A8@S+@A=А=*@4V>>@I??}?5?m?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(l@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>Y rx_data_ngccm[43] Jnet (fo=76, routed)Xh(?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][65]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][65]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXhu )%SFP_GEN[43].rx_data_ngccm_reg[43][65]Setup_FFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh1A; J arrival timeXh// JXh4 JslackXh*@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][67]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsur=@}A1AS+B;A8@S+@A=А=*@4V>>@I??}?5?m?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(l@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>Y rx_data_ngccm[43] Jnet (fo=76, routed)Xh(?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][67]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)XhC@X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][67]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXhu )%SFP_GEN[43].rx_data_ngccm_reg[43][67]Setup_GFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh1A; J arrival timeXh// JXh4 JslackXh*@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][75]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuK@}AS1Ao+`x;A8@o+@A=А=37@4V>>-@I??}?5?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(l@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>Y rx_data_ngccm[43] Jnet (fo=76, routed)XhNb?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][75]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh @X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][75]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXhv )%SFP_GEN[43].rx_data_ngccm_reg[43][75]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXhS1A; J arrival timeXhG/ JXh4 JslackXh37@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][59]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu43@}A1Ao+`x;A8@o+@A=А=^8@4V>>{@I??}?5?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(l@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>Y rx_data_ngccm[43] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][59]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh @X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][59]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXhu )%SFP_GEN[43].rx_data_ngccm_reg[43][59]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh^8@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][79]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu43@}A1Ao+`x;A8@o+@A=А=^8@4V>>{@I??}?5?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(l@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>Y rx_data_ngccm[43] Jnet (fo=76, routed)Xh?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][79]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)Xh @X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][79]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXhu )%SFP_GEN[43].rx_data_ngccm_reg[43][79]Setup_FFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh^8@Lg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C,(SFP_GEN[43].rx_data_ngccm_reg[43][45]/CE"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuG@}A,1A*g7A8@*@A=А=?;@4V>>(@I??}?5?x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(l@ wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/I0 JXhzr vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/SFP_GEN[43].rx_data_ngccm[43][83]_i_1/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzr>Y rx_data_ngccm[43] Jnet (fo=76, routed)XhQ?^ ,(SFP_GEN[43].rx_data_ngccm_reg[43][45]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>w g_gbt_bank[3].gbtbank_n_94 Jnet (fo=674, routed)XhI @X1Y8 (CLOCK_ROOT)] +'SFP_GEN[43].rx_data_ngccm_reg[43][45]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXhv )%SFP_GEN[43].rx_data_ngccm_reg[43][45]Setup_AFF2_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh,1A; J arrival timeXh:/ JXh4 JslackXh?;@L( !gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!)y@1y @9Ay@Iy @eA@hq} == wv?66" rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C+'SFP_GEN[44].rx_data_ngccm_reg[44][66]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuE6>}|t=A??=="D=>%>M"?>yF?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/QProp_BFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[44][66] Jnet (fo=1, routed)Xh>] +'SFP_GEN[44].rx_data_ngccm_reg[44][66]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhsh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_104 Jnet (fo=674, routed)Xh(?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[44].rx_data_ngccm_reg[44][66]/C JFDCEXhzr> Jclock pessimismXh"s )%SFP_GEN[44].rx_data_ngccm_reg[44][66]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh|t; J arrival timeXh> ?/ JXh4 JslackXh==9g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu]B>}w6=َ?w? ="==%>|?>+G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/O85[1] Jnet (fo=2, routed)Xh1= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__43/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[20]_i_1__43/OProp_A6LUT_SLICEM_I0_O JLUT3XhzrQ8= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/I9[1] Jnet (fo=1, routed)XhD< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhI?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]/C JFDREXhzr> Jclock pessimismXh" g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[20]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh+?/ JXh4 JslackXh =g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu>}G w-J=ף?w?d6=IF=9H=%>o#?>+G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in Jnet (fo=2, routed)Xh+= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__43/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__43/OProp_C6LUT_SLICEM_I2_O JLUT3XhzrT= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhʁ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhI?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C JFDREXhzr> Jclock pessimismXhIF g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhG ; J arrival timeXh ף?/ JXh4 JslackXhd6=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuK>}w6=َ?w?7="=\=%>|?>+G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/QProp_AFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/O85[1] Jnet (fo=2, routed)Xh1= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__43/I2 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__43/OProp_C5LUT_SLICEM_I2_O JLUT3XhzrGa= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[18] Jnet (fo=1, routed)XhX94< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhI?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C JFDREXhzr> Jclock pessimismXh" g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[18]Hold_CFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhQ?/ JXh4 JslackXh7=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C+'SFP_GEN[44].rx_data_ngccm_reg[44][70]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu/>}WD=d;?D?8="D=l=%>A ?>@?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/QProp_FFF2_SLICEM_C_Q JFDREXhzrD=V rx_data[44][70] Jnet (fo=1, routed)Xhl=] +'SFP_GEN[44].rx_data_ngccm_reg[44][70]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhNb?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_104 Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[44].rx_data_ngccm_reg[44][70]/C JFDCEXhzr> Jclock pessimismXh"t )%SFP_GEN[44].rx_data_ngccm_reg[44][70]Hold_AFF2_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhW; J arrival timeXh?/ JXh4 JslackXh8=A+'SFP_GEN[44].rx_data_ngccm_reg[44][68]/C0,SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[68]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuX94>}۟VX=d;?V?|<="==%>A ?>A?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR)x +'SFP_GEN[44].rx_data_ngccm_reg[44][68]/QProp_AFF_SLICEM_C_Q JFDCEXhzr9H=w 40SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[83]_0[60] Jnet (fo=1, routed)Xhxi=_ 1-SFP_GEN[44].ngCCM_gbt/RX_Word_rx40[68]_i_1/I1 JXhzr 0,SFP_GEN[44].ngCCM_gbt/RX_Word_rx40[68]_i_1/OProp_D6LUT_SLICEM_I1_O JLUT3Xhzr/]=u 2.SFP_GEN[44].ngCCM_gbt/RX_Word_rx40[68]_i_1_n_0 Jnet (fo=1, routed)Xho<b 0,SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[68]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[3].gbtbank_n_104 Jnet (fo=674, routed)XhNb?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[44].rx_data_ngccm_reg[44][68]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[44].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[68]/C JFDCEXhzr> Jclock pessimismXh"x .*SFP_GEN[44].ngCCM_gbt/RX_Word_rx40_reg[68]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh۟; J arrival timeXh¥?/ JXh4 JslackXh|<=eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[31]/Ceag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[31]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuE6>}F板"˜=/?"?/1B=`<#D=>%>(?>=?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[31]/QProp_CFF_SLICEL_C_Q JFDCEXhzrD= _[g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0[31] Jnet (fo=1, routed)Xh> eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[31]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh |?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[31]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[31]/C JFDCEXhzr> Jclock pessimismXh`<# c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[31]Hold_CFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhF板; J arrival timeXh?/ JXh4 JslackXh/1B=:mig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/Cmig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuS=}K֣;|??L=iffo=@=%> ?>8A?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) mig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/QProp_AFF_SLICEL_C_Q JFDREXhzr9H= XTg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/timer[5] Jnet (fo=2, routed)Xh)\= rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__44/I0 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__44/OProp_A6LUT_SLICEL_I0_O JLUT6Xhzru< sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer[5]_i_3__44_n_0 Jnet (fo=1, routed)XhD< mig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK Jnet (fo=674, routed)Xhף?X1Y9 (CLOCK_ROOT) mig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK Jnet (fo=674, routed)Xhx?X1Y9 (CLOCK_ROOT) mig_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]/C JFDREXhzr> Jclock pessimismXhiff kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/clkSlipProcess.timer_reg[5]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhK; J arrival timeXh-?/ JXh4 JslackXhL=@,(SFP_GEN[44].ngCCM_gbt/pwr_good_pre_reg/C,(SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu>}<Nb==?Nb?HP=F=T=%>%?>rH?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR)y ,(SFP_GEN[44].ngCCM_gbt/pwr_good_pre_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=i &"SFP_GEN[44].ngCCM_gbt/pwr_good_pre Jnet (fo=1, routed)Xht=_ 1-SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_i_1__45/I1 JXhzr 0,SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_i_1__45/OProp_C6LUT_SLICEL_I1_O JLUT4XhzrT=u 2.SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_i_1__45_n_0 Jnet (fo=1, routed)Xho<^ ,(SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[44].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhЂ?X1Y9 (CLOCK_ROOT)^ ,(SFP_GEN[44].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[44].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)^ ,(SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_reg/C JFDREXhzr> Jclock pessimismXhFt *&SFP_GEN[44].ngCCM_gbt/pwr_good_cnt_regHold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh<; J arrival timeXh}??/ JXh4 JslackXhHP=eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/Ceag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuS=}+p;|?p?[P=!ko=@=%> ?>]B?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= ]Yg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/rxslide_in[0] Jnet (fo=2, routed)Xh)\= jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__43/I2 JXhzr ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__43/OProp_E6LUT_SLICEL_I2_O JLUT3Xhzru< kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_i_1__43_n_0 Jnet (fo=1, routed)XhD< eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= SOg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK Jnet (fo=674, routed)Xhף?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> SOg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C JFDCEXhzr> Jclock pessimismXh!k c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].rxBitSlipControl/RX_BITSLIPCMD_o_regHold_EFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh+; J arrival timeXh-?/ JXh4 JslackXh[P=d!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu.@}A 0Av'=.@v'@A=А=A@nX>S?rp@ K??5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhD4@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrQ= sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrZd> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43_n_0 Jnet (fo=1, routed)XhZd> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXhnX>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[0]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh 0A; J arrival timeXh\/ JXh4 JslackXhA@ d!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu.@}A 0Av'=.@v'@A=А=A@nX>S?rp@ K??5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhD4@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrQ= sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xh> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43/OProp_D6LUT_SLICEL_I2_O JLUT4XhzrZd> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_7__43_n_0 Jnet (fo=1, routed)XhZd> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr+> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state[1]_i_1__43_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhnX>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh 0A; J arrival timeXh\/ JXh4 JslackXhA@ rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsux@}A=0Ab(=.@b(@A=А=0"J@nX>?أp@ K??5?}??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhD4@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrQ= sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhD> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr֣p> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhnX>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh=0A; J arrival timeXhb/ JXh4 JslackXh0"J@ qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuX@}A1Ab(=.@b(@A=А=J@nX>?Nbp@ K??5?}??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhD4@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrQ= sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhD> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr֣p> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhnX>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhJ@ rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu٢@}A1AA(=.@A(@A=А=֒O@nX>?[dk@ K??5?ˡ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhD4@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrQ= sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhD> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr֣p> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]/C JFDREXhzr> Jclock pessimismXhnX>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[6]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh1A; J arrival timeXhE/ JXh4 JslackXh֒O@ qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuS@}A1AA(=.@A(@A=А=P@nX>?"k@ K??5?ˡ?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhD4@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrQ= sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhD> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr֣p> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]/C JFDREXhzr> Jclock pessimismXhnX>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[5]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXh1A; J arrival timeXh$/ JXh4 JslackXhP@ rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu@}A=0Ab(=.@b(@A=А=U@nX>?We@ K??5?}??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhD4@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrQ= sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhD> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr֣p> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhP> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]/C JFDREXhzr> Jclock pessimismXhnX>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]Setup_HFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh=0A; J arrival timeXh/ JXh4 JslackXhU@ rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu@}A=0Ab(=.@b(@A=А=U@nX>?We@ K??5?}??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhD4@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrQ= sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhD> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr֣p> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)XhP> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]/C JFDREXhzr> Jclock pessimismXhnX>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[1]Setup_GFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh=0A; J arrival timeXh/ JXh4 JslackXhU@ qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu+@}A1A'1(=.@'1(@A=А=% W@nX>?2d@ K??5??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)XhD4@ qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__43/OProp_D6LUT_SLICEL_I0_O JLUT4XhzrQ= sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhD> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__44/OProp_F6LUT_SLICEL_I3_O JLUT5Xhzr֣p> ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh)\> tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/CLK Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhnX>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXh% W@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[109]/D"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu@}AH2A'q=.@'@A=А=g`@nX> k?ף@ K??5?Z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXCTRL1[0]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXCTRL1[0] J GTHE3_CHANNELXhzr k? [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/D[9] Jnet (fo=6, routed)Xhף@ fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[109]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhP@X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[109]/C JFDCEXhzr> Jclock pessimismXhnX>@ Jclock uncertaintyXh d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[109]Setup_EFF_SLICEM_C_D JFDCEXho=/ JXh< J required timeXhH2A; J arrival timeXhp/ JXh4 JslackXhg`@( !gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!)y@1y @9Ay@Iy @eS@hq} < vv?77& rise - rise rise - rise  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C+'SFP_GEN[45].rx_data_ngccm_reg[45][46]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsun>}ƅ>(>d;?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=V rx_data[45][46] Jnet (fo=1, routed)Xh[=] +'SFP_GEN[45].rx_data_ngccm_reg[45][46]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh \?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_114 Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[45].rx_data_ngccm_reg[45][46]/C JFDCEXhzr> Jclock pessimismXh<.t )%SFP_GEN[45].rx_data_ngccm_reg[45][46]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhƅ; J arrival timeXh|?/ JXh4 JslackXh<g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C+'SFP_GEN[45].rx_data_ngccm_reg[45][69]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu/>}c=z??B=WD=l=j>p>(>?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[45][69] Jnet (fo=1, routed)Xhl=] +'SFP_GEN[45].rx_data_ngccm_reg[45][69]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_114 Jnet (fo=674, routed)Xh,?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[45].rx_data_ngccm_reg[45][69]/C JFDCEXhzr> Jclock pessimismXhWs )%SFP_GEN[45].rx_data_ngccm_reg[45][69]Hold_BFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh43?/ JXh4 JslackXhB=n0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[29]/CHDSFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu-2>}lX=[d{?X?e1=D=%>j>>(>.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR)~ 0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[29]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD=q .*SFP_GEN[45].ngCCM_gbt/gbt_rx_checker/Q[13] Jnet (fo=2, routed)Xh%>z HDSFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.]?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[29]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> GCSFP_GEN[45].ngCCM_gbt/gbt_rx_checker/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X1Y9 (CLOCK_ROOT)z HDSFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]/C JFDREXhzr> Jclock pessimismXh FBSFP_GEN[45].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[13]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhl; J arrival timeXh?/ JXh4 JslackXhe1=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C+'SFP_GEN[45].rx_data_ngccm_reg[45][51]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu~>}]=Iz??<=-D=/=j>>(>d;?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=V rx_data[45][51] Jnet (fo=1, routed)Xh/=] +'SFP_GEN[45].rx_data_ngccm_reg[45][51]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/]?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_114 Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[45].rx_data_ngccm_reg[45][51]/C JFDCEXhzr> Jclock pessimismXh-s )%SFP_GEN[45].rx_data_ngccm_reg[45][51]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXhth?/ JXh4 JslackXh<=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C+'SFP_GEN[45].rx_data_ngccm_reg[45][63]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuv>>}72_u=z??1==9H=I >j>p>(>d;?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=V rx_data[45][63] Jnet (fo=1, routed)XhI >] +'SFP_GEN[45].rx_data_ngccm_reg[45][63]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_114 Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[45].rx_data_ngccm_reg[45][63]/C JFDCEXhzr> Jclock pessimismXht )%SFP_GEN[45].rx_data_ngccm_reg[45][63]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh72; J arrival timeXh?/ JXh4 JslackXh1==<,(SFP_GEN[45].ngCCM_gbt/pwr_good_pre_reg/C,(SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_reg/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu)>}4X4=l{?X?@=.o==j>?(>.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR)y ,(SFP_GEN[45].ngCCM_gbt/pwr_good_pre_reg/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H=i &"SFP_GEN[45].ngCCM_gbt/pwr_good_pre Jnet (fo=1, routed)XhL7=_ 1-SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_i_1__11/I1 JXhzr 0,SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_i_1__11/OProp_C6LUT_SLICEL_I1_O JLUT4Xhzru<u 2.SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_i_1__11_n_0 Jnet (fo=1, routed)Xho<^ ,(SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_reg/D JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= 84SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@5^?X1Y9 (CLOCK_ROOT)^ ,(SFP_GEN[45].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X1Y9 (CLOCK_ROOT)^ ,(SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_reg/C JFDREXhzr> Jclock pessimismXh.t *&SFP_GEN[45].ngCCM_gbt/pwr_good_cnt_regHold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh4; J arrival timeXhĐ?/ JXh4 JslackXh@=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuD>} ="{? ?sJA=!o=o>j>v>(>$!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in Jnet (fo=2, routed)XhA`= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__44/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__44/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzru< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp]?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhP?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C JFDREXhzr> Jclock pessimismXh! g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]Hold_CFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh$?/ JXh4 JslackXhsJA=?+'SFP_GEN[45].rx_data_ngccm_reg[45][35]/C0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu'>} w=[d{? ?XB=, =w=j>>(>$!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR)y +'SFP_GEN[45].rx_data_ngccm_reg[45][35]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD=w 40SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[83]_0[27] Jnet (fo=1, routed)XhL7=_ 1-SFP_GEN[45].ngCCM_gbt/RX_Word_rx40[34]_i_1/I0 JXhzr 0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40[34]_i_1/OProp_D5LUT_SLICEL_I0_O JLUT3Xhzr=u 2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40[34]_i_1_n_0 Jnet (fo=1, routed)XhX94<b 0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/D JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr=x g_gbt_bank[3].gbtbank_n_114 Jnet (fo=674, routed)Xh.]?X1Y9 (CLOCK_ROOT)] +'SFP_GEN[45].rx_data_ngccm_reg[45][35]/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhP?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXh,y .*SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]Hold_DFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh; J arrival timeXh!?/ JXh4 JslackXhXB=g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C*&SFP_GEN[45].rx_data_ngccm_reg[45][0]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuv>}pq=U={?q=? C=-9H="=j>|>(>|?z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=U rx_data[45][0] Jnet (fo=1, routed)Xh"=\ *&SFP_GEN[45].rx_data_ngccm_reg[45][0]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh]?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C JFDREXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr>x g_gbt_bank[3].gbtbank_n_114 Jnet (fo=674, routed)XhȆ?X1Y9 (CLOCK_ROOT)\ *&SFP_GEN[45].rx_data_ngccm_reg[45][0]/C JFDCEXhzr> Jclock pessimismXh-r ($SFP_GEN[45].rx_data_ngccm_reg[45][0]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhp; J arrival timeXhʑ?/ JXh4 JslackXh C=eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[32]/Ceag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[32]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu">}5F#ۙa=5^z?#ۙ?Q`H=^,D=S=j>>(>S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[32]/QProp_CFF_SLICEM_C_Q JFDCEXhzrD= _[g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0[32] Jnet (fo=1, routed)XhS= eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[32]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh \?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[32]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhgf?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[32]/C JFDCEXhzr> Jclock pessimismXh^, c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[32]Hold_FFF2_SLICEM_C_D JFDCEXhGa=/ JXh< J required timeXh5F; J arrival timeXh8?/ JXh4 JslackXhQ`H=W$eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[11]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT2=1 LUT4=1 LUT6=3)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuA@}A!x-Ag)@@A=А=S@M>}?u?33{@TE?#۹?1?̜?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[11]/QProp_GFF2_SLICEL_C_Q JFDCEXhzrV> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/Q[7] Jnet (fo=12, routed)XhNb? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___6_i_5__44/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___6_i_5__44/OProp_D5LUT_SLICEM_I0_O JLUT2Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___6_i_5__44_n_0 Jnet (fo=2, routed)Xho#? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_2__44/I1 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_2__44/OProp_G6LUT_SLICEL_I1_O JLUT6Xhzr+> kgg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/s2_from_syndromes[1] Jnet (fo=36, routed)Xh? hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/i___38_i_1__44/I0 JXhzr gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/i___38_i_1__44/OProp_C6LUT_SLICEL_I0_O JLUT4XhzfX9= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/syndromes/i___32_i_5__44_0 Jnet (fo=22, routed)XhX9t? plg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__89/I5 JXhzf okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__89/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> qmg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/ERROR_DETECT_O_i_4__89_n_0 Jnet (fo=1, routed)Xh> xtg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__89/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/decoder/ERROR_DETECT_O_i_1__89/OProp_D6LUT_SLICEL_I3_O JLUT6Xhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg_1 Jnet (fo=1, routed)Xh*\= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/D JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhff@X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[11]/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_reg/C JFDREXhzr> Jclock pessimismXhM>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/decoder/gbtFrame_gen.reedSolomonDecoder60to119/ERROR_DETECT_O_regSetup_DFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXh!x-A; J arrival timeXhV/ JXh4 JslackXhS@$`!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuy~@}A+AZ:$Zd+@Z@A=А=@-iL>23?z@TE?p?1??(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhn? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/OProp_A6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xha> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__44/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__44/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzrgff> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__44_n_0 Jnet (fo=1, routed)Xh = okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__44/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__44/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__44_n_0 Jnet (fo=2, routed)Xh/> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xht?X1Y9 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]/C JFDCEXhzr> Jclock pessimismXh-iL>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[0]Setup_DFF_SLICEM_C_CE JFDCEXh/]/ JXh< J required timeXh+A; J arrival timeXhi/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu@}AC-ACv5Zd+@C@A=А=ɛ@L>?L79@TE?p?1?p?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[3] Jnet (fo=10, routed)XhL79@ eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhff?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[83]Setup_CFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXhC-A; J arrival timeXht/ JXh4 JslackXhɛ@ `!g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=2 LUT6=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu|@}A+AW9A&Zd+@W9@A=А=@jnL>23?43@TE?p?1?(\?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhn? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/OProp_A6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)Xha> okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__44/I2 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__44/OProp_B6LUT_SLICEM_I2_O JLUT4Xhzrgff> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_7__44_n_0 Jnet (fo=1, routed)Xh = okg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__44/I5 JXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__44/OProp_H6LUT_SLICEM_I5_O JLUT6Xhzr&1> plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state[1]_i_1__44_n_0 Jnet (fo=2, routed)Xh> kgg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/CE JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)XhQ?X1Y9 (CLOCK_ROOT) jfg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]/C JFDCEXhzr> Jclock pessimismXhjnL>@ Jclock uncertaintyXh hdg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/FSM_sequential_state_reg[1]Setup_HFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[3]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu.}@}A(-A"}7Zd+@"@A=А= u@L>?Zd3@TE?p?1?/?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[3] Jnet (fo=10, routed)XhZd3@ d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[3]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh$?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[3]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh b^g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[3]Setup_FFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXh(-A; J arrival timeXhD/ JXh4 JslackXh u@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[43]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsur@}A2-Ao#8Zd+@o@A=А=?@L>?'@TE?p?1?V?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[3]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[3] J GTHE3_CHANNELXhzr? [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[3] Jnet (fo=10, routed)Xh'@ eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[43]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[43]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[43]Setup_GFF_SLICEL_C_D JFDCEXho=/ JXh< J required timeXh2-A; J arrival timeXh/ JXh4 JslackXh?@ ng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsunj@}A+Ad0Zd+@@A=А=`p@L>(?Z@TE?p?1?z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhn? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/OProp_A6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__45/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__45/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrv= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh= ?X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]/C JFDREXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[3]Setup_HFF2_SLICEM_C_CE JFDREXhim/ JXh< J required timeXh+A; J arrival timeXhx/ JXh4 JslackXh`p@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[16]/D""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuq@}A(-A"}7Zd+@"@A=А=%y@L>"?,@TE?p?1?/?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[14]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[14] J GTHE3_CHANNELXhzr"? \Xg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/D[16] Jnet (fo=6, routed)Xh,@ eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[16]/D JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh$?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[16]/C JFDCEXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg0_reg[16]Setup_HFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXh(-A; J arrival timeXh+/ JXh4 JslackXh%y@mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsun=j@}A6+Ad0Zd+@@A=А=@L>(?(@TE?p?1?z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhn? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/OProp_A6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__45/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__45/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrv= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh= ?X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]/C JFDREXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[2]Setup_HFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh6+A; J arrival timeXh/ JXh4 JslackXh@ mg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT4=1 LUT5=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsun=j@}A6+Ad0Zd+@@A=А=@L>(?(@TE?p?1?z?(rising edge-triggered cell GTHE3_CHANNEL clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})z(rising edge-triggered cell FDRE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[1]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[1] J GTHE3_CHANNELXhzf ? rng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/bbstub_gtwiz_userdata_rx_out[19][1] Jnet (fo=10, routed)Xhn? qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/I0 JXhzf plg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/FSM_sequential_state[1]_i_3__44/OProp_A6LUT_SLICEL_I0_O JLUT4Xhzr)> sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[0]_0 Jnet (fo=5, routed)XhK> xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__45/I3 JXhzr wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders[6]_i_1__45/OProp_F6LUT_SLICEM_I3_O JLUT5Xhzrv= ^Zg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/nbCheckedHeaders0 Jnet (fo=7, routed)Xh? tpg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/CE JFDREXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh= ?X1Y9 (CLOCK_ROOT) sog_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]/C JFDREXhzr> Jclock pessimismXhL>@ Jclock uncertaintyXh qmg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/lockFSM_proc.nbCheckedHeaders_reg[4]Setup_GFF_SLICEM_C_CE JFDREXhGa/ JXh< J required timeXh6+A; J arrival timeXh/ JXh4 JslackXh@  rxoutclk_out[0]_1rxoutclk_out[0]_1!)Ë>?1Ë>@9AË>?IË>@hq}?::  TTC_rxusrclk TTC_rxusrclk!)Ë>?1Ë>@9AË>?IË>@ez#>hq}=ͣ><< rise - rise rise - rise  ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[248]/CZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[248]/D"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsu-2>}:㿍Q=7??=C+9H=>`0? -r?ʡE??e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[248]/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= TPi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0[248] Jnet (fo=1, routed)Xh> ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[248]/D JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh7?X3Y2 (CLOCK_ROOT) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[248]/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[248]/C JFDCEXhzr> Jclock pessimismXhC+ XTi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[248]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh:㿐; J arrival timeXh?/ JXh4 JslackXh= @}r  ~=? ?L=x+=Q=`0?Vm?ʡE?O?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) @ Jclock pessimismXhx+ \Xi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[67]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhr ; J arrival timeXhA/ JXh4 JslackXhL= O d`i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[138]/C@}޿Nb$<==%?Nb? '=9K9H==`0?&q?ʡE?h?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[138]/QProp_AFF_SLICEL_C_Q JFDCEXhzr9H=v 3/i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[138] Jnet (fo=1, routed)Xh=r @ Jclock pessimismXh9K >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[138]Hold_AFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh޿; J arrival timeXhS?/ JXh4 JslackXh '=G c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[94]/C?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[94]/D"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuv>>}B⿍=`0?n?ʡE?-?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[94]/QProp_HFF_SLICEL_C_Q JFDCEXhzrD=u 2.i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[94] Jnet (fo=1, routed)XhO >q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[94]/D JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh Jclock pessimismXh/[+ =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[94]Hold_HFF2_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhB⿐; J arrival timeXh?/ JXh4 JslackXhl-=H c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[91]/C?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]/D"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuE6>}῍A9=ף?A?[1=P+D=>`0?Nbp?ʡE?p?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[91]/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD=u 2.i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[91] Jnet (fo=1, routed)Xh>q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]/D JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhף?X3Y2 (CLOCK_ROOT) c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[91]/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)XhA?X3Y2 (CLOCK_ROOT)q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]/C JFDCEXhzr> Jclock pessimismXhP+ =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhῐ; J arrival timeXhl?/ JXh4 JslackXh[1= ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[61]/C^Zi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[11]/D"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZ(LUT6=1)bL Timing Exception: MultiCycle Path Setup -end 3 Hold -start 2j5TTC_rxusrclk rise@6.238ns - TTC_rxusrclk rise@6.238nsu/>}+֣ [=w?֣?Z6=gPo=Q=`0?n?ʡE?ҍ?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[61]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= @ Jclock pessimismXhgP \Xi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[11]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh+; J arrival timeXhq=A/ JXh4 JslackXhZ6= }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/memory_register_reg[24]/C|i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[5]/D"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZ(LUT3=1)j5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuMb>}\ۿ￭#=|??b8=* T=@=`0?{n?ʡE?I?e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR)  }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/memory_register_reg[24]/QProp_EFF_SLICEL_C_Q JFDREXhzr9H= {wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/memory_register[24] Jnet (fo=2, routed)Xh)\= }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData[5]_i_1/I0 JXhzr |i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData[5]_i_1/OProp_A6LUT_SLICEL_I0_O JLUT3XhzrQ8= rni_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/p_0_out[5] Jnet (fo=1, routed)XhD< |i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[5]/D JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/rxusrclk_out Jnet (fo=1861, routed)Xh|?X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/memory_register_reg[24]/C JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) |i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[5]/C JFDREXhzr> Jclock pessimismXh* T ~zi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler60bitOrder58_h1_inst/descrambledData_reg[5]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh\ۿ; J arrival timeXh7?/ JXh4 JslackXhb8= ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[96]/C_[i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[168]/D"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZ(LUT6=1)bL Timing Exception: MultiCycle Path Setup -end 3 Hold -start 2j5TTC_rxusrclk rise@6.238ns - TTC_rxusrclk rise@6.238nsu>}) ]P=???8=Mo=X9=`0? p?ʡE??e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[96]/QProp_FFF_SLICEL_C_Q JFDCEXhzr9H= @ Jclock pessimismXhM ]Yi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[168]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh); J arrival timeXhMA/ JXh4 JslackXh?8= P d`i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[236]/C@}⿍%=G?%?9=3+9H=+>`0?q?ʡE??5?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[236]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H=v 3/i_tcds2_if/cmp_lpgbtfpga_uplink/gbxFrame_s[236] Jnet (fo=1, routed)Xh+>r @ Jclock pessimismXh3+ >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[236]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXh⿐; J arrival timeXhr?/ JXh4 JslackXh9=F c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[48]/C?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[48]/D"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsu:A>} ⿍%=Nb?%?Gm9=H+9H=)\>`0?q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[48]/D JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)XhNb?X3Y2 (CLOCK_ROOT) c_i_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/dat_outFrame_o_reg[48]/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xh%?X3Y2 (CLOCK_ROOT)q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[48]/C JFDCEXhzr> Jclock pessimismXhH+ =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[48]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh ⿐; J arrival timeXhv?/ JXh4 JslackXhGm9= 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C^Zi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[5]/CE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsuO5@}G@>.@jl x@jl@G@=А=z#> >O >z,@)\?&@/? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/QProp_EFF2_SLICEL_C_Q JFDCEXhzrO > _[i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[233]_0 Jnet (fo=708, routed)Xhz,@ ^Zi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[5]/CE JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT)f 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr GCi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/rxusrclk_out Jnet (fo=1861, routed)Xhjl@X3Y2 (CLOCK_ROOT) ]Yi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[5]/C JFDREXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh [Wi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[5]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh>.@; J arrival timeXhn/ JXh4 JslackXhz#> 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C_[i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[95]/CE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsuO5@}G@>.@jl x@jl@G@=А=z#> >O >z,@)\?&@/? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/QProp_EFF2_SLICEL_C_Q JFDCEXhzrO > _[i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[233]_0 Jnet (fo=708, routed)Xhz,@ _[i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[95]/CE JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT)f 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr GCi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/rxusrclk_out Jnet (fo=1861, routed)Xhjl@X3Y2 (CLOCK_ROOT) ^Zi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[95]/C JFDREXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh \Xi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/fec5_correction_pattern_o_reg[95]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh>.@; J arrival timeXhn/ JXh4 JslackXhz#> 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[19]/CE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu4@}G@>@lpx@l@G@=А=*> >O >(,@)\?&@/??5@e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/QProp_EFF2_SLICEL_C_Q JFDCEXhzrO > |i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[0]_0 Jnet (fo=708, routed)Xh(,@ ~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[19]/CE JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT)f 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out Jnet (fo=1861, routed)Xhl@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[19]/C JFDREXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[19]Setup_EFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh>@; J arrival timeXhw/ JXh4 JslackXh*> 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[57]/CE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu4@}G@>@lpx@l@G@=А=*> >O >(,@)\?&@/??5@e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/QProp_EFF2_SLICEL_C_Q JFDCEXhzrO > |i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[0]_0 Jnet (fo=708, routed)Xh(,@ ~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[57]/CE JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT)f 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out Jnet (fo=1861, routed)Xhl@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[57]/C JFDREXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/memory_register_reg[57]Setup_FFF2_SLICEL_C_CE JFDREXhim/ JXh< J required timeXh>@; J arrival timeXhw/ JXh4 JslackXh*> 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[12]/CE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu4@}G@>@Cl[x@Cl@G@=А=3*> >O >(,@)\?&@/? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/QProp_EFF2_SLICEL_C_Q JFDCEXhzrO > |i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[0]_0 Jnet (fo=708, routed)Xh(,@ ~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[12]/CE JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT)f 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out Jnet (fo=1861, routed)XhCl@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[12]/C JFDREXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[12]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh>@; J arrival timeXhw/ JXh4 JslackXh3*> 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[31]/CE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu4@}G@>@Cl[x@Cl@G@=А=3*> >O >(,@)\?&@/? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/QProp_EFF2_SLICEL_C_Q JFDCEXhzrO > |i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[0]_0 Jnet (fo=708, routed)Xh(,@ ~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[31]/CE JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT)f 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out Jnet (fo=1861, routed)XhCl@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[31]/C JFDREXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[31]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh>@; J arrival timeXhw/ JXh4 JslackXh3*> 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[47]/CE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu4@}G@>@Cl[x@Cl@G@=А=3*> >O >(,@)\?&@/? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/QProp_EFF2_SLICEL_C_Q JFDCEXhzrO > |i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[0]_0 Jnet (fo=708, routed)Xh(,@ ~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[47]/CE JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT)f 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out Jnet (fo=1861, routed)XhCl@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[47]/C JFDREXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[47]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh>@; J arrival timeXhw/ JXh4 JslackXh3*> 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[50]/CE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu4@}G@>@Cl[x@Cl@G@=А=3*> >O >(,@)\?&@/? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/QProp_EFF2_SLICEL_C_Q JFDCEXhzrO > |i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[0]_0 Jnet (fo=708, routed)Xh(,@ ~i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[50]/CE JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT)f 40i_tcds2_if/cmp_lpgbtfpga_uplink/clkEnOut_s_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/rxusrclk_out Jnet (fo=1861, routed)XhCl@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[50]/C JFDREXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l1_inst/descrambledData_reg[50]Setup_AFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh>@; J arrival timeXhw/ JXh4 JslackXh3*>, \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C}i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[11]/R"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu5^2@}G@.@Zl*x@Zl@G@=А=M,> >)\>rh)@)\?@/? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzf)\> oki_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/reset_i Jnet (fo=731, routed)Xhrh)@ }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[11]/R JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out Jnet (fo=1861, routed)XhZl@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[11]/C JFDREXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[11]Setup_HFF_SLICEL_C_R JFDREXh\½/ JXh< J required timeXh.@; J arrival timeXhp/ JXh4 JslackXhM,>, \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C}i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[30]/R"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu5^2@}G@.@Zl*x@Zl@G@=А=M,> >)\>rh)@)\?@/? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})e(rising edge-triggered cell FDRE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow TTC_rxusrclk TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzf)\> oki_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/reset_i Jnet (fo=731, routed)Xhrh)@ }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[30]/R JFDREXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr tpi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/rxusrclk_out Jnet (fo=1861, routed)XhZl@X3Y2 (CLOCK_ROOT) }i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[30]/C JFDREXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh {i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_h0_inst/descrambledData_reg[30]Setup_GFF_SLICEL_C_R JFDREXh\½/ JXh< J required timeXh.@; J arrival timeXhp/ JXh4 JslackXhM,>  fabric_clk_in fabric_clk_in!)Ë>(@1Ë>8@9AË>(@IË>8@eAhq}q8=@==@ rise - rise rise - rise  { -)i_tcds2_if/prbs_checker/data_r_reg[104]/C.*i_tcds2_if/prbs_checker/data_r2_reg[104]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZj7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsu`->}j<SS3=z4@SS@q8=ӾD==^I?B?A`?+g?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR)z -)i_tcds2_if/prbs_checker/data_r_reg[104]/QProp_GFF_SLICEL_C_Q JFDREXhzrD=j '#i_tcds2_if/prbs_checker/data_r[104] Jnet (fo=1, routed)Xh=` .*i_tcds2_if/prbs_checker/data_r2_reg[104]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)XhE?X4Y2 (CLOCK_ROOT)_ -)i_tcds2_if/prbs_checker/data_r_reg[104]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xht?L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)XhF?X4Y2 (CLOCK_ROOT)` .*i_tcds2_if/prbs_checker/data_r2_reg[104]/C JFDREXhzr> Jclock pessimismXhӾv ,(i_tcds2_if/prbs_checker/data_r2_reg[104]Hold_EFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhj<; J arrival timeXhK?@/ JXh4 JslackXhq8=} -)i_tcds2_if/prbs_checker/data_r_reg[129]/C.*i_tcds2_if/prbs_checker/data_r2_reg[129]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZj7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsuph>}o8GQqK+=q=2@GQ@9=⾥D==^I?#9?A`?^?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR){ -)i_tcds2_if/prbs_checker/data_r_reg[129]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD=j '#i_tcds2_if/prbs_checker/data_r[129] Jnet (fo=1, routed)Xh=` .*i_tcds2_if/prbs_checker/data_r2_reg[129]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)Xh?X4Y2 (CLOCK_ROOT)_ -)i_tcds2_if/prbs_checker/data_r_reg[129]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xht?L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)Xh?X4Y2 (CLOCK_ROOT)` .*i_tcds2_if/prbs_checker/data_r2_reg[129]/C JFDREXhzr> Jclock pessimismXh⾐w ,(i_tcds2_if/prbs_checker/data_r2_reg[129]Hold_EFF2_SLICEL_C_D JFDREXhGa=/ JXh< J required timeXho8; J arrival timeXhS;@/ JXh4 JslackXh9=t ,(i_tcds2_if/prbs_checker/data_r_reg[59]/C-)i_tcds2_if/prbs_checker/data_r2_reg[59]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZj7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsuUb>}ZL:CS.=Z4@CS@D=e侥D=v=^I?MB?A`?zf?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR)z ,(i_tcds2_if/prbs_checker/data_r_reg[59]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD=i &"i_tcds2_if/prbs_checker/data_r[59] Jnet (fo=1, routed)Xhv=_ -)i_tcds2_if/prbs_checker/data_r2_reg[59]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)Xh?X4Y2 (CLOCK_ROOT)^ ,(i_tcds2_if/prbs_checker/data_r_reg[59]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xht?L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)Xh?X4Y2 (CLOCK_ROOT)_ -)i_tcds2_if/prbs_checker/data_r2_reg[59]/C JFDREXhzr> Jclock pessimismXhe侐u +'i_tcds2_if/prbs_checker/data_r2_reg[59]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhZL:; J arrival timeXhB`=@/ JXh4 JslackXhD=i_tcds2_if/bcnt_reg[6]/Ci_tcds2_if/bcnt_reg[8]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsu=} 3vN֣;/@vN@.]=\9o=aP=^I?*\/?A`?GS?h(rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR)i i_tcds2_if/bcnt_reg[6]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= wsi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt_reg[11][6] Jnet (fo=7, routed)Xhw= vri_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt[8]_i_1/I2 JXhzr uqi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt[8]_i_1/OProp_A6LUT_SLICEM_I2_O JLUT6Xhzru<[ i_tcds2_if/p_0_in[8] Jnet (fo=1, routed)XhD<N i_tcds2_if/bcnt_reg[8]/D JFDCEXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף<u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)XhD?X4Y2 (CLOCK_ROOT)N i_tcds2_if/bcnt_reg[6]/C JFDCEXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xht?L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr=u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)Xh?X4Y2 (CLOCK_ROOT)N i_tcds2_if/bcnt_reg[8]/C JFDCEXhzr> Jclock pessimismXh\9d i_tcds2_if/bcnt_reg[8]Hold_AFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh 3; J arrival timeXh6@/ JXh4 JslackXh.]= #i_tcds2_if/ttc_rx_err_cnt_reg/C#i_tcds2_if/ttc_rx_err_cnt_reg/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsu>=}:8FS;/4@FS@Ga=m%=T=^I?ZD?A`?:h?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR)p #i_tcds2_if/ttc_rx_err_cnt_reg/QProp_HFF_SLICEL_C_Q JFDREXhzrD= RNi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/ttc_rx_err_cnt_reg_0[0] Jnet (fo=2, routed)Xht=~ PLi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/ttc_rx_err_cnt_i_1/I5 JXhzr OKi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_decoder_inst/ttc_rx_err_cnt_i_1/OProp_H6LUT_SLICEL_I5_O JLUT6Xhzru<k ($i_tcds2_if/cmp_lpgbtfpga_uplink_n_41 Jnet (fo=1, routed)Xho<U #i_tcds2_if/ttc_rx_err_cnt_reg/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף<u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)Xh> ?X4Y2 (CLOCK_ROOT)U #i_tcds2_if/ttc_rx_err_cnt_reg/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xht?L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr=u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)Xhz?X4Y2 (CLOCK_ROOT)U #i_tcds2_if/ttc_rx_err_cnt_reg/C JFDREXhzr> Jclock pessimismXhmk !i_tcds2_if/ttc_rx_err_cnt_regHold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh:8; J arrival timeXhY9<@/ JXh4 JslackXhGa=u ,(i_tcds2_if/prbs_checker/data_r_reg[41]/C-)i_tcds2_if/prbs_checker/data_r2_reg[41]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZj7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsup=>}y<tS,z=(4@tS@a=ӾD=I >^I?8A?A`?g?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR)z ,(i_tcds2_if/prbs_checker/data_r_reg[41]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD=i &"i_tcds2_if/prbs_checker/data_r[41] Jnet (fo=1, routed)XhI >_ -)i_tcds2_if/prbs_checker/data_r2_reg[41]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)Xhˡ?X4Y2 (CLOCK_ROOT)^ ,(i_tcds2_if/prbs_checker/data_r_reg[41]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xht?L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)Xh?X4Y2 (CLOCK_ROOT)_ -)i_tcds2_if/prbs_checker/data_r2_reg[41]/C JFDREXhzr> Jclock pessimismXhӾv +'i_tcds2_if/prbs_checker/data_r2_reg[41]Hold_FFF2_SLICEL_C_D JFDREXhGa=/ JXh< J required timeXhy<; J arrival timeXh@@/ JXh4 JslackXha=i_tcds2_if/bcnt_reg[3]/Ci_tcds2_if/bcnt_reg[4]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsu=}3gfN ף;/@gfN@`e=53o=Y=^I?/?A`?tS?h(rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR)j i_tcds2_if/bcnt_reg[3]/QProp_AFF2_SLICEL_C_Q JFDCEXhzr9H= wsi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt_reg[11][3] Jnet (fo=6, routed)XhP= vri_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt[4]_i_1/I4 JXhzr uqi_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_descrambler_inst/fec5_gen.descrambler58bitOrder58_l0_inst/bcnt[4]_i_1/OProp_C6LUT_SLICEL_I4_O JLUT6Xhzru<[ i_tcds2_if/p_0_in[4] Jnet (fo=1, routed)Xho<N i_tcds2_if/bcnt_reg[4]/D JFDCEXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף<u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)Xh?X4Y2 (CLOCK_ROOT)N i_tcds2_if/bcnt_reg[3]/C JFDCEXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xht?L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr=u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)Xh#?X4Y2 (CLOCK_ROOT)N i_tcds2_if/bcnt_reg[4]/C JFDCEXhzr> Jclock pessimismXh53d i_tcds2_if/bcnt_reg[4]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh3; J arrival timeXh+7@/ JXh4 JslackXh`e={ -)i_tcds2_if/prbs_checker/data_r_reg[128]/C.*i_tcds2_if/prbs_checker/data_r2_reg[128]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZj7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsuS>} 8GQqK+=q=2@GQ@b5j=⾥D="=^I?#9?A`?^?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR)z -)i_tcds2_if/prbs_checker/data_r_reg[128]/QProp_HFF_SLICEL_C_Q JFDREXhzrD=j '#i_tcds2_if/prbs_checker/data_r[128] Jnet (fo=1, routed)Xh"=` .*i_tcds2_if/prbs_checker/data_r2_reg[128]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)Xh?X4Y2 (CLOCK_ROOT)_ -)i_tcds2_if/prbs_checker/data_r_reg[128]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xht?L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)Xh?X4Y2 (CLOCK_ROOT)` .*i_tcds2_if/prbs_checker/data_r2_reg[128]/C JFDREXhzr> Jclock pessimismXh⾐v ,(i_tcds2_if/prbs_checker/data_r2_reg[128]Hold_EFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh 8; J arrival timeXh(<@/ JXh4 JslackXhb5j=C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/C:6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[21]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsuL>}'=jTX=z4@jT@!q=Ӿ%=I >^I?B?A`?k?h(rising edge-triggered cell FDSE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR) C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/QProp_CFF2_SLICEL_C_Q JFDSEXhzrD=q -)i_tcds2_if/prbs_checker/cmp_prbs_gen/Q[1] Jnet (fo=29, routed)Xh"=l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff[21]_i_1__0/I0 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff[21]_i_1__0/OProp_B6LUT_SLICEL_I0_O JLUT6Xhzru<v 3/i_tcds2_if/prbs_checker/cmp_prbs_gen/p_1_in[21] Jnet (fo=1, routed)Xhu<l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[21]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)XhE?X4Y2 (CLOCK_ROOT)u C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/C JFDSEXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xht?L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)XhT?X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[21]/C JFDREXhzr> Jclock pessimismXhӾ 84i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[21]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh'=; J arrival timeXhGA@/ JXh4 JslackXh!q=:6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[12]/C95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[58]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT6=1)j7fabric_clk_in rise@0.000ns - fabric_clk_in rise@0.000nsuz>}!)8Q<2@Q@w=/辥=aP=^I?l;?A`?A`?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk_in fabric_clk_in fabric_clk_in(DCD - SCD - CPR) :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[12]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[11] Jnet (fo=43, routed)Xhw=k =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[58]_i_1__0/I1 JXhzr <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[58]_i_1__0/OProp_F6LUT_SLICEL_I1_O JLUT6XhzrQ8= <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[58]_0[0] Jnet (fo=1, routed)XhD<k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[58]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh ?O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr ף< :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh?X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[12]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xht?L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr= :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)XhA?X4Y2 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[58]/C JFDREXhzr> Jclock pessimismXh/辐 73i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[58]Hold_FFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh!)8; J arrival timeXh0<@/ JXh4 JslackXhw=+:i_tcds2_if/bcnt_reg[8]/C:6i_tcds2_if/local_ttc_reg[sync_flags_and_commands][0]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT2=1 LUT6=2)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsuC@}ABEx齵I@E@A=А=Al?CK?#@p?K7???h(rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDCE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) i i_tcds2_if/bcnt_reg[8]/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\>b i_tcds2_if/bcnt_reg_n_0_[8] Jnet (fo=5, routed)Xh+>i ;7i_tcds2_if/local_ttc[sync_flags_and_commands][0]_i_3/I4 JXhzr :6i_tcds2_if/local_ttc[sync_flags_and_commands][0]_i_3/OProp_E6LUT_SLICEM_I4_O JLUT6Xhzf"y> <8i_tcds2_if/local_ttc[sync_flags_and_commands][0]_i_3_n_0 Jnet (fo=1, routed)Xh%>i ;7i_tcds2_if/local_ttc[sync_flags_and_commands][0]_i_2/I5 JXhzf :6i_tcds2_if/local_ttc[sync_flags_and_commands][0]_i_2/OProp_F6LUT_SLICEM_I5_O JLUT6Xhzflg> @:ctrl_regs_inst/local_ttc[sync_flags_and_commands][0]_i_1/OProp_B5LUT_SLICEM_I1_O JLUT2Xhzrj<>w 40i_tcds2_if/local_ttc[sync_flags_and_commands][0] Jnet (fo=1, routed)Xhv@l :6i_tcds2_if/local_ttc_reg[sync_flags_and_commands][0]/D JFDCEXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh+G@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף>u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)XhS{@X4Y2 (CLOCK_ROOT)N i_tcds2_if/bcnt_reg[8]/C JFDCEXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhj4@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr>u i_tcds2_if/fabric_clk_in Jnet (fo=792, routed)Xh5^j@X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/local_ttc_reg[sync_flags_and_commands][0]/C JFDCEXhzr> Jclock pessimismXhl?@ Jclock uncertaintyXh 84i_tcds2_if/local_ttc_reg[sync_flags_and_commands][0]Setup_EFF_SLICEL_C_D JFDCEXho=/ JXh< J required timeXhB; J arrival timeXhi/ JXh4 JslackXhA95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[2]/C:6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[127]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT2=1 LUT5=1 LUT6=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsu -@}A+B/pm?@/@A=А=>ΠAQj&?Mb0? @p?@??h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[2]/QProp_CFF_SLICEL_C_Q JFDREXhzrO > <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[1] Jnet (fo=47, routed)Xh?i ;7i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[228]_i_2/I1 JXhzr :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[228]_i_2/OProp_A6LUT_SLICEL_I1_O JLUT2Xhzr)> <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[228]_i_2_n_0 Jnet (fo=22, routed)Xhrh?i ;7i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[167]_i_2/I0 JXhzr :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[167]_i_2/OProp_G6LUT_SLICEL_I0_O JLUT6Xhzr)> <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[167]_i_2_n_0 Jnet (fo=4, routed)Xh&>l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[127]_i_1__0/I4 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[127]_i_1__0/OProp_C6LUT_SLICEL_I4_O JLUT5XhzrA`> >:i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[115]_4[12] Jnet (fo=1, routed)XhVN?l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[127]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh+G@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)XhX@X4Y2 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[2]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhj4@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)XhOe@X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[127]/C JFDREXhzr> Jclock pessimismXhQj&?@ Jclock uncertaintyXh 84i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[127]Setup_EFF_SLICEL_C_D JFDREXho=/ JXh< J required timeXh+B; J arrival timeXhnC/ JXh4 JslackXh>ΠA/:6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C:6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT2=1 LUT6=2)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsuK@}AX*BL7`%@L7@A=А=5@AbS&??ףx@p?z@?ף?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/QProp_HFF_SLICEL_C_Q JFDREXhzrO > =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[16] Jnet (fo=49, routed)Xh?i ;7i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6/I0 JXhzr :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6/OProp_D6LUT_SLICEL_I0_O JLUT2XhzrFs> <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6_n_0 Jnet (fo=8, routed)Xh ?l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0/I5 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr`P= ?;i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0_n_0 Jnet (fo=3, routed)Xh>l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[130]_i_1__0/I5 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[130]_i_1__0/OProp_B6LUT_SLICEL_I5_O JLUT6Xhzr)> >:i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[115]_4[15] Jnet (fo=1, routed)Xh+=l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh+G@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhff@X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhj4@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)XhA`e@X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]/C JFDREXhzr> Jclock pessimismXhbS&?@ Jclock uncertaintyXh 84i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[130]Setup_BFF_SLICEL_C_D JFDREXh}=/ JXh< J required timeXhX*B; J arrival timeXh(@/ JXh4 JslackXh5@A1w:6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[86]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT6=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsu"@}A>B2NN%@@A=А= sAG&?$&?jt@p?z@??h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/QProp_HFF_SLICEL_C_Q JFDREXhzrO > =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[16] Jnet (fo=49, routed)Xh~?i ;7i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4/I3 JXhzr :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4/OProp_B5LUT_SLICEL_I3_O JLUT4XhzrC> <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4_n_0 Jnet (fo=15, routed)XhO @k =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[86]_i_1__0/I2 JXhzr <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[86]_i_1__0/OProp_G6LUT_SLICEL_I2_O JLUT6Xhzrjt> <8i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[77]_1[9] Jnet (fo=1, routed)XhC =k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[86]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh+G@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhff@X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhj4@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh+f@X4Y2 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[86]/C JFDREXhzr> Jclock pessimismXhG&?@ Jclock uncertaintyXh 73i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[86]Setup_GFF_SLICEL_C_D JFDREXho=/ JXh< J required timeXh>B; J arrival timeXh{@/ JXh4 JslackXh sA1:6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C:6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[170]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT2=1 LUT6=2)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsux@}A^+BL7`%@L7@A=А=AbS&?r=*?q@p?z@?ף?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/QProp_HFF_SLICEL_C_Q JFDREXhzrO > =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[16] Jnet (fo=49, routed)Xh?i ;7i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6/I0 JXhzr :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6/OProp_D6LUT_SLICEL_I0_O JLUT2XhzrFs> <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6_n_0 Jnet (fo=8, routed)Xh ?l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0/I5 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr`P= ?;i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0_n_0 Jnet (fo=3, routed)Xh|?>l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[170]_i_1__0/I5 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[170]_i_1__0/OProp_D6LUT_SLICEL_I5_O JLUT6XhzrFs> >:i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[153]_5[17] Jnet (fo=1, routed)Xh*\=l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[170]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh+G@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhff@X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhj4@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)XhA`e@X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[170]/C JFDREXhzr> Jclock pessimismXhbS&?@ Jclock uncertaintyXh 84i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[170]Setup_DFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXh^+B; J arrival timeXhN?/ JXh4 JslackXhA1y:6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[91]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=1 LUT6=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsup@}AKBEE?%@E@A=А=A=&?t?v@p?z@?0?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/QProp_HFF_SLICEL_C_Q JFDREXhzrO > =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[16] Jnet (fo=49, routed)Xh~?i ;7i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4/I3 JXhzr :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4/OProp_B5LUT_SLICEL_I3_O JLUT4XhzrC> <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4_n_0 Jnet (fo=15, routed)Xh@k =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[91]_i_1__0/I0 JXhzr <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[91]_i_1__0/OProp_B6LUT_SLICEL_I0_O JLUT6Xhzr)> =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[77]_1[14] Jnet (fo=1, routed)Xh+=k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[91]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh+G@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhff@X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhj4@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xh|g@X4Y2 (CLOCK_ROOT)k 95i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[91]/C JFDREXhzr> Jclock pessimismXh=&?@ Jclock uncertaintyXh 73i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[91]Setup_BFF_SLICEL_C_D JFDREXh}=/ JXh< J required timeXhKB; J arrival timeXhe;?/ JXh4 JslackXhA1g-)i_tcds2_if/prbs_checker/data_r2_reg[53]/CD@i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/CE"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(CARRY8=8 LUT5=1 LUT6=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsuV@}ABtNT(@t@A=А=SA67&?I ?K@p?Z@??h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) &{ -)i_tcds2_if/prbs_checker/data_r2_reg[53]/QProp_EFF2_SLICEL_C_Q JFDREXhzrO > UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_4 Jnet (fo=1, routed)XhH? RNi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_75/I2 JXhzr QMi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_75/OProp_B6LUT_SLICEL_I2_O JLUT6XhzrY= SOi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_75_n_0 Jnet (fo=1, routed)Xh XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/S[1] JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CO[7]Prop_CARRY8_SLICEL_S[1]_CO[7] JCARRY8Xhzr`> WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32_n_0 Jnet (fo=1, routed)Xh 0= VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14_n_0 Jnet (fo=1, routed)Xh< UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CI JXhzr XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8XhzrB`< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7_n_0 Jnet (fo=1, routed)Xh< UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CI JXhzr XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CO[5]Prop_CARRY8_SLICEL_CI_CO[5] JCARRY8XhzrC >q .*i_tcds2_if/prbs_checker/cmp_prbs_gen/CO[0] Jnet (fo=3, routed)Xht? QMi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_2/I1 JXhzr PLi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_2/OProp_H6LUT_SLICEL_I1_O JLUT5XhzrFs>n +'i_tcds2_if/prbs_checker/prbs_lock_state Jnet (fo=2, routed)Xh>v D@i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/CE JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh+G@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)Xh7@X4Y2 (CLOCK_ROOT)_ -)i_tcds2_if/prbs_checker/data_r2_reg[53]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhj4@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)Xh#i@X4Y2 (CLOCK_ROOT)u C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]/C JFDREXhzr> Jclock pessimismXh67&?@ Jclock uncertaintyXh A=i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[0]Setup_DFF2_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhB; J arrival timeXh{?=/ JXh4 JslackXhSAg-)i_tcds2_if/prbs_checker/data_r2_reg[53]/CD@i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/CE"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(CARRY8=8 LUT5=1 LUT6=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsuV@}ABtNT(@t@A=А=SA67&?I ?K@p?Z@??h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDSE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) &{ -)i_tcds2_if/prbs_checker/data_r2_reg[53]/QProp_EFF2_SLICEL_C_Q JFDREXhzrO > UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_4 Jnet (fo=1, routed)XhH? RNi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_75/I2 JXhzr QMi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_75/OProp_B6LUT_SLICEL_I2_O JLUT6XhzrY= SOi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_75_n_0 Jnet (fo=1, routed)Xh XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/S[1] JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59/CO[7]Prop_CARRY8_SLICEL_S[1]_CO[7] JCARRY8Xhzr`> WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_59_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_50_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_41_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_32_n_0 Jnet (fo=1, routed)Xh 0= VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_23_n_0 Jnet (fo=1, routed)Xh< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CI JXhzr YUi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8XhzrB`< WSi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_14_n_0 Jnet (fo=1, routed)Xh< UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CI JXhzr XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8XhzrB`< VRi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_7_n_0 Jnet (fo=1, routed)Xh< UQi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CI JXhzr XTi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state_reg[1]_i_5/CO[5]Prop_CARRY8_SLICEL_CI_CO[5] JCARRY8XhzrC >q .*i_tcds2_if/prbs_checker/cmp_prbs_gen/CO[0] Jnet (fo=3, routed)Xht? QMi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_2/I1 JXhzr PLi_tcds2_if/prbs_checker/cmp_prbs_gen/FSM_sequential_prbs_lock_state[1]_i_2/OProp_H6LUT_SLICEL_I1_O JLUT5XhzrFs>n +'i_tcds2_if/prbs_checker/prbs_lock_state Jnet (fo=2, routed)Xh>v D@i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/CE JFDSEXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh+G@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)Xh7@X4Y2 (CLOCK_ROOT)_ -)i_tcds2_if/prbs_checker/data_r2_reg[53]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhj4@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> +'i_tcds2_if/prbs_checker/node_ff_reg[22] Jnet (fo=792, routed)Xh#i@X4Y2 (CLOCK_ROOT)u C?i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]/C JFDSEXhzr> Jclock pessimismXh67&?@ Jclock uncertaintyXh A=i_tcds2_if/prbs_checker/FSM_sequential_prbs_lock_state_reg[1]Setup_CFF2_SLICEL_C_CE JFDSEXhGa/ JXh< J required timeXhB; J arrival timeXh{?=/ JXh4 JslackXhSA:6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C:6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[210]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT2=1 LUT6=2)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsuे@}Ae-BG^%@G@A=А=/AR&?!?j@p?z@?`?h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/QProp_HFF_SLICEL_C_Q JFDREXhzrO > =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[16] Jnet (fo=49, routed)Xh?i ;7i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6/I0 JXhzr :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6/OProp_D6LUT_SLICEL_I0_O JLUT2XhzrFs> <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[231]_i_6_n_0 Jnet (fo=8, routed)Xh ?l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0/I5 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr`P= ?;i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_2__0_n_0 Jnet (fo=3, routed)Xh㥛=l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_1__0/I5 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[210]_i_1__0/OProp_C6LUT_SLICEL_I5_O JLUT6Xhzr> =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[210]_6[0] Jnet (fo=1, routed)XhP=l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[210]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh+G@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhff@X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhj4@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhe@X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[210]/C JFDREXhzr> Jclock pessimismXhR&?@ Jclock uncertaintyXh 84i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[210]Setup_CFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXhe-B; J arrival timeXhV</ JXh4 JslackXh/A1:6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C:6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[211]/D"#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X71Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT4=2 LUT6=1)j8fabric_clk_in rise@24.952ns - fabric_clk_in rise@0.000nsu֣@}AOBVJ=%@V@A=А=B5As<&?G!?h@p?z@??h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})h(rising edge-triggered cell FDRE clocked by fabric_clk_in {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk_in fabric_clk_in fabric_clk_in#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/QProp_HFF_SLICEL_C_Q JFDREXhzrO > =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[1]_13[16] Jnet (fo=49, routed)Xh~?i ;7i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4/I3 JXhzr :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4/OProp_B5LUT_SLICEL_I3_O JLUT4XhzrC> <8i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[230]_i_4_n_0 Jnet (fo=15, routed)XhW9?l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[211]_i_2__0/I0 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[211]_i_2__0/OProp_F6LUT_SLICEL_I0_O JLUT6Xhzr`P= ?;i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[211]_i_2__0_n_0 Jnet (fo=3, routed)XhT=l >:i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[211]_i_1__0/I3 JXhzr =9i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o[211]_i_1__0/OProp_C5LUT_SLICEL_I3_O JLUT4XhzrV-> =9i_tcds2_if/prbs_checker/cmp_prbs_gen/node_array[210]_6[1] Jnet (fo=1, routed)Xh1?l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[211]/D JFDREXhzrQ J(clock fabric_clk_in rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xh+G@O !i_tcds2_if/bufgce_clk_40_rx/I JXhzrt !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzrף> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhff@X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[17]/C JFDREXhzrQ J(clock fabric_clk_in rise edge)XhzrA WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzra i_tcds2_if/rxusrclk_out Jnet (fo=1861, routed)Xhj4@L !i_tcds2_if/bufgce_clk_40_rx/I JXht !i_tcds2_if/bufgce_clk_40_rx/OProp_BUFGCE_DIV_I_O J BUFGCE_DIVXhzr> :6i_tcds2_if/prbs_checker/cmp_prbs_gen/node_ff_reg[22]_1 Jnet (fo=792, routed)Xhg@X4Y2 (CLOCK_ROOT)l :6i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[211]/C JFDREXhzr> Jclock pessimismXhs<&?@ Jclock uncertaintyXh 84i_tcds2_if/prbs_checker/cmp_prbs_gen/data_o_reg[211]Setup_EFF_SLICEL_C_D JFDREXho=/ JXh< J required timeXhOB; J arrival timeXh</ JXh4 JslackXhB5A1 CLKFBOUTCLKFBOUT!Ë>@)yuȶ2@1Ë>8@9Ë>@Ayuȶ2@IË>8@hq}A>> fabric_clk_dcmfabric_clk_dcm!)Ë>(@1Ë>8@9AË>(@IË>8@hq}A??0 tx_wordclk_dcmtx_wordclk_dcm!)y@1y @9Ay@Iy @hq}^@@@< clk125clk125!)@1@9A@I@e1t?hq}B<B @AA rise - rise rise - rise   }ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[39]_srl32____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_30/CLK~zipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[42]_srl3____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_33/D"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsu >})\̿t<ٮ??<hff>X9>ʁ?>H?b(rising edge-triggered cell SRLC32E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) }ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[39]_srl32____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_30/Q31Prop_B6LUT_SLICEM_CLK_Q31 JSRLC32EXhzr> }ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[39]_srl32____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_30_n_1 Jnet (fo=1, routed)Xh ~zipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[42]_srl3____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_33/D JSRL16EXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)Xhٮ?X3Y4 (CLOCK_ROOT) }ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[39]_srl32____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_30/CLK JSRLC32EXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT) |ipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[42]_srl3____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_33/CLK JSRL16EXhzr> Jclock pessimismXhhff |xipb/udp_if/rx_packet_parser/ipbus_mask.pkt_mask_reg[42]_srl3____ipb_udp_if_rx_packet_parser_ipbus_mask.pkt_mask_reg_s_33Hold_A6LUT_SLICEM_CLK_D JSRL16EXh=/ JXh< J required timeXh)\; J arrival timeXhn?/ JXh4 JslackXh<P B>ipb/udp_if/tx_main/udp_build_data.udpram_end_addr_int_reg[7]/C:6ipb/udp_if/tx_main/state_machine.end_addr_int_reg[7]/D"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT5=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu&1>}{ο =|?{?G<ʡ==X9>n?>(?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) B>ipb/udp_if/tx_main/udp_build_data.udpram_end_addr_int_reg[7]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H= @ipb/udp_if/tx_main/udp_build_data.udpram_end_addr_int_reg[7]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrx ipb/udp_if/tx_main/CLKFBIN Jnet (fo=3804, routed)Xh{?X3Y4 (CLOCK_ROOT)l :6ipb/udp_if/tx_main/state_machine.end_addr_int_reg[7]/C JFDREXhzr> Jclock pessimismXh 84ipb/udp_if/tx_main/state_machine.end_addr_int_reg[7]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhˡ?/ JXh4 JslackXhG< 73ipb/udp_if/rx_packet_parser/rarp.pkt_mask_reg[37]/C3/ipb/udp_if/rx_packet_parser/rarp.pkt_drop_reg/D"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT6=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu&1>}pͿDЭ=?p?=!ʡ==X9>?>?_(rising edge-triggered cell FDSE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) 73ipb/udp_if/rx_packet_parser/rarp.pkt_mask_reg[37]/QProp_DFF2_SLICEL_C_Q JFDSEXhzf9H=z 73ipb/udp_if/rx_packet_parser/rarp.pkt_mask_reg[37]_0 Jnet (fo=4, routed)Xhw=b 40ipb/udp_if/rx_packet_parser/rarp.pkt_drop_i_1/I2 JXhzf 3/ipb/udp_if/rx_packet_parser/rarp.pkt_drop_i_1/OProp_D6LUT_SLICEL_I2_O JLUT6Xhzr<x 51ipb/udp_if/rx_packet_parser/rarp.pkt_drop_i_1_n_0 Jnet (fo=1, routed)Xho<e 3/ipb/udp_if/rx_packet_parser/rarp.pkt_drop_reg/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT)i 73ipb/udp_if/rx_packet_parser/rarp.pkt_mask_reg[37]/C JFDSEXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)Xhp?X3Y4 (CLOCK_ROOT)e 3/ipb/udp_if/rx_packet_parser/rarp.pkt_drop_reg/C JFDREXhzr> Jclock pessimismXh!{ 1-ipb/udp_if/rx_packet_parser/rarp.pkt_drop_regHold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh=4 B>eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/CB>eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6/D"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsun>}1ĿҿZ;_=T??=/D=[=X9>Ԉ?>`?_(rising edge-triggered cell FDPE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDPE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) B>eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/QProp_EFF2_SLICEL_C_Q JFDPEXhzrD= D@eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync_reg5 Jnet (fo=1, routed)Xh[=t B>eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6/D JFDPEXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr =9eth/phy/U0/transceiver_inst/reclock_encommaalign/userclk2 Jnet (fo=3804, routed)XhT?X3Y4 (CLOCK_ROOT)t B>eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/C JFDPEXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr =9eth/phy/U0/transceiver_inst/reclock_encommaalign/userclk2 Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT)t B>eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6/C JFDPEXhzr> Jclock pessimismXh/ @}7ÿѿ]=??`=.D=[=X9>b?>?_(rising edge-triggered cell FDPE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDPE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync5/QProp_EFF2_SLICEL_C_Q JFDPEXhzrD= C?eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync_reg5 Jnet (fo=1, routed)Xh[=s A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync6/D JFDPEXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr >:eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/rxuserclk2 Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT)s A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync5/C JFDPEXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr >:eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/rxuserclk2 Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT)s A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync6/C JFDPEXhzr> Jclock pessimismXh. ?;eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_RX/reset_sync6Hold_AFF2_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh7ÿ; J arrival timeXhl?/ JXh4 JslackXh`= 40ipb/udp_if/status/write_data.shift_buf_reg[20]/C40ipb/udp_if/status/write_data.shift_buf_reg[28]/D"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT5=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu>}3ο͏w=??_v =+;o= =X9>]?>?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) 40ipb/udp_if/status/write_data.shift_buf_reg[20]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=x 51ipb/udp_if/status_buffer/status_data_reg[7]_0[20] Jnet (fo=2, routed)Xh)\=m ?;ipb/udp_if/status_buffer/write_data.shift_buf[28]_i_1__0/I2 JXhzr >:ipb/udp_if/status_buffer/write_data.shift_buf[28]_i_1__0/OProp_D6LUT_SLICEL_I2_O JLUT5Xhzru<^ ipb/udp_if/status/D[20] Jnet (fo=1, routed)Xho<f 40ipb/udp_if/status/write_data.shift_buf_reg[28]/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrw ipb/udp_if/status/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT)f 40ipb/udp_if/status/write_data.shift_buf_reg[20]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrw ipb/udp_if/status/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT)f 40ipb/udp_if/status/write_data.shift_buf_reg[28]/C JFDREXhzr> Jclock pessimismXh+;| 2.ipb/udp_if/status/write_data.shift_buf_reg[28]Hold_DFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh3; J arrival timeXh?/ JXh4 JslackXh_v = {eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]/Cxteth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5/D"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsuY?}Lxos >#Y@os@ =;l=$>R^?-"@ -r?,6@_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125(DCD - SCD - CPR) {eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]/QProp_EFF2_SLICEL_C_Q JFDREXhzrl= c_eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/Q[7] Jnet (fo=8, routed)Xh$> xteth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5/D JSRL16EXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr A=eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/userclk2 Jnet (fo=3804, routed)Xh#Y@X3Y4 (CLOCK_ROOT) {eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr gceth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/userclk2 Jnet (fo=3804, routed)Xhos@X3Y4 (CLOCK_ROOT) zveth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5/CLK JSRL16EXhzr> Jclock pessimismXh; vreth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5Hold_H6LUT_SLICEM_CLK_D JSRL16EXhV>/ JXh< J required timeXhLx; J arrival timeXh~z@/ JXh4 JslackXh = .*eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[12]/C.*eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[20]/D"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT4=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsuX9>}jHǿ0=^??==-=X9>Xy?>T?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR){ .*eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[12]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=i &"eth/mac/i_mac/i_tx_CRC32D8/p_19_in Jnet (fo=2, routed)Xh=] /+eth/mac/i_mac/i_tx_CRC32D8/crc_i[20]_i_1/I2 JXhzr~ .*eth/mac/i_mac/i_tx_CRC32D8/crc_i[20]_i_1/OProp_H6LUT_SLICEL_I2_O JLUT4XhzrQ8=n +'eth/mac/i_mac/i_tx_CRC32D8/p_42_out[20] Jnet (fo=1, routed)XhD<` .*eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[20]/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr &"eth/mac/i_mac/i_tx_CRC32D8/CLKFBIN Jnet (fo=3804, routed)Xh^?X3Y4 (CLOCK_ROOT)` .*eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[12]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr &"eth/mac/i_mac/i_tx_CRC32D8/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT)` .*eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[20]/C JFDREXhzr> Jclock pessimismXhw ,(eth/mac/i_mac/i_tx_CRC32D8/crc_i_reg[20]Hold_HFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhjH; J arrival timeXh`?/ JXh4 JslackXh=y ;7ipb/udp_if/tx_main/do_ipbus_hdr.ipbus_hdr_int_reg[21]/C0,ipb/udp_if/status_buffer/ipbus_out_reg[21]/D"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsu;^:>}#O¿RοZ=w?R?zc=9H='1>X9>!?>̜?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) ;7ipb/udp_if/tx_main/do_ipbus_hdr.ipbus_hdr_int_reg[21]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H=e "ipb/udp_if/status_buffer/Q[21] Jnet (fo=3, routed)Xh'1>b 0,ipb/udp_if/status_buffer/ipbus_out_reg[21]/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrx ipb/udp_if/tx_main/CLKFBIN Jnet (fo=3804, routed)Xhw?X3Y4 (CLOCK_ROOT)m ;7ipb/udp_if/tx_main/do_ipbus_hdr.ipbus_hdr_int_reg[21]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr~ $ ipb/udp_if/status_buffer/CLKFBIN Jnet (fo=3804, routed)XhR?X3Y4 (CLOCK_ROOT)b 0,ipb/udp_if/status_buffer/ipbus_out_reg[21]/C JFDREXhzr> Jclock pessimismXhy .*ipb/udp_if/status_buffer/ipbus_out_reg[21]Hold_HFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh#O¿; J arrival timeXh? ?/ JXh4 JslackXhzc= :6ipb/udp_if/RARP_block/data_block.data_buffer_reg[47]/C73ipb/udp_if/RARP_block/data_block.we_buffer_reg[2]/D"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu;^:>}'1ȿP=?'1?x={=X9=X9>z?>E?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fastclk125clk125clk125(DCD - SCD - CPR) :6ipb/udp_if/RARP_block/data_block.data_buffer_reg[47]/QProp_EFF_SLICEL_C_Q JFDREXhzr9H=l )%ipb/udp_if/RARP_block/data_buffer[47] Jnet (fo=2, routed)XhP=f 84ipb/udp_if/RARP_block/data_block.we_buffer[2]_i_1/I1 JXhzr 73ipb/udp_if/RARP_block/data_block.we_buffer[2]_i_1/OProp_G6LUT_SLICEL_I1_O JLUT2XhzrQ8=| 95ipb/udp_if/RARP_block/data_block.we_buffer[2]_i_1_n_0 Jnet (fo=1, routed)XhA`e<i 73ipb/udp_if/RARP_block/data_block.we_buffer_reg[2]/D JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr{ !ipb/udp_if/RARP_block/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT)l :6ipb/udp_if/RARP_block/data_block.data_buffer_reg[47]/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr{ !ipb/udp_if/RARP_block/CLKFBIN Jnet (fo=3804, routed)Xh'1?X3Y4 (CLOCK_ROOT)i 73ipb/udp_if/RARP_block/data_block.we_buffer_reg[2]/C JFDREXhzr> Jclock pessimismXh{ 51ipb/udp_if/RARP_block/data_block.we_buffer_reg[2]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXhth?/ JXh4 JslackXhx= ($eth/mac/i_mac/emacclientrxdvld_reg/Csoipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[107]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76/CE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1 LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsui@}A.A'1XKs@'1X@AY=А==1t?ڥ=>0ݰ@ -r?l7@R^? @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)u ($eth/mac/i_mac/emacclientrxdvld_reg/QProp_AFF_SLICEL_C_Q JFDREXhzf)\>o *&ipb/udp_if/rx_reset_block/mac_rx_valid Jnet (fo=302, routed)XhSC@^ 0,ipb/udp_if/rx_reset_block/set_addr_i_1__1/I1 JXhzf /+ipb/udp_if/rx_reset_block/set_addr_i_1__1/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr1,>h #ipb/udp_if/rx_reset_block/SR[0] Jnet (fo=682, routed)Xhˡ?e 73ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/I0 JXhzr 62ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/OProp_C5LUT_SLICEL_I0_O JLUT3Xhzr@>| 84ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 Jnet (fo=97, routed)Xh+? soipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[107]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76/CE JSRL16EXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrs eth/mac/i_mac/CLKFBIN Jnet (fo=3804, routed)Xhs@X3Y4 (CLOCK_ROOT)Z ($eth/mac/i_mac/emacclientrxdvld_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)Xh'1X@X3Y4 (CLOCK_ROOT) tpipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[107]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76/CLK JSRL16EXhzr> Jclock pessimismXhڥ=@ Jclock uncertaintyXhY plipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[107]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76Setup_A6LUT_SLICEM_CLK_CE JSRL16EXhl/ JXh< J required timeXh.A; J arrival timeXh(\/ JXh4 JslackXh1t? ($eth/mac/i_mac/emacclientrxdvld_reg/Ctpipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[110]_srl11___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_85/CE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1 LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsui@}A.A'1XKs@'1X@AY=А==1t?ڥ=>0ݰ@ -r?l7@R^? @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)u ($eth/mac/i_mac/emacclientrxdvld_reg/QProp_AFF_SLICEL_C_Q JFDREXhzf)\>o *&ipb/udp_if/rx_reset_block/mac_rx_valid Jnet (fo=302, routed)XhSC@^ 0,ipb/udp_if/rx_reset_block/set_addr_i_1__1/I1 JXhzf /+ipb/udp_if/rx_reset_block/set_addr_i_1__1/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr1,>h #ipb/udp_if/rx_reset_block/SR[0] Jnet (fo=682, routed)Xhˡ?e 73ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/I0 JXhzr 62ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/OProp_C5LUT_SLICEL_I0_O JLUT3Xhzr@>| 84ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 Jnet (fo=97, routed)Xh+? tpipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[110]_srl11___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_85/CE JSRL16EXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrs eth/mac/i_mac/CLKFBIN Jnet (fo=3804, routed)Xhs@X3Y4 (CLOCK_ROOT)Z ($eth/mac/i_mac/emacclientrxdvld_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)Xh'1X@X3Y4 (CLOCK_ROOT) uqipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[110]_srl11___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_85/CLK JSRL16EXhzr> Jclock pessimismXhڥ=@ Jclock uncertaintyXhY qmipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[110]_srl11___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_85Setup_B6LUT_SLICEM_CLK_CE JSRL16EXhl/ JXh< J required timeXh.A; J arrival timeXh(\/ JXh4 JslackXh1t? ($eth/mac/i_mac/emacclientrxdvld_reg/Crnipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[67]_srl3___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_77/CE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1 LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsui@}A.A'1XKs@'1X@AY=А==1t?ڥ=>0ݰ@ -r?l7@R^? @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)u ($eth/mac/i_mac/emacclientrxdvld_reg/QProp_AFF_SLICEL_C_Q JFDREXhzf)\>o *&ipb/udp_if/rx_reset_block/mac_rx_valid Jnet (fo=302, routed)XhSC@^ 0,ipb/udp_if/rx_reset_block/set_addr_i_1__1/I1 JXhzf /+ipb/udp_if/rx_reset_block/set_addr_i_1__1/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr1,>h #ipb/udp_if/rx_reset_block/SR[0] Jnet (fo=682, routed)Xhˡ?e 73ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/I0 JXhzr 62ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/OProp_C5LUT_SLICEL_I0_O JLUT3Xhzr@>| 84ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 Jnet (fo=97, routed)Xh+? rnipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[67]_srl3___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_77/CE JSRL16EXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrs eth/mac/i_mac/CLKFBIN Jnet (fo=3804, routed)Xhs@X3Y4 (CLOCK_ROOT)Z ($eth/mac/i_mac/emacclientrxdvld_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)Xh'1X@X3Y4 (CLOCK_ROOT) soipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[67]_srl3___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_77/CLK JSRL16EXhzr> Jclock pessimismXhڥ=@ Jclock uncertaintyXhY okipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[67]_srl3___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_77Setup_C6LUT_SLICEM_CLK_CE JSRL16EXhl/ JXh< J required timeXh.A; J arrival timeXh(\/ JXh4 JslackXh1t? ($eth/mac/i_mac/emacclientrxdvld_reg/Crnipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[90]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76/CE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1 LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsui@}A.A'1XKs@'1X@AY=А==1t?ڥ=>0ݰ@ -r?l7@R^? @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)u ($eth/mac/i_mac/emacclientrxdvld_reg/QProp_AFF_SLICEL_C_Q JFDREXhzf)\>o *&ipb/udp_if/rx_reset_block/mac_rx_valid Jnet (fo=302, routed)XhSC@^ 0,ipb/udp_if/rx_reset_block/set_addr_i_1__1/I1 JXhzf /+ipb/udp_if/rx_reset_block/set_addr_i_1__1/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr1,>h #ipb/udp_if/rx_reset_block/SR[0] Jnet (fo=682, routed)Xhˡ?e 73ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/I0 JXhzr 62ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/OProp_C5LUT_SLICEL_I0_O JLUT3Xhzr@>| 84ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 Jnet (fo=97, routed)Xh+? rnipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[90]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76/CE JSRL16EXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrs eth/mac/i_mac/CLKFBIN Jnet (fo=3804, routed)Xhs@X3Y4 (CLOCK_ROOT)Z ($eth/mac/i_mac/emacclientrxdvld_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)Xh'1X@X3Y4 (CLOCK_ROOT) soipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[90]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76/CLK JSRL16EXhzr> Jclock pessimismXhڥ=@ Jclock uncertaintyXhY okipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[90]_srl2___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_76Setup_D6LUT_SLICEM_CLK_CE JSRL16EXhl/ JXh< J required timeXh.A; J arrival timeXh(\/ JXh4 JslackXh1t? ($eth/mac/i_mac/emacclientrxdvld_reg/Csoipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[105]_srl4___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_78/CE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1 LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu @}A).AXks@X@AY=А==?ڥ=>A@ -r?l7@R^? @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)u ($eth/mac/i_mac/emacclientrxdvld_reg/QProp_AFF_SLICEL_C_Q JFDREXhzf)\>o *&ipb/udp_if/rx_reset_block/mac_rx_valid Jnet (fo=302, routed)XhSC@^ 0,ipb/udp_if/rx_reset_block/set_addr_i_1__1/I1 JXhzf /+ipb/udp_if/rx_reset_block/set_addr_i_1__1/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr1,>h #ipb/udp_if/rx_reset_block/SR[0] Jnet (fo=682, routed)Xhˡ?e 73ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/I0 JXhzr 62ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/OProp_C5LUT_SLICEL_I0_O JLUT3Xhzr@>| 84ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 Jnet (fo=97, routed)Xhj? soipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[105]_srl4___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_78/CE JSRL16EXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrs eth/mac/i_mac/CLKFBIN Jnet (fo=3804, routed)Xhs@X3Y4 (CLOCK_ROOT)Z ($eth/mac/i_mac/emacclientrxdvld_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)XhX@X3Y4 (CLOCK_ROOT) tpipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[105]_srl4___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_78/CLK JSRL16EXhzr> Jclock pessimismXhڥ=@ Jclock uncertaintyXhY plipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[105]_srl4___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_78Setup_A6LUT_SLICEM_CLK_CE JSRL16EXhl/ JXh< J required timeXh).A; J arrival timeXhV/ JXh4 JslackXh? ($eth/mac/i_mac/emacclientrxdvld_reg/Crnipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[72]_srl5___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_79/CE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1 LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu @}A).AXks@X@AY=А==?ڥ=>A@ -r?l7@R^? @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)u ($eth/mac/i_mac/emacclientrxdvld_reg/QProp_AFF_SLICEL_C_Q JFDREXhzf)\>o *&ipb/udp_if/rx_reset_block/mac_rx_valid Jnet (fo=302, routed)XhSC@^ 0,ipb/udp_if/rx_reset_block/set_addr_i_1__1/I1 JXhzf /+ipb/udp_if/rx_reset_block/set_addr_i_1__1/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr1,>h #ipb/udp_if/rx_reset_block/SR[0] Jnet (fo=682, routed)Xhˡ?e 73ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/I0 JXhzr 62ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/OProp_C5LUT_SLICEL_I0_O JLUT3Xhzr@>| 84ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 Jnet (fo=97, routed)Xhj? rnipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[72]_srl5___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_79/CE JSRL16EXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrs eth/mac/i_mac/CLKFBIN Jnet (fo=3804, routed)Xhs@X3Y4 (CLOCK_ROOT)Z ($eth/mac/i_mac/emacclientrxdvld_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)XhX@X3Y4 (CLOCK_ROOT) soipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[72]_srl5___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_79/CLK JSRL16EXhzr> Jclock pessimismXhڥ=@ Jclock uncertaintyXhY okipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[72]_srl5___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_79Setup_B6LUT_SLICEM_CLK_CE JSRL16EXhl/ JXh< J required timeXh).A; J arrival timeXhV/ JXh4 JslackXh? ($eth/mac/i_mac/emacclientrxdvld_reg/Crnipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[92]_srl6___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_80/CE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1 LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu @}A).AXks@X@AY=А==?ڥ=>A@ -r?l7@R^? @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)u ($eth/mac/i_mac/emacclientrxdvld_reg/QProp_AFF_SLICEL_C_Q JFDREXhzf)\>o *&ipb/udp_if/rx_reset_block/mac_rx_valid Jnet (fo=302, routed)XhSC@^ 0,ipb/udp_if/rx_reset_block/set_addr_i_1__1/I1 JXhzf /+ipb/udp_if/rx_reset_block/set_addr_i_1__1/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr1,>h #ipb/udp_if/rx_reset_block/SR[0] Jnet (fo=682, routed)Xhˡ?e 73ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/I0 JXhzr 62ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/OProp_C5LUT_SLICEL_I0_O JLUT3Xhzr@>| 84ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 Jnet (fo=97, routed)Xhj? rnipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[92]_srl6___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_80/CE JSRL16EXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrs eth/mac/i_mac/CLKFBIN Jnet (fo=3804, routed)Xhs@X3Y4 (CLOCK_ROOT)Z ($eth/mac/i_mac/emacclientrxdvld_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)XhX@X3Y4 (CLOCK_ROOT) soipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[92]_srl6___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_80/CLK JSRL16EXhzr> Jclock pessimismXhڥ=@ Jclock uncertaintyXhY okipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[92]_srl6___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_80Setup_C6LUT_SLICEM_CLK_CE JSRL16EXhl/ JXh< J required timeXh).A; J arrival timeXhV/ JXh4 JslackXh? ($eth/mac/i_mac/emacclientrxdvld_reg/Crnipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[93]_srl7___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_81/CE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1 LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu @}A).AXks@X@AY=А==?ڥ=>A@ -r?l7@R^? @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})a(rising edge-triggered cell SRL16E clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)u ($eth/mac/i_mac/emacclientrxdvld_reg/QProp_AFF_SLICEL_C_Q JFDREXhzf)\>o *&ipb/udp_if/rx_reset_block/mac_rx_valid Jnet (fo=302, routed)XhSC@^ 0,ipb/udp_if/rx_reset_block/set_addr_i_1__1/I1 JXhzf /+ipb/udp_if/rx_reset_block/set_addr_i_1__1/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr1,>h #ipb/udp_if/rx_reset_block/SR[0] Jnet (fo=682, routed)Xhˡ?e 73ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/I0 JXhzr 62ipb/udp_if/rx_reset_block/rarp.pkt_data[125]_i_1/OProp_C5LUT_SLICEL_I0_O JLUT3Xhzr@>| 84ipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[125]_0 Jnet (fo=97, routed)Xhj? rnipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[93]_srl7___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_81/CE JSRL16EXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrs eth/mac/i_mac/CLKFBIN Jnet (fo=3804, routed)Xhs@X3Y4 (CLOCK_ROOT)Z ($eth/mac/i_mac/emacclientrxdvld_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)XhX@X3Y4 (CLOCK_ROOT) soipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[93]_srl7___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_81/CLK JSRL16EXhzr> Jclock pessimismXhڥ=@ Jclock uncertaintyXhY okipb/udp_if/rx_packet_parser/rarp.pkt_data_reg[93]_srl7___ipb_udp_if_rx_packet_parser_rarp.pkt_data_reg_r_81Setup_D6LUT_SLICEM_CLK_CE JSRL16EXhl/ JXh< J required timeXh).A; J arrival timeXhV/ JXh4 JslackXh?V ($eth/mac/i_mac/emacclientrxdvld_reg/Cjfipb/udp_if/rx_packet_parser/arp.pkt_data_reg[100]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_75/CE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1 LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu23@}A E4AnSAྵs@nS@AY=А==k?ڥ=>+@ -r?l7@R^?Yd@_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)u ($eth/mac/i_mac/emacclientrxdvld_reg/QProp_AFF_SLICEL_C_Q JFDREXhzf)\>o *&ipb/udp_if/rx_reset_block/mac_rx_valid Jnet (fo=302, routed)XhSC@^ 0,ipb/udp_if/rx_reset_block/set_addr_i_1__1/I1 JXhzf /+ipb/udp_if/rx_reset_block/set_addr_i_1__1/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr1,>h #ipb/udp_if/rx_reset_block/SR[0] Jnet (fo=682, routed)Xh^I?c 51ipb/udp_if/rx_reset_block/arp.pkt_data[31]_i_1/I0 JXhzr 40ipb/udp_if/rx_reset_block/arp.pkt_data[31]_i_1/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrX9=z 62ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[31]_0 Jnet (fo=87, routed)Xh? jfipb/udp_if/rx_packet_parser/arp.pkt_data_reg[100]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_75/CE JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrs eth/mac/i_mac/CLKFBIN Jnet (fo=3804, routed)Xhs@X3Y4 (CLOCK_ROOT)Z ($eth/mac/i_mac/emacclientrxdvld_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)XhnS@X3Y4 (CLOCK_ROOT) ieipb/udp_if/rx_packet_parser/arp.pkt_data_reg[100]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_75/C JFDREXhzr> Jclock pessimismXhڥ=@ Jclock uncertaintyXhY gcipb/udp_if/rx_packet_parser/arp.pkt_data_reg[100]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_75Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh E4A; J arrival timeXh / JXh4 JslackXhk?R ($eth/mac/i_mac/emacclientrxdvld_reg/Cieipb/udp_if/rx_packet_parser/arp.pkt_data_reg[59]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_70/CE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1 LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu23@}A E4AnSAྵs@nS@AY=А==k?ڥ=>+@ -r?l7@R^?Yd@_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slowclk125clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)u ($eth/mac/i_mac/emacclientrxdvld_reg/QProp_AFF_SLICEL_C_Q JFDREXhzf)\>o *&ipb/udp_if/rx_reset_block/mac_rx_valid Jnet (fo=302, routed)XhSC@^ 0,ipb/udp_if/rx_reset_block/set_addr_i_1__1/I1 JXhzf /+ipb/udp_if/rx_reset_block/set_addr_i_1__1/OProp_D5LUT_SLICEL_I1_O JLUT2Xhzr1,>h #ipb/udp_if/rx_reset_block/SR[0] Jnet (fo=682, routed)Xh^I?c 51ipb/udp_if/rx_reset_block/arp.pkt_data[31]_i_1/I0 JXhzr 40ipb/udp_if/rx_reset_block/arp.pkt_data[31]_i_1/OProp_C6LUT_SLICEL_I0_O JLUT3XhzrX9=z 62ipb/udp_if/rx_packet_parser/arp.pkt_data_reg[31]_0 Jnet (fo=87, routed)Xh? ieipb/udp_if/rx_packet_parser/arp.pkt_data_reg[59]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_70/CE JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzrs eth/mac/i_mac/CLKFBIN Jnet (fo=3804, routed)Xhs@X3Y4 (CLOCK_ROOT)Z ($eth/mac/i_mac/emacclientrxdvld_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr '#ipb/udp_if/rx_packet_parser/CLKFBIN Jnet (fo=3804, routed)XhnS@X3Y4 (CLOCK_ROOT) hdipb/udp_if/rx_packet_parser/arp.pkt_data_reg[59]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_70/C JFDREXhzr> Jclock pessimismXhڥ=@ Jclock uncertaintyXhY fbipb/udp_if/rx_packet_parser/arp.pkt_data_reg[59]_ipb_udp_if_rx_packet_parser_arp.pkt_data_reg_r_70Setup_BFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh E4A; J arrival timeXh / JXh4 JslackXhk? clk250clk250!)?1@9A?I@eb">hq}&,=$?pBB rise - rise rise - rise  RNstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLKuqstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[24]"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@0.000ns - clk250 rise@0.000nsuSc>}ſ033>u??&,=jP==E>V?'1?sh?e(rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})g(rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) TPstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/P[42]!Prop_DSP_OUTPUT_DSP48E2_CLK_P[42] J DSP_OUTPUTXhzr= c_stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/A[24] Jnet (fo=1, routed)Xh= uqstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[24] J DSP_A_B_DATAXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr B>stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/CLK Jnet (fo=17714, routed)Xhu?X3Y3 (CLOCK_ROOT) RNstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK J DSP_OUTPUTXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr a]stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/CLK Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT) sostat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CLK J DSP_A_B_DATAXhzr> Jclock pessimismXhjP okstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST#Hold_DSP_A_B_DATA_DSP48E2_CLK_A[24] J DSP_A_B_DATAXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh&,= RNstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLKuqstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[23]"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@0.000ns - clk250 rise@0.000nsuSc>}ſ033>u??zj<=jP"==E>V?'1?sh?e(rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})g(rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) TPstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/P[41]!Prop_DSP_OUTPUT_DSP48E2_CLK_P[41] J DSP_OUTPUTXhzr"= c_stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/A[23] Jnet (fo=1, routed)Xh= uqstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[23] J DSP_A_B_DATAXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr B>stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/CLK Jnet (fo=17714, routed)Xhu?X3Y3 (CLOCK_ROOT) RNstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK J DSP_OUTPUTXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr a]stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/CLK Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT) sostat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CLK J DSP_A_B_DATAXhzr> Jclock pessimismXhjP okstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST#Hold_DSP_A_B_DATA_DSP48E2_CLK_A[23] J DSP_A_B_DATAXho:/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhzj<= RNstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLKuqstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[29]"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@0.000ns - clk250 rise@0.000nsuxi>}wſ033>u??%@=jPl=> =E>V?'1?sh?e(rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})g(rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) TPstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/P[47]!Prop_DSP_OUTPUT_DSP48E2_CLK_P[47] J DSP_OUTPUTXhzrl= c_stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/A[29] Jnet (fo=1, routed)Xh> = uqstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[29] J DSP_A_B_DATAXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr B>stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/CLK Jnet (fo=17714, routed)Xhu?X3Y3 (CLOCK_ROOT) RNstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK J DSP_OUTPUTXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr a]stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/CLK Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT) sostat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CLK J DSP_A_B_DATAXhzr> Jclock pessimismXhjP okstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST#Hold_DSP_A_B_DATA_DSP48E2_CLK_A[29] J DSP_A_B_DATAXh;/ JXh< J required timeXhw; J arrival timeXh?/ JXh4 JslackXh%@=0 84g_clock_rate_din[40].i_rate_ngccm_status0/P0_q_reg/C51g_clock_rate_din[40].i_rate_ngccm_status0/q_reg/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT2=1)j)clk250 rise@0.000ns - clk250 rise@0.000nsu=`=}  ף;33??[P=p=o=D=E>C+?'1?N?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) 84g_clock_rate_din[40].i_rate_ngccm_status0/P0_q_reg/QProp_DFF_SLICEL_C_Q JFDREXhzr9H=u 2.g_clock_rate_din[40].i_rate_ngccm_status0/P0_q Jnet (fo=1, routed)Xho=h :6g_clock_rate_din[40].i_rate_ngccm_status0/q_i_1__39/I1 JXhzr 95g_clock_rate_din[40].i_rate_ngccm_status0/q_i_1__39/OProp_C6LUT_SLICEL_I1_O JLUT2Xhzru<t 0,g_clock_rate_din[40].i_rate_ngccm_status0/q0 Jnet (fo=33, routed)Xho<g 51g_clock_rate_din[40].i_rate_ngccm_status0/q_reg/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[40].i_rate_ngccm_status0/clk250 Jnet (fo=17714, routed)Xh33?X3Y3 (CLOCK_ROOT)j 84g_clock_rate_din[40].i_rate_ngccm_status0/P0_q_reg/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[40].i_rate_ngccm_status0/clk250 Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT)g 51g_clock_rate_din[40].i_rate_ngccm_status0/q_reg/C JFDREXhzr> Jclock pessimismXhp=} 3/g_clock_rate_din[40].i_rate_ngccm_status0/q_regHold_CFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXh7?/ JXh4 JslackXh[P=! RNstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLKuqstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[22]"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@0.000ns - clk250 rise@0.000nsuGa>}@5ſ033>u??[P=jP==E>V?'1?sh?e(rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})g(rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) TPstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/P[40]!Prop_DSP_OUTPUT_DSP48E2_CLK_P[40] J DSP_OUTPUTXhzr= c_stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/A[22] Jnet (fo=1, routed)Xh= uqstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/A[22] J DSP_A_B_DATAXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr B>stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/CLK Jnet (fo=17714, routed)Xhu?X3Y3 (CLOCK_ROOT) RNstat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK J DSP_OUTPUTXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr a]stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/CLK Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT) sostat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST/CLK J DSP_A_B_DATAXhzr> Jclock pessimismXhjP okstat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst/DSP_A_B_DATA_INST#Hold_DSP_A_B_DATA_DSP48E2_CLK_A[22] J DSP_A_B_DATAXhĻ/ JXh< J required timeXh@5; J arrival timeXhk?/ JXh4 JslackXh[P= B>stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/reset_r_reg[1]/CEAstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst_reg[1]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j)clk250 rise@0.000ns - clk250 rise@0.000nsu>}Zʱ#=Q?ʱ?e=E"=D=E>5?'1?[d[?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) B>stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/reset_r_reg[1]/QProp_FFF_SLICEL_C_Q JFDREXhzr9H={ 84stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/p_5_in Jnet (fo=2, routed)XhP=t FBstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst[1]_i_1/I1 JXhzr EAstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst[1]_i_1/OProp_C5LUT_SLICEL_I1_O JLUT3XhzrGa= GCstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst[1]_i_1_n_0 Jnet (fo=1, routed)XhX94<w EAstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst_reg[1]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 84stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/clk250 Jnet (fo=17714, routed)XhQ?X3Y3 (CLOCK_ROOT)t B>stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/reset_r_reg[1]/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 84stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/clk250 Jnet (fo=17714, routed)Xhʱ?X3Y3 (CLOCK_ROOT)w EAstat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst_reg[1]/C JFDREXhzr> Jclock pessimismXhE" C?stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/d_sync_rst_reg[1]Hold_CFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhZ; J arrival timeXhƫ?/ JXh4 JslackXhe=@ mistat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[0].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C=9stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[0]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT2=1)j)clk250 rise@0.000ns - clk250 rise@0.000nsu7>} Χ =َ?Χ? zp=qr=Y=E>^"?'1?lG?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) mistat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[0].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=~ ;7stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_sync_0 Jnet (fo=2, routed)Xhw=l >:stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d[0]_i_1/I1 JXhzr =9stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d[0]_i_1/OProp_G6LUT_SLICEL_I1_O JLUT2XhzrY= =9stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/p_3_out[0] Jnet (fo=1, routed)XhA`e<o =9stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[0]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr _[stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[0].g_cdc.xpm_cdc_single_inst/dest_clk Jnet (fo=17714, routed)Xhَ?X3Y3 (CLOCK_ROOT) mistat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/g_sync[0].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 95stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/clk250 Jnet (fo=17714, routed)XhΧ?X3Y3 (CLOCK_ROOT)o =9stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[0]/C JFDREXhzr> Jclock pessimismXhqr ;7stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/d_reg[0]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh ; J arrival timeXh^?/ JXh4 JslackXh zp=@ mistat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/g_sync[2].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C=9stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_reg[2]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT2=1)j)clk250 rise@0.000ns - clk250 rise@0.000nsuS>}mQ =d;?Q?}t=x =Ga=E>S#?'1?rH?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) mistat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/g_sync[2].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD=~ ;7stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_sync_2 Jnet (fo=2, routed)Xhw=l >:stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d[2]_i_1/I1 JXhzr =9stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d[2]_i_1/OProp_H6LUT_SLICEL_I1_O JLUT2XhzrT= =9stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/p_3_out[2] Jnet (fo=1, routed)Xho<o =9stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_reg[2]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr _[stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/g_sync[2].g_cdc.xpm_cdc_single_inst/dest_clk Jnet (fo=17714, routed)Xhd;?X3Y3 (CLOCK_ROOT) mistat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/g_sync[2].g_cdc.xpm_cdc_single_inst/syncstages_ff_reg[3]/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 95stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/clk250 Jnet (fo=17714, routed)XhQ?X3Y3 (CLOCK_ROOT)o =9stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_reg[2]/C JFDREXhzr> Jclock pessimismXhx  ;7stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/d_reg[2]Hold_HFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhm; J arrival timeXho?/ JXh4 JslackXh}t== .*stat_regs_inst/i_cntr_rst_ctrl/SR_reg[1]/COKstat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst/DSP_A_B_DATA_INST/B[1]"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@0.000ns - clk250 rise@0.000nsur>}a尿!c=?a?u=Ŗ9H=ʡ=E>6?'1?Y?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})g(rising edge-triggered cell DSP_A_B_DATA clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR){ .*stat_regs_inst/i_cntr_rst_ctrl/SR_reg[1]/QProp_EFF_SLICEL_C_Q JFDREXhzr9H= =9stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst/B[1] Jnet (fo=12, routed)Xhʡ= OKstat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst/DSP_A_B_DATA_INST/B[1] J DSP_A_B_DATAXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT)` .*stat_regs_inst/i_cntr_rst_ctrl/SR_reg[1]/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr <8stat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst/CLK Jnet (fo=17714, routed)Xha?X3Y3 (CLOCK_ROOT) NJstat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst/DSP_A_B_DATA_INST/CLK J DSP_A_B_DATAXhzr> Jclock pessimismXhŖ JFstat_regs_inst/i_cntr_rst_ctrl/g_DSP[1].DSP48E2_inst/DSP_A_B_DATA_INST"Hold_DSP_A_B_DATA_DSP48E2_CLK_B[1] J DSP_A_B_DATAXh/ JXh< J required timeXh; J arrival timeXhX?/ JXh4 JslackXhu=  B>stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/reset_r_reg[1]/CEAstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst_reg[1]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j)clk250 rise@0.000ns - clk250 rise@0.000nsu >}پ>c=?پ?u=D+0=9H=E>XM?'1?u?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250clk250clk250(DCD - SCD - CPR) B>stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/reset_r_reg[1]/QProp_FFF_SLICEM_C_Q JFDREXhzr9H={ 84stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/p_5_in Jnet (fo=2, routed)Xh=t FBstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst[1]_i_1/I1 JXhzr EAstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst[1]_i_1/OProp_C5LUT_SLICEM_I1_O JLUT3XhzrGa= GCstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst[1]_i_1_n_0 Jnet (fo=1, routed)XhX94<w EAstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst_reg[1]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 84stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/clk250 Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT)t B>stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/reset_r_reg[1]/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 84stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/clk250 Jnet (fo=17714, routed)Xhپ?X3Y3 (CLOCK_ROOT)w EAstat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst_reg[1]/C JFDREXhzr> Jclock pessimismXhD+0 C?stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/d_sync_rst_reg[1]Hold_CFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhu= -)stat_regs_inst/reset_count_rate_reg_rep/CSOstat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuRF@}@Z@&I#a@&I@@d=А==b"> =)\>=@?;@+?"?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})e(rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)z -)stat_regs_inst/reset_count_rate_reg_rep/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> C?stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/RSTP Jnet (fo=32, routed)Xh=@ SOstat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP J DSP_OUTPUTXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzrt stat_regs_inst/clk250 Jnet (fo=17714, routed)Xh#a@X3Y3 (CLOCK_ROOT)_ -)stat_regs_inst/reset_count_rate_reg_rep/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr B>stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/CLK Jnet (fo=17714, routed)Xh&I@X3Y3 (CLOCK_ROOT) RNstat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK J DSP_OUTPUTXhzr> Jclock pessimismXh =@ Jclock uncertaintyXhd NJstat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST!Setup_DSP_OUTPUT_DSP48E2_CLK_RSTP J DSP_OUTPUTXhVξ/ JXh< J required timeXhZ@; J arrival timeXhI/ JXh4 JslackXhb"> ; 51g_clock_rate_din[23].i_rate_ngccm_status0/q_reg/C>:g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[5]/CE"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsu{@}@@/LW>lO@/L@@d=А==©#>*D>V>Gr@?I?+?G@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[23].i_rate_ngccm_status0/q_reg/QProp_EFF_SLICEL_C_Q JFDREXhzrV>v 2.g_clock_rate_din[23].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)XhGr@p >:g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[5]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[23].i_rate_ngccm_status0/clk250 Jnet (fo=17714, routed)XhlO@X3Y3 (CLOCK_ROOT)g 51g_clock_rate_din[23].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[23].i_rate_ngccm_status2/clk250 Jnet (fo=17714, routed)Xh/L@X3Y3 (CLOCK_ROOT)o =9g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[5]/C JFDREXhzr> Jclock pessimismXh*D>@ Jclock uncertaintyXhd ;7g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[5]Setup_AFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXh@; J arrival timeXh/ JXh4 JslackXh©#>b? 51g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C?;g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[21]/CE"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuq@}@dR@EKGa=N@EK@@d=А=='$>=V>`h@?K7?+? @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/QProp_DFF_SLICEM_C_Q JFDREXhzrV>v 2.g_clock_rate_din[24].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)Xh`h@q ?;g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[21]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[24].i_rate_ngccm_status0/clk250 Jnet (fo=17714, routed)XhN@X3Y3 (CLOCK_ROOT)g 51g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[24].i_rate_ngccm_status2/clk250 Jnet (fo=17714, routed)XhEK@X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[21]/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhd <8g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[21]Setup_DFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhdR@; J arrival timeXh&1/ JXh4 JslackXh'$>b? 51g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C?;g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[28]/CE"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuq@}@dR@EKGa=N@EK@@d=А=='$>=V>`h@?K7?+? @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/QProp_DFF_SLICEM_C_Q JFDREXhzrV>v 2.g_clock_rate_din[24].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)Xh`h@q ?;g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[28]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[24].i_rate_ngccm_status0/clk250 Jnet (fo=17714, routed)XhN@X3Y3 (CLOCK_ROOT)g 51g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[24].i_rate_ngccm_status2/clk250 Jnet (fo=17714, routed)XhEK@X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[28]/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhd <8g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[28]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhdR@; J arrival timeXh&1/ JXh4 JslackXh'$>b; 51g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C>:g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[6]/CE"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuq@}@dR@EKGa=N@EK@@d=А=='$>=V>`h@?K7?+? @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/QProp_DFF_SLICEM_C_Q JFDREXhzrV>v 2.g_clock_rate_din[24].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)Xh`h@p >:g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[6]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[24].i_rate_ngccm_status0/clk250 Jnet (fo=17714, routed)XhN@X3Y3 (CLOCK_ROOT)g 51g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[24].i_rate_ngccm_status2/clk250 Jnet (fo=17714, routed)XhEK@X3Y3 (CLOCK_ROOT)o =9g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[6]/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhd ;7g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[6]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhdR@; J arrival timeXh&1/ JXh4 JslackXh'$>b; 51g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C>:g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[8]/CE"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuq@}@dR@EKGa=N@EK@@d=А=='$>=V>`h@?K7?+? @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/QProp_DFF_SLICEM_C_Q JFDREXhzrV>v 2.g_clock_rate_din[24].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)Xh`h@p >:g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[8]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[24].i_rate_ngccm_status0/clk250 Jnet (fo=17714, routed)XhN@X3Y3 (CLOCK_ROOT)g 51g_clock_rate_din[24].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[24].i_rate_ngccm_status2/clk250 Jnet (fo=17714, routed)XhEK@X3Y3 (CLOCK_ROOT)o =9g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[8]/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhd ;7g_clock_rate_din[24].i_rate_ngccm_status2/rate_i_reg[8]Setup_AFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhdR@; J arrival timeXh&1/ JXh4 JslackXh'$>b )%stat_regs_inst/reset_count_rate_reg/CRNstat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsu_1@}@@z4b#a@z4@@d=А==9'> =V>(@?;@+??_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})e(rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)v )%stat_regs_inst/reset_count_rate_reg/QProp_BFF_SLICEL_C_Q JFDREXhzrV> B>stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/RSTP Jnet (fo=32, routed)Xh(@ RNstat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP J DSP_OUTPUTXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzrt stat_regs_inst/clk250 Jnet (fo=17714, routed)Xh#a@X3Y3 (CLOCK_ROOT)[ )%stat_regs_inst/reset_count_rate_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr A=stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/CLK Jnet (fo=17714, routed)Xhz4@X3Y3 (CLOCK_ROOT) QMstat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK J DSP_OUTPUTXhzr> Jclock pessimismXh =@ Jclock uncertaintyXhd MIstat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST!Setup_DSP_OUTPUT_DSP48E2_CLK_RSTP J DSP_OUTPUTXhVξ/ JXh< J required timeXh@; J arrival timeXh/ JXh4 JslackXh9'>  -)stat_regs_inst/reset_count_rate_reg_rep/CSOstat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuRF@}@@I+#a@I@@d=А==SF)> =)\>=@?;@+?0?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})e(rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)z -)stat_regs_inst/reset_count_rate_reg_rep/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> C?stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/RSTP Jnet (fo=32, routed)Xh=@ SOstat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP J DSP_OUTPUTXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzrt stat_regs_inst/clk250 Jnet (fo=17714, routed)Xh#a@X3Y3 (CLOCK_ROOT)_ -)stat_regs_inst/reset_count_rate_reg_rep/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr B>stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/CLK Jnet (fo=17714, routed)XhI@X3Y3 (CLOCK_ROOT) RNstat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK J DSP_OUTPUTXhzr> Jclock pessimismXh =@ Jclock uncertaintyXhd NJstat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST!Setup_DSP_OUTPUT_DSP48E2_CLK_RSTP J DSP_OUTPUTXhVξ/ JXh< J required timeXh@; J arrival timeXhI/ JXh4 JslackXhSF)>  )%stat_regs_inst/reset_count_rate_reg/CRNstat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuX1@}@.@Z4w#a@Z4@@d=А==R+> =V>r(@?;@+?6?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})e(rising edge-triggered cell DSP_OUTPUT clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)v )%stat_regs_inst/reset_count_rate_reg/QProp_BFF_SLICEL_C_Q JFDREXhzrV> B>stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/RSTP Jnet (fo=32, routed)Xhr(@ RNstat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/RSTP J DSP_OUTPUTXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzrt stat_regs_inst/clk250 Jnet (fo=17714, routed)Xh#a@X3Y3 (CLOCK_ROOT)[ )%stat_regs_inst/reset_count_rate_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr A=stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/CLK Jnet (fo=17714, routed)XhZ4@X3Y3 (CLOCK_ROOT) QMstat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST/CLK J DSP_OUTPUTXhzr> Jclock pessimismXh =@ Jclock uncertaintyXhd MIstat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst/DSP_OUTPUT_INST!Setup_DSP_OUTPUT_DSP48E2_CLK_RSTP J DSP_OUTPUTXhVξ/ JXh< J required timeXh.@; J arrival timeXh/ JXh4 JslackXhR+> ; 51g_clock_rate_din[23].i_rate_ngccm_status0/q_reg/C>:g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[0]/CE"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj)clk250 rise@4.000ns - clk250 rise@0.000nsuz@}@@CLsR>lO@CL@@d=А==+>*D>V>J r@?I?+?@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250clk250clk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 51g_clock_rate_din[23].i_rate_ngccm_status0/q_reg/QProp_EFF_SLICEL_C_Q JFDREXhzrV>v 2.g_clock_rate_din[23].i_rate_ngccm_status2/E[0] Jnet (fo=98, routed)XhJ r@p >:g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[0]/CE JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[23].i_rate_ngccm_status0/clk250 Jnet (fo=17714, routed)XhlO@X3Y3 (CLOCK_ROOT)g 51g_clock_rate_din[23].i_rate_ngccm_status0/q_reg/C JFDREXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[23].i_rate_ngccm_status2/clk250 Jnet (fo=17714, routed)XhCL@X3Y3 (CLOCK_ROOT)o =9g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[0]/C JFDREXhzr> Jclock pessimismXh*D>@ Jclock uncertaintyXhd ;7g_clock_rate_din[23].i_rate_ngccm_status2/rate_i_reg[0]Setup_DFF_SLICEM_C_CE JFDREXh/]/ JXh< J required timeXh@; J arrival timeXh// JXh4 JslackXh+>b  fabric_clk fabric_clk!)Ë>(@1Ë>8@9AË>(@IË>8@e1Ahq} < o=6ACC? rise - rise rise - rise  q <8SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/DoSleep_reg/CB>SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[4]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu>}͒t~ׄ> [@~@<">>lg?!@~j|?x>@e(rising edge-triggered cell FDCE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) <8SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/DoSleep_reg/QProp_DFF_SLICEM_C_Q JFDCEXhzrl= <8SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reg_o[9] Jnet (fo=35, routed)XhSc>u GCSFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount[4]_i_1__39/I2 JXhzr FBSFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount[4]_i_1__39/OProp_C6LUT_SLICEM_I2_O JLUT6Xhzrt= HDSFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount[4]_i_1__39_n_0 Jnet (fo=1, routed)Xh)\=t B>SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[4]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 95SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/fabric_clk Jnet (fo=103803, routed)Xh [@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]n <8SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/DoSleep_reg/C JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 95SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/fabric_clk Jnet (fo=103803, routed)Xh~@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]t B>SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[4]/C JFDPEXhzr> Jclock pessimismXh @/ JXh< J required timeXh͒t; J arrival timeXhvv@/ JXh4 JslackXh<#[ PLSFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[14]/CPLSFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[13]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu'>}R˿׿=??(<Dʡ={=>6^?sh>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) PLSFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[14]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= ZVSFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/TDIBits_reg[13]_0 Jnet (fo=1, routed)Xh= _[SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/TDIBits[13]_i_1__19/I0 JXhzr ^ZSFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/TDIBits[13]_i_1__19/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzr< MISFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM_n_50 Jnet (fo=1, routed)XhD< PLSFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[13]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr IESFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] PLSFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[14]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr IESFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] PLSFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[13]/C JFDREXhzr> Jclock pessimismXhD NJSFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDIBits_reg[13]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhR˿; J arrival timeXh?/ JXh4 JslackXh(<suqSFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/CuqSFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu/$>}Xɿz=/?X? =<1 ==>Iz?sh>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) uqSFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/QProp_AFF_SLICEL_C_Q JFDREXhzf9H= eaSFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/c_state__0_0[0] Jnet (fo=15, routed)XhT= {wSFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[2]_i_1__415/I4 JXhzf zvSFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[2]_i_1__415/OProp_B6LUT_SLICEM_I4_O JLUT6Xhzro< |xSFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[2]_i_1__415_n_0 Jnet (fo=1, routed)Xhu< uqSFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr `\SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xh/?X2Y4 (CLOCK_ROOT) uqSFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr `\SFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)XhX?X2Y4 (CLOCK_ROOT) uqSFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/C JFDREXhzr> Jclock pessimismXh1  soSFP_GEN[32].ngCCM_gbt/i2c_gen[11].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]Hold_BFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh =< WSSFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[6]/CSOSFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[6]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT4=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu">}b ſGѿW=z?G?f<n:==>k?sh>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) WSSFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[6]/QProp_DFF_SLICEL_C_Q JFDREXhzr9H= SOSFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/dout[6] Jnet (fo=2, routed)Xhw= b^SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/wb_dat_o[6]_i_1__30/I3 JXhzr a]SFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/wb_dat_o[6]_i_1__30/OProp_D6LUT_SLICEM_I3_O JLUT4Xhzro< MISFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o[6] Jnet (fo=1, routed)Xho< SOSFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[6]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr VRSFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/fabric_clk Jnet (fo=103803, routed)Xhz?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] WSSFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[6]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr LHSFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/fabric_clk Jnet (fo=103803, routed)XhG?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] SOSFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[6]/C JFDREXhzr> Jclock pessimismXhn: QMSFP_GEN[15].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[6]Hold_DFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhb ſ; J arrival timeXh?/ JXh4 JslackXhf< MISFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/cr_reg[5]/CXTSFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_reg/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT4=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu6$>}ͪ ˿Sk=ٮ? ?{<%=:=>@5~?sh>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) MISFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/cr_reg[5]/QProp_EFF2_SLICEM_C_Q JFDREXhzrD= FBSFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/read Jnet (fo=7, routed)Xh1= ]YSFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_i_1__18/I3 JXhzr \XSFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_i_1__18/OProp_G6LUT_SLICEM_I3_O JLUT4Xhzru< ^ZSFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_i_1__18_n_0 Jnet (fo=1, routed)XhA`e< XTSFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_reg/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr LHSFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/fabric_clk Jnet (fo=103803, routed)Xhٮ?X2Y4 (CLOCK_ROOT) MISFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/cr_reg[5]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr LHSFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/fabric_clk Jnet (fo=103803, routed)Xh ?X2Y4 (CLOCK_ROOT) XTSFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_reg/C JFDREXhzr> Jclock pessimismXh VRSFP_GEN[14].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/st_irq_block.tip_regHold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhͪ; J arrival timeXht?/ JXh4 JslackXh{< IESFP_GEN[17].ngCCM_gbt/IPbus_gen[6].IPbus_local_inst/write_local_reg/CMISFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr_reg[3]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu?5>}sſ-ҿ& =o?-?<Dv==>S?sh>ҝ?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) IESFP_GEN[17].ngCCM_gbt/IPbus_gen[6].IPbus_local_inst/write_local_reg/QProp_CFF_SLICEM_C_Q JFDREXhzrD= MISFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/write_local Jnet (fo=5, routed)Xh1= SOSFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__290/I3 JXhzr RNSFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__290/OProp_B6LUT_SLICEL_I3_O JLUT6Xhzr< TPSFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__290_n_0 Jnet (fo=1, routed)Xhu< MISFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr_reg[3]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr A=SFP_GEN[17].ngCCM_gbt/IPbus_gen[6].IPbus_local_inst/clk_local Jnet (fo=103803, routed)Xho?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]{ IESFP_GEN[17].ngCCM_gbt/IPbus_gen[6].IPbus_local_inst/write_local_reg/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr LHSFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/fabric_clk Jnet (fo=103803, routed)Xh-?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] MISFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr_reg[3]/C JFDREXhzr> Jclock pessimismXhD KGSFP_GEN[17].ngCCM_gbt/i2c_gen[6].LocalI2CBridge_fe/i2c_master/cr_reg[3]Hold_BFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhsſ; J arrival timeXh_?/ JXh4 JslackXh< NJSFP_GEN[30].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/DataIn_local_reg[11]/CMISFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr_reg[3]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu>}䛽̿w=R??#<w3o==>}?sh>u?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) NJSFP_GEN[30].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/DataIn_local_reg[11]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H= QMSFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/DataIn_local[9] Jnet (fo=1, routed)Xh)\= RNSFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__84/I0 JXhzr QMSFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__84/OProp_A6LUT_SLICEL_I0_O JLUT6Xhzru< SOSFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__84_n_0 Jnet (fo=1, routed)XhD< MISFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr_reg[3]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr A=SFP_GEN[30].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/clk_local Jnet (fo=103803, routed)XhR?X2Y4 (CLOCK_ROOT) NJSFP_GEN[30].ngCCM_gbt/IPbus_gen[1].IPbus_local_inst/DataIn_local_reg[11]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr LHSFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT) MISFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr_reg[3]/C JFDREXhzr> Jclock pessimismXhw3 KGSFP_GEN[30].ngCCM_gbt/i2c_gen[1].LocalI2CBridge_fe/i2c_master/cr_reg[3]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh䛽; J arrival timeXhsh?/ JXh4 JslackXh#<[ KGSFP_GEN[37].ngCCM_gbt/IPbus_gen[7].IPbus_local_inst/addr_local_reg[0]/CSOSFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT4=1)j1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu 0>}=ÿο =%??uM<>v==>G?sh>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) KGSFP_GEN[37].ngCCM_gbt/IPbus_gen[7].IPbus_local_inst/addr_local_reg[0]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD= YUSFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/addr_local[0] Jnet (fo=17, routed)Xh= c_SFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/wb_dat_o[7]_i_1__246/I2 JXhzr b^SFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/wb_dat_o[7]_i_1__246/OProp_A6LUT_SLICEM_I2_O JLUT4Xhzr< MISFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o[7] Jnet (fo=1, routed)XhD< SOSFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr A=SFP_GEN[37].ngCCM_gbt/IPbus_gen[7].IPbus_local_inst/clk_local Jnet (fo=103803, routed)Xh%?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]} KGSFP_GEN[37].ngCCM_gbt/IPbus_gen[7].IPbus_local_inst/addr_local_reg[0]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr LHSFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] SOSFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]/C JFDREXhzr> Jclock pessimismXh> QMSFP_GEN[37].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/wb_dat_o_reg[7]Hold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh=ÿ; J arrival timeXh> ?/ JXh4 JslackXhuM<p PLSFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[28]/CPLSFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[27]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu+>}Ŀпvf=??;<XD=F=>43?sh>(?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) PLSFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[28]/QProp_HFF2_SLICEM_C_Q JFDREXhzrD= IESFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/p_0_in[27] Jnet (fo=2, routed)XhF= PLSFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[27]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr IESFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] PLSFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[28]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr IESFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] PLSFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[27]/C JFDREXhzr> Jclock pessimismXhX NJSFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/TDOBits_reg[27]Hold_BFF2_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhĿ; J arrival timeXhQ?/ JXh4 JslackXh;< NJSFP_GEN[34].ngCCM_gbt/IPbus_gen[10].IPbus_local_inst/DataIn_local_reg[1]/COKSFP_GEN[34].ngCCM_gbt/i2c_gen[10].LocalI2CBridge_fe/i2c_master/txr_reg[1]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsun>})IHʿA+j=̬?H?]<6D=[=>z?sh>+?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast fabric_clk fabric_clk fabric_clk(DCD - SCD - CPR) NJSFP_GEN[34].ngCCM_gbt/IPbus_gen[10].IPbus_local_inst/DataIn_local_reg[1]/QProp_EFF2_SLICEL_C_Q JFDREXhzrD= RNSFP_GEN[34].ngCCM_gbt/i2c_gen[10].LocalI2CBridge_fe/i2c_master/DataIn_local[1] Jnet (fo=1, routed)Xh[= OKSFP_GEN[34].ngCCM_gbt/i2c_gen[10].LocalI2CBridge_fe/i2c_master/txr_reg[1]/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr B>SFP_GEN[34].ngCCM_gbt/IPbus_gen[10].IPbus_local_inst/clk_local Jnet (fo=103803, routed)Xh̬?X2Y4 (CLOCK_ROOT) NJSFP_GEN[34].ngCCM_gbt/IPbus_gen[10].IPbus_local_inst/DataIn_local_reg[1]/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr MISFP_GEN[34].ngCCM_gbt/i2c_gen[10].LocalI2CBridge_fe/i2c_master/fabric_clk Jnet (fo=103803, routed)XhH?X2Y4 (CLOCK_ROOT) OKSFP_GEN[34].ngCCM_gbt/i2c_gen[10].LocalI2CBridge_fe/i2c_master/txr_reg[1]/C JFDREXhzr> Jclock pessimismXh6 MISFP_GEN[34].ngCCM_gbt/i2c_gen[10].LocalI2CBridge_fe/i2c_master/txr_reg[1]Hold_AFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh)I; J arrival timeXh?/ JXh4 JslackXh]<fi2c_clk_en_reg_rep__17/CtpSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]/CE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuxUA}AjAb=!b@b@A~>А={>1A=>uPA~j|?#@lg?`(@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) جʾ%b@-lg?5i i2c_clk_en_reg_rep__17/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhVIAD JXhSLR Crossing[1->0] yuSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/I5 JXhzr xtSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> zvSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440_n_0 Jnet (fo=6, routed)Xh֣> tpSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]/CE JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)Xh!b@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N i2c_clk_en_reg_rep__17/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr ^ZSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xhb@X2Y4 (CLOCK_ROOT) soSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]/C JFDREXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhجʾ@ Jclock uncertaintyXh~ qmSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[1]Setup_HFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhjA; J arrival timeXho/ JXh4 JslackXh1Afi2c_clk_en_reg_rep__17/CtpSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]/CE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuxUA}AjAb=!b@b@A~>А={>1A=>uPA~j|?#@lg?`(@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) جʾ%b@-lg?5i i2c_clk_en_reg_rep__17/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhVIAD JXhSLR Crossing[1->0] yuSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/I5 JXhzr xtSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> zvSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440_n_0 Jnet (fo=6, routed)Xh֣> tpSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]/CE JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)Xh!b@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N i2c_clk_en_reg_rep__17/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr ^ZSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xhb@X2Y4 (CLOCK_ROOT) soSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]/C JFDREXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhجʾ@ Jclock uncertaintyXh~ qmSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[4]Setup_GFF_SLICEL_C_CE JFDREXhGa/ JXh< J required timeXhjA; J arrival timeXho/ JXh4 JslackXh1Afi2c_clk_en_reg_rep__17/CtpSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/CE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuTA}AAb =!b@b@A~>А={>m2A=>1PA~j|?#@lg?)@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ʾ%b@-lg?5i i2c_clk_en_reg_rep__17/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhVIAD JXhSLR Crossing[1->0] yuSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/I5 JXhzr xtSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> zvSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440_n_0 Jnet (fo=6, routed)Xhe;> tpSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/CE JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)Xh!b@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N i2c_clk_en_reg_rep__17/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr ^ZSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xhb@X2Y4 (CLOCK_ROOT) soSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]/C JFDREXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhʾ@ Jclock uncertaintyXh~ qmSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[0]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhA; J arrival timeXh̆/ JXh4 JslackXhm2Afi2c_clk_en_reg_rep__17/CtpSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/CE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuTA}AAb =!b@b@A~>А={>Ӛ2A=>"OA~j|?#@lg?)@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ʾ%b@-lg?5i i2c_clk_en_reg_rep__17/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhVIAD JXhSLR Crossing[1->0] yuSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/I5 JXhzr xtSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> zvSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440_n_0 Jnet (fo=6, routed)Xh> tpSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/CE JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)Xh!b@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N i2c_clk_en_reg_rep__17/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr ^ZSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xhb@X2Y4 (CLOCK_ROOT) soSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]/C JFDREXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhʾ@ Jclock uncertaintyXh~ qmSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[2]Setup_CFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhA; J arrival timeXhF/ JXh4 JslackXhӚ2Afi2c_clk_en_reg_rep__17/CtpSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]/CE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuTA}AAb =!b@b@A~>А={>Ӛ2A=>"OA~j|?#@lg?)@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ʾ%b@-lg?5i i2c_clk_en_reg_rep__17/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhVIAD JXhSLR Crossing[1->0] yuSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/I5 JXhzr xtSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> zvSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440_n_0 Jnet (fo=6, routed)Xh> tpSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]/CE JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)Xh!b@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N i2c_clk_en_reg_rep__17/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr ^ZSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xhb@X2Y4 (CLOCK_ROOT) soSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]/C JFDREXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhʾ@ Jclock uncertaintyXh~ qmSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state_reg[3]Setup_BFF_SLICEL_C_CE JFDREXh/]/ JXh< J required timeXhA; J arrival timeXhF/ JXh4 JslackXhӚ2A(i2c_clk_en_reg_rep__17/Cb^SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1 LUT6=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsu> UA}AAHb|=!b@Hb@A~>А={>,4A=>|MA~j|?#@lg?%)@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) *ʾ%Hb@-lg?5 i i2c_clk_en_reg_rep__17/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhVIAD JXhSLR Crossing[1->0] yuSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/I5 JXhzr xtSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440/OProp_G6LUT_SLICEL_I5_O JLUT6Xhzr)> zvSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/FSM_sequential_c_state[4]_i_1__440_n_0 Jnet (fo=6, routed)Xhw> hdSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_i_1__440/I1 JXhzr gcSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_i_1__440/OProp_D6LUT_SLICEL_I1_O JLUT3Xhzr)> ieSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_i_1__440_n_0 Jnet (fo=1, routed)Xh*\= b^SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)Xh!b@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N i2c_clk_en_reg_rep__17/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr ^ZSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)XhHb@X2Y4 (CLOCK_ROOT) b^SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_reg/C JFDREXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh*ʾ@ Jclock uncertaintyXh~ `\SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/iscl_oen_regSetup_DFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXhA; J arrival timeXh#ۆ/ JXh4 JslackXh,4A\i2c_clk_en_reg_rep__17/Cb^SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1 LUT6=2)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuSA}AA5^b(=!b@5^b@A~>А={>85A=$>OMA~j|?#@lg?(@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 6ʾ%5^b@-lg?5i i2c_clk_en_reg_rep__17/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhHAD JXhSLR Crossing[1->0] gcSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/sda_chk_i_3__440/I5 JXhzr fbSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/sda_chk_i_3__440/OProp_F6LUT_SLICEL_I5_O JLUT6Xhzr>v 3/SFP_GEN[8].ngCCM_gbt/Sync_TX_Reset/isda_oen_reg Jnet (fo=2, routed)Xh'>i ;7SFP_GEN[8].ngCCM_gbt/Sync_TX_Reset/isda_oen_i_5__440/I2 JXhzr :6SFP_GEN[8].ngCCM_gbt/Sync_TX_Reset/isda_oen_i_5__440/OProp_E6LUT_SLICEL_I2_O JLUT3XhzrL= b^SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg_0 Jnet (fo=1, routed)Xh)\= hdSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__440/I3 JXhzr gcSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__440/OProp_C6LUT_SLICEL_I3_O JLUT6Xhzr`P= ieSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_i_1__440_n_0 Jnet (fo=1, routed)XhP= b^SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/D JFDREXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)Xh!b@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N i2c_clk_en_reg_rep__17/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr ^ZSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xh5^b@X2Y4 (CLOCK_ROOT) b^SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_reg/C JFDREXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh6ʾ@ Jclock uncertaintyXh~ `\SFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/isda_oen_regSetup_CFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXhA; J arrival timeXh/ JXh4 JslackXh85A/i2c_clk_en_reg_rep__17/ClhSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[6]/CE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuPA}AAb&=!b@b@A~>А={>Y6A=>JA~j|?#@lg?(@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDSE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ʾ%b@-lg?5i i2c_clk_en_reg_rep__17/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhE@AD JXhSLR Crossing[1->0] qmSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440/I1 JXhzr plSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440/OProp_F6LUT_SLICEL_I1_O JLUT3Xhzr֣p> rnSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440_n_0 Jnet (fo=8, routed)XhA`%? lhSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[6]/CE JFDSEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)Xh!b@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N i2c_clk_en_reg_rep__17/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr ^ZSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xhb@X2Y4 (CLOCK_ROOT) kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[6]/C JFDSEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhʾ@ Jclock uncertaintyXh~ ieSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[6]Setup_HFF2_SLICEL_C_CE JFDSEXhim/ JXh< J required timeXhA; J arrival timeXhף/ JXh4 JslackXhY6A.i2c_clk_en_reg_rep__17/ClhSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[7]/CE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuBPA}A(Ab&=!b@b@A~>А={>6A=>DJA~j|?#@lg?(@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDSE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ʾ%b@-lg?5i i2c_clk_en_reg_rep__17/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhE@AD JXhSLR Crossing[1->0] qmSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440/I1 JXhzr plSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440/OProp_F6LUT_SLICEL_I1_O JLUT3Xhzr֣p> rnSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440_n_0 Jnet (fo=8, routed)XhZ$? lhSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[7]/CE JFDSEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)Xh!b@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N i2c_clk_en_reg_rep__17/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr ^ZSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xhb@X2Y4 (CLOCK_ROOT) kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[7]/C JFDSEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhʾ@ Jclock uncertaintyXh~ ieSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[7]Setup_EFF_SLICEL_C_CE JFDSEXhGa/ JXh< J required timeXh(A; J arrival timeXh/ JXh4 JslackXh6A/i2c_clk_en_reg_rep__17/ClhSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[3]/CE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsugOA}AAa*\=!b@a@A~>А={>!7A=>hIA~j|?#@lg?c(@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell FDSE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow fabric_clk fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) Aɾ%a@-lg?5i i2c_clk_en_reg_rep__17/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[1]_0 Jnet (fo=132, routed)XhE@AD JXhSLR Crossing[1->0] qmSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440/I1 JXhzr plSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440/OProp_F6LUT_SLICEL_I1_O JLUT3Xhzr֣p> rnSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt[1]_i_1__440_n_0 Jnet (fo=8, routed)Xhk? lhSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[3]/CE JFDSEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)Xh!b@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N i2c_clk_en_reg_rep__17/C JFDREXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr ^ZSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/fabric_clk Jnet (fo=103803, routed)Xha@X2Y4 (CLOCK_ROOT) kgSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[3]/C JFDSEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhAɾ@ Jclock uncertaintyXh~ ieSFP_GEN[8].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_cnt_reg[3]Setup_CFF2_SLICEL_C_CE JFDSEXhGa/ JXh< J required timeXhA; J arrival timeXh/ JXh4 JslackXh!7A ipb_clkipb_clk!)/@1?@9A/@I?@e`K>hq}<pA DDA rise - rise rise - rise   LHSFP_GEN[21].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[1]/C}ySFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[1]"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsuK7>}利0ݴ=ff?0ݴ?<D=$>x?gff>c?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) LHSFP_GEN[21].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[1]/QProp_GFF2_SLICEL_C_Q JFDCEXhzrD= RNSFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/dinb[1] Jnet (fo=2, routed)Xh$> }ySFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[1] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr =9SFP_GEN[21].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/CLK Jnet (fo=204776, routed)Xhff?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]~ LHSFP_GEN[21].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[1]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204776, routed)Xh0ݴ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xSFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh rnSFP_GEN[21].ngFEC_module/bram_array[9].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0)Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[1] JRAMB36E2Xhi</ JXh< J required timeXh利; J arrival timeXhO?/ JXh4 JslackXh<t B>SFP_GEN[31].ngFEC_module/buffer_ngccm_jtag/ngccm_din_reg[16]/C|SFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINPBDINP[0]"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsuX9>} (=/?(?<D='1>gff?gff>)\?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) B>SFP_GEN[31].ngFEC_module/buffer_ngccm_jtag/ngccm_din_reg[16]/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= TPSFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/dinb[16] Jnet (fo=2, routed)Xh'1> |SFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINPBDINP[0] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[31].ngFEC_module/buffer_ngccm_jtag/CLK Jnet (fo=204776, routed)Xh/?X2Y4 (CLOCK_ROOT)t B>SFP_GEN[31].ngFEC_module/buffer_ngccm_jtag/ngccm_din_reg[16]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr PLSFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204776, routed)Xh(?X2Y4 (CLOCK_ROOT) }ySFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh soSFP_GEN[31].ngFEC_module/bram_array[12].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0+Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINPBDINP[0] JRAMB36E2Xhi</ JXh< J required timeXh ; J arrival timeXhZ?/ JXh4 JslackXh<u LHSFP_GEN[31].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[9]/CvrSFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DINADIN[9]"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsu;^:>} Ȯ(=C?(? <vD=L7 >G?gff>)\?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB18E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) LHSFP_GEN[31].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[9]/QProp_CFF2_SLICEM_C_Q JFDCEXhzrD= RNSFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/dina[9] Jnet (fo=2, routed)XhL7 > vrSFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DINADIN[9] JRAMB18E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr =9SFP_GEN[31].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/CLK Jnet (fo=204776, routed)XhC?X2Y4 (CLOCK_ROOT)~ LHSFP_GEN[31].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[9]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/clka Jnet (fo=204776, routed)Xh(?X2Y4 (CLOCK_ROOT) uqSFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB18E2Xhzr> Jclock pessimismXhv kgSFP_GEN[31].ngFEC_module/bram_array[5].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg,Hold_RAMB18E2_U_RAMB181_CLKBWRCLK_DINADIN[9] JRAMB18E2Xhi</ JXh< J required timeXh Ȯ; J arrival timeXh]?/ JXh4 JslackXh < MISFP_GEN[27].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/ngccm_din_reg[26]/C}ySFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[8]"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsu >}Lxly=~?x?:<!D=> =&a?gff>?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) MISFP_GEN[27].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/ngccm_din_reg[26]/QProp_EFF2_SLICEL_C_Q JFDCEXhzrD= SOSFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/dinb[26] Jnet (fo=2, routed)Xh> = }ySFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[8] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr =9SFP_GEN[27].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/CLK Jnet (fo=204776, routed)Xh~?X2Y4 (CLOCK_ROOT) MISFP_GEN[27].ngFEC_module/i2c_comm_gen[8].buffer_ngccm/ngccm_din_reg[26]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204776, routed)Xhx?X2Y4 (CLOCK_ROOT) |xSFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh! rnSFP_GEN[27].ngFEC_module/bram_array[8].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1)Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[8] JRAMB36E2Xhi</ JXh< J required timeXhL; J arrival timeXh|?/ JXh4 JslackXh:< MISFP_GEN[32].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[14]/C~zSFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[14]"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsuE6>}殿I}=m?I?Q<-9H=>?gff>|?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) MISFP_GEN[32].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[14]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= SOSFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/dinb[14] Jnet (fo=2, routed)Xh> ~zSFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[14] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr =9SFP_GEN[32].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/CLK Jnet (fo=204776, routed)Xhm?X2Y4 (CLOCK_ROOT) MISFP_GEN[32].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[14]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204776, routed)XhI?X2Y4 (CLOCK_ROOT) |xSFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh- rnSFP_GEN[32].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0*Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[14] JRAMB36E2Xhi</ JXh< J required timeXh殿; J arrival timeXh"?/ JXh4 JslackXhQ< LHSFP_GEN[9].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[24]/C|xSFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[6]"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsuϡE>} F >)\??<39H=t>B`?gff>F?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) LHSFP_GEN[9].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[24]/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= RNSFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/dinb[24] Jnet (fo=2, routed)Xht> |xSFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[6] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr <8SFP_GEN[9].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/CLK Jnet (fo=204776, routed)Xh)\?X2Y4 (CLOCK_ROOT)~ LHSFP_GEN[9].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[24]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr NJSFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204776, routed)Xh?X2Y4 (CLOCK_ROOT) {wSFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh3 qmSFP_GEN[9].ngFEC_module/bram_array[3].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1)Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[6] JRAMB36E2Xhi</ JXh< J required timeXh F; J arrival timeXhc?/ JXh4 JslackXh<{ MISFP_GEN[1].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[12]/CwsSFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DINADIN[12]"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsuv>}'1o=??Z<K9H="=?gff>?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB18E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) MISFP_GEN[1].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[12]/QProp_DFF_SLICEM_C_Q JFDCEXhzr9H= SOSFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/dina[12] Jnet (fo=2, routed)Xh"= wsSFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DINADIN[12] JRAMB18E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr =9SFP_GEN[1].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/CLK Jnet (fo=204776, routed)Xh?X2Y4 (CLOCK_ROOT) MISFP_GEN[1].ngFEC_module/i2c_comm_gen[11].buffer_ngccm/ngccm_din_reg[12]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/clka Jnet (fo=204776, routed)Xh?X2Y4 (CLOCK_ROOT) uqSFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK JRAMB18E2Xhzr> Jclock pessimismXhK kgSFP_GEN[1].ngFEC_module/bram_array[11].RAM/BRAM_h/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg-Hold_RAMB18E2_L_RAMB180_CLKBWRCLK_DINADIN[12] JRAMB18E2Xhi</ JXh< J required timeXh'; J arrival timeXh?/ JXh4 JslackXhZ< MISFP_GEN[47].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[26]/C}ySFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[8]"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsu>}锿>=}???<D==,V?gff>Ȇ?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) MISFP_GEN[47].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[26]/QProp_GFF2_SLICEL_C_Q JFDCEXhzrD= SOSFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/dinb[26] Jnet (fo=2, routed)Xh= }ySFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[8] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr =9SFP_GEN[47].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/CLK Jnet (fo=204776, routed)Xh}??X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] MISFP_GEN[47].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[26]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204776, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xSFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh rnSFP_GEN[47].ngFEC_module/bram_array[7].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1)Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[8] JRAMB36E2Xhi</ JXh< J required timeXh锿; J arrival timeXh;?/ JXh4 JslackXh< @}5K >В??<$D=z>q?gff>Ȗ?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) @ ~zSFP_GEN[18].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/DINBDIN[2] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[18].ngFEC_module/bkp_buffer_ngccm/CLK Jnet (fo=204776, routed)XhВ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]r @1] }ySFP_GEN[18].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh$ soSFP_GEN[18].ngFEC_module/bram_array[13].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_0)Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[2] JRAMB36E2Xhi</ JXh< J required timeXh5; J arrival timeXh ?/ JXh4 JslackXh< MISFP_GEN[26].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[29]/C~zSFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[11]"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsuj<>}lpS>?p?#<9H=p= > ?gff>ף?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkipb_clkipb_clk(DCD - SCD - CPR) MISFP_GEN[26].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[29]/QProp_BFF_SLICEM_C_Q JFDCEXhzr9H= SOSFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/dinb[29] Jnet (fo=2, routed)Xhp= > ~zSFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/DINBDIN[11] JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr =9SFP_GEN[26].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/CLK Jnet (fo=204776, routed)Xh?X2Y4 (CLOCK_ROOT) MISFP_GEN[26].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[29]/C JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr OKSFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/clka Jnet (fo=204776, routed)Xhp?X2Y4 (CLOCK_ROOT) |xSFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1/CLKBWRCLK JRAMB36E2Xhzr> Jclock pessimismXh rnSFP_GEN[26].ngFEC_module/bram_array[5].RAM/BRAM_l/xpm_memory_base_inst/gen_wr_b.gen_word_narrow.mem_reg_bram_1*Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[11] JRAMB36E2Xhi</ JXh< J required timeXhl; J arrival timeXhX9?/ JXh4 JslackXh#< $ ipb/trans/sm/rmw_result_reg[8]/COKSFP_GEN[43].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[8]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsu A}Bc B9(pxI@9(@Bڭ=А=>`K>D=ˡE>vAc?t#@ ?@b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %9(@- ?5q $ ipb/trans/sm/rmw_result_reg[8]/QProp_HFF_SLICEL_C_Q JFDREXhzrO >m ($ipb/trans/iface/regs_reg[126][31][8] Jnet (fo=688, routed)Xh'1AD JXhSLR Crossing[0->1]\ .*ipb/trans/iface/input_size_i[8]_i_1__75/I4 JXhzr} -)ipb/trans/iface/input_size_i[8]_i_1__75/OProp_B6LUT_SLICEM_I4_O JLUT6XhzrGa= SOSFP_GEN[43].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[12]_1[6] Jnet (fo=1, routed)XhC = OKSFP_GEN[43].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[8]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrp ipb/trans/sm/CLK Jnet (fo=204776, routed)XhxI@X2Y4 (CLOCK_ROOT)V $ ipb/trans/sm/rmw_result_reg[8]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr =9SFP_GEN[43].ngFEC_module/bram_array[11].buffer_server/CLK Jnet (fo=204776, routed)Xh9(@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] OKSFP_GEN[43].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhD=E Jinter-SLR compensationXh@ Jclock uncertaintyXhڭ MISFP_GEN[43].ngFEC_module/bram_array[11].buffer_server/input_size_i_reg[8]Setup_BFF_SLICEM_C_D JFDCEXh}=/ JXh< J required timeXhc B; J arrival timeXh/ JXh4 JslackXh`K>51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLKOKSFP_GEN[38].ngFEC_module/bram_array[13].buffer_server/input_size_i_reg[8]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1 RAMB36E2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsu,A}B B>>q@>@Bڭ=А=>~?D=(\?jAc?K@ ?1@f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) =%>@- ?5  73ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0]*Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0] JRAMB36E2XhzrV?s 0,ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 Jnet (fo=1, routed)Xhu<d 62ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CASDINB[0] JXhzr 84ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0],Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0] JRAMB36E2Xhzre;_>b ipb/trans/iface/rx_dob[8] Jnet (fo=698, routed)Xh5^AD JXhSLR Crossing[0->1]] /+ipb/trans/iface/input_size_i[8]_i_1__147/I0 JXhzr~ .*ipb/trans/iface/input_size_i[8]_i_1__147/OProp_A6LUT_SLICEM_I0_O JLUT6XhzrL= SOSFP_GEN[38].ngFEC_module/bram_array[13].buffer_server/input_size_i_reg[12]_2[6] Jnet (fo=1, routed)Xh< OKSFP_GEN[38].ngFEC_module/bram_array[13].buffer_server/input_size_i_reg[8]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr{ ipb/udp_if/ipbus_rx_ram/CLK Jnet (fo=204776, routed)Xhq@X2Y4 (CLOCK_ROOT)k 51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr =9SFP_GEN[38].ngFEC_module/bram_array[13].buffer_server/CLK Jnet (fo=204776, routed)Xh>@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] OKSFP_GEN[38].ngFEC_module/bram_array[13].buffer_server/input_size_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhD=E Jinter-SLR compensationXh=@ Jclock uncertaintyXhڭ MISFP_GEN[38].ngFEC_module/bram_array[13].buffer_server/input_size_i_reg[8]Setup_AFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXh B; J arrival timeXhu/ JXh4 JslackXh~?51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLKNJSFP_GEN[38].ngFEC_module/bram_array[5].buffer_server/input_size_i_reg[8]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1 RAMB36E2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsu,A}B BhE$q@hE@Bڭ=А=>z?D=~ @MbAc?K@ ?"@f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) &þ%hE@- ?5  73ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0]*Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0] JRAMB36E2XhzrV?s 0,ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 Jnet (fo=1, routed)Xhu<d 62ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CASDINB[0] JXhzr 84ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0],Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0] JRAMB36E2Xhzre;_>b ipb/trans/iface/rx_dob[8] Jnet (fo=698, routed)XhAD JXhSLR Crossing[0->1]] /+ipb/trans/iface/input_size_i[8]_i_1__139/I0 JXhzr~ .*ipb/trans/iface/input_size_i[8]_i_1__139/OProp_B6LUT_SLICEL_I0_O JLUT6XhzrA`> RNSFP_GEN[38].ngFEC_module/bram_array[5].buffer_server/input_size_i_reg[12]_1[6] Jnet (fo=1, routed)Xh+= NJSFP_GEN[38].ngFEC_module/bram_array[5].buffer_server/input_size_i_reg[8]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr{ ipb/udp_if/ipbus_rx_ram/CLK Jnet (fo=204776, routed)Xhq@X2Y4 (CLOCK_ROOT)k 51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr <8SFP_GEN[38].ngFEC_module/bram_array[5].buffer_server/CLK Jnet (fo=204776, routed)XhhE@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] NJSFP_GEN[38].ngFEC_module/bram_array[5].buffer_server/input_size_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhD=E Jinter-SLR compensationXh&þ@ Jclock uncertaintyXhڭ LHSFP_GEN[38].ngFEC_module/bram_array[5].buffer_server/input_size_i_reg[8]Setup_BFF_SLICEL_C_D JFDCEXh}=/ JXh< J required timeXh B; J arrival timeXhu/ JXh4 JslackXhz?51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLKNJSFP_GEN[38].ngFEC_module/bram_array[3].buffer_server/input_size_i_reg[8]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1 RAMB36E2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuA}BB B?5FL "q@?5F@Bڭ=А=>.8?D=W9 @lAc?K@ ?C#@f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) þ%?5F@- ?5  73ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0]*Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0] JRAMB36E2XhzrV?s 0,ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 Jnet (fo=1, routed)Xhu<d 62ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CASDINB[0] JXhzr 84ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0],Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0] JRAMB36E2Xhzre;_>b ipb/trans/iface/rx_dob[8] Jnet (fo=698, routed)Xh1AD JXhSLR Crossing[0->1]] /+ipb/trans/iface/input_size_i[8]_i_1__137/I0 JXhzr~ .*ipb/trans/iface/input_size_i[8]_i_1__137/OProp_G6LUT_SLICEM_I0_O JLUT6Xhzrl{> RNSFP_GEN[38].ngFEC_module/bram_array[3].buffer_server/input_size_i_reg[12]_1[6] Jnet (fo=1, routed)XhC = NJSFP_GEN[38].ngFEC_module/bram_array[3].buffer_server/input_size_i_reg[8]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr{ ipb/udp_if/ipbus_rx_ram/CLK Jnet (fo=204776, routed)Xhq@X2Y4 (CLOCK_ROOT)k 51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr <8SFP_GEN[38].ngFEC_module/bram_array[3].buffer_server/CLK Jnet (fo=204776, routed)Xh?5F@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] NJSFP_GEN[38].ngFEC_module/bram_array[3].buffer_server/input_size_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhD=E Jinter-SLR compensationXhþ@ Jclock uncertaintyXhڭ LHSFP_GEN[38].ngFEC_module/bram_array[3].buffer_server/input_size_i_reg[8]Setup_GFF_SLICEM_C_D JFDCEXho=/ JXh< J required timeXhB B; J arrival timeXh/ JXh4 JslackXh.8?51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLKNJSFP_GEN[38].ngFEC_module/bram_array[4].buffer_server/input_size_i_reg[8]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1 RAMB36E2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsumA}B BxFi;q@xF@Bڭ=А=>*9V?D=1 @hAc?K@ ?#@f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ľ%yF@- ?5  73ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0]*Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0] JRAMB36E2XhzrV?s 0,ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 Jnet (fo=1, routed)Xhu<d 62ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CASDINB[0] JXhzr 84ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0],Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0] JRAMB36E2Xhzre;_>b ipb/trans/iface/rx_dob[8] Jnet (fo=698, routed)Xh-AD JXhSLR Crossing[0->1]] /+ipb/trans/iface/input_size_i[8]_i_1__138/I0 JXhzr~ .*ipb/trans/iface/input_size_i[8]_i_1__138/OProp_B6LUT_SLICEM_I0_O JLUT6Xhzrx> RNSFP_GEN[38].ngFEC_module/bram_array[4].buffer_server/input_size_i_reg[12]_1[6] Jnet (fo=1, routed)XhC = NJSFP_GEN[38].ngFEC_module/bram_array[4].buffer_server/input_size_i_reg[8]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr{ ipb/udp_if/ipbus_rx_ram/CLK Jnet (fo=204776, routed)Xhq@X2Y4 (CLOCK_ROOT)k 51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr <8SFP_GEN[38].ngFEC_module/bram_array[4].buffer_server/CLK Jnet (fo=204776, routed)XhxF@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] NJSFP_GEN[38].ngFEC_module/bram_array[4].buffer_server/input_size_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhD=E Jinter-SLR compensationXhľ@ Jclock uncertaintyXhڭ LHSFP_GEN[38].ngFEC_module/bram_array[4].buffer_server/input_size_i_reg[8]Setup_BFF_SLICEM_C_D JFDCEXh}=/ JXh< J required timeXh B; J arrival timeXh/ JXh4 JslackXh*9V?51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLKNJSFP_GEN[38].ngFEC_module/bram_array[6].buffer_server/input_size_i_reg[8]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1 RAMB36E2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsue;A}Bܮ B@? 7q@@@Bڭ=А=>T}?D=5^@Ac?K@ ?@f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %@@- ?5  73ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0]*Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0] JRAMB36E2XhzrV?s 0,ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 Jnet (fo=1, routed)Xhu<d 62ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CASDINB[0] JXhzr 84ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0],Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0] JRAMB36E2Xhzre;_>b ipb/trans/iface/rx_dob[8] Jnet (fo=698, routed)Xh7AD JXhSLR Crossing[0->1]] /+ipb/trans/iface/input_size_i[8]_i_1__140/I0 JXhzr~ .*ipb/trans/iface/input_size_i[8]_i_1__140/OProp_D6LUT_SLICEM_I0_O JLUT6Xhzrj= RNSFP_GEN[38].ngFEC_module/bram_array[6].buffer_server/input_size_i_reg[12]_1[6] Jnet (fo=1, routed)Xh*\= NJSFP_GEN[38].ngFEC_module/bram_array[6].buffer_server/input_size_i_reg[8]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr{ ipb/udp_if/ipbus_rx_ram/CLK Jnet (fo=204776, routed)Xhq@X2Y4 (CLOCK_ROOT)k 51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr <8SFP_GEN[38].ngFEC_module/bram_array[6].buffer_server/CLK Jnet (fo=204776, routed)Xh@@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] NJSFP_GEN[38].ngFEC_module/bram_array[6].buffer_server/input_size_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhD=E Jinter-SLR compensationXh@ Jclock uncertaintyXhڭ LHSFP_GEN[38].ngFEC_module/bram_array[6].buffer_server/input_size_i_reg[8]Setup_DFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXhܮ B; J arrival timeXh_/ JXh4 JslackXhT}?51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLKNJSFP_GEN[38].ngFEC_module/bram_array[8].buffer_server/input_size_i_reg[8]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1 RAMB36E2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsujA}B2 B?;q@?@Bڭ=А=>Ȩ?D=@~jAc?K@ ?.@f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) <%?@- ?5  73ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0]*Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0] JRAMB36E2XhzrV?s 0,ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 Jnet (fo=1, routed)Xhu<d 62ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CASDINB[0] JXhzr 84ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0],Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0] JRAMB36E2Xhzre;_>b ipb/trans/iface/rx_dob[8] Jnet (fo=698, routed)XhAD JXhSLR Crossing[0->1]] /+ipb/trans/iface/input_size_i[8]_i_1__142/I0 JXhzr~ .*ipb/trans/iface/input_size_i[8]_i_1__142/OProp_D6LUT_SLICEM_I0_O JLUT6XhzrGa= RNSFP_GEN[38].ngFEC_module/bram_array[8].buffer_server/input_size_i_reg[12]_1[6] Jnet (fo=1, routed)Xh*\= NJSFP_GEN[38].ngFEC_module/bram_array[8].buffer_server/input_size_i_reg[8]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr{ ipb/udp_if/ipbus_rx_ram/CLK Jnet (fo=204776, routed)Xhq@X2Y4 (CLOCK_ROOT)k 51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr <8SFP_GEN[38].ngFEC_module/bram_array[8].buffer_server/CLK Jnet (fo=204776, routed)Xh?@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] NJSFP_GEN[38].ngFEC_module/bram_array[8].buffer_server/input_size_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhD=E Jinter-SLR compensationXh<@ Jclock uncertaintyXhڭ LHSFP_GEN[38].ngFEC_module/bram_array[8].buffer_server/input_size_i_reg[8]Setup_DFF_SLICEM_C_D JFDCEXh%=/ JXh< J required timeXh2 B; J arrival timeXhQ/ JXh4 JslackXhȨ?51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLKNJSFP_GEN[38].ngFEC_module/bram_array[1].buffer_server/input_size_i_reg[8]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1 RAMB36E2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsu> A}B9 B@7q@@@Bڭ=А=>-?D=|@Ac?K@ ?@f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) c%@@- ?5  73ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0]*Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0] JRAMB36E2XhzrV?s 0,ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 Jnet (fo=1, routed)Xhu<d 62ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CASDINB[0] JXhzr 84ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0],Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0] JRAMB36E2Xhzre;_>b ipb/trans/iface/rx_dob[8] Jnet (fo=698, routed)XhFAD JXhSLR Crossing[0->1]] /+ipb/trans/iface/input_size_i[8]_i_1__135/I0 JXhzr~ .*ipb/trans/iface/input_size_i[8]_i_1__135/OProp_B6LUT_SLICEM_I0_O JLUT6Xhzr 0> RNSFP_GEN[38].ngFEC_module/bram_array[1].buffer_server/input_size_i_reg[12]_1[6] Jnet (fo=1, routed)XhC = NJSFP_GEN[38].ngFEC_module/bram_array[1].buffer_server/input_size_i_reg[8]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr{ ipb/udp_if/ipbus_rx_ram/CLK Jnet (fo=204776, routed)Xhq@X2Y4 (CLOCK_ROOT)k 51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr <8SFP_GEN[38].ngFEC_module/bram_array[1].buffer_server/CLK Jnet (fo=204776, routed)Xh@@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] NJSFP_GEN[38].ngFEC_module/bram_array[1].buffer_server/input_size_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhD=E Jinter-SLR compensationXhc@ Jclock uncertaintyXhڭ LHSFP_GEN[38].ngFEC_module/bram_array[1].buffer_server/input_size_i_reg[8]Setup_BFF_SLICEM_C_D JFDCEXh}=/ JXh< J required timeXh9 B; J arrival timeXh!/ JXh4 JslackXh-?51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLKNJSFP_GEN[38].ngFEC_module/bram_array[2].buffer_server/input_size_i_reg[8]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1 RAMB36E2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuZA}B BlG/q@lG@Bڭ=А=>5?D=@Ac?K@ ?z$@f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ?`ž%lG@- ?5  73ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0]*Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0] JRAMB36E2XhzrV?s 0,ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 Jnet (fo=1, routed)Xhu<d 62ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CASDINB[0] JXhzr 84ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0],Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0] JRAMB36E2Xhzre;_>b ipb/trans/iface/rx_dob[8] Jnet (fo=698, routed)XhAD JXhSLR Crossing[0->1]] /+ipb/trans/iface/input_size_i[8]_i_1__136/I0 JXhzr~ .*ipb/trans/iface/input_size_i[8]_i_1__136/OProp_C6LUT_SLICEL_I0_O JLUT6XhzrX9= RNSFP_GEN[38].ngFEC_module/bram_array[2].buffer_server/input_size_i_reg[12]_1[6] Jnet (fo=1, routed)XhP= NJSFP_GEN[38].ngFEC_module/bram_array[2].buffer_server/input_size_i_reg[8]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr{ ipb/udp_if/ipbus_rx_ram/CLK Jnet (fo=204776, routed)Xhq@X2Y4 (CLOCK_ROOT)k 51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr <8SFP_GEN[38].ngFEC_module/bram_array[2].buffer_server/CLK Jnet (fo=204776, routed)XhlG@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] NJSFP_GEN[38].ngFEC_module/bram_array[2].buffer_server/input_size_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhD=E Jinter-SLR compensationXh?`ž@ Jclock uncertaintyXhڭ LHSFP_GEN[38].ngFEC_module/bram_array[2].buffer_server/input_size_i_reg[8]Setup_CFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXh B; J arrival timeXhI/ JXh4 JslackXh5?51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLKNJSFP_GEN[38].ngFEC_module/bram_array[9].buffer_server/input_size_i_reg[8]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1 RAMB36E2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuKA}B BEF!q@EF@Bڭ=А=>p?D=1 @Ac?K@ ?S#@f(rising edge-triggered cell RAMB36E2 clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkipb_clkipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) Zþ%EF@- ?5  73ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CASDOUTB[0]*Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[0] JRAMB36E2XhzrV?s 0,ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0_n_67 Jnet (fo=1, routed)Xhu<d 62ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/CASDINB[0] JXhzr 84ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1/DOUTBDOUT[0],Prop_RAMB36E2_RAMB36_CASDINB[0]_DOUTBDOUT[0] JRAMB36E2Xhzre;_>b ipb/trans/iface/rx_dob[8] Jnet (fo=698, routed)XhffAD JXhSLR Crossing[0->1]] /+ipb/trans/iface/input_size_i[8]_i_1__143/I0 JXhzr~ .*ipb/trans/iface/input_size_i[8]_i_1__143/OProp_B6LUT_SLICEM_I0_O JLUT6Xhzrx> RNSFP_GEN[38].ngFEC_module/bram_array[9].buffer_server/input_size_i_reg[12]_1[6] Jnet (fo=1, routed)XhC = NJSFP_GEN[38].ngFEC_module/bram_array[9].buffer_server/input_size_i_reg[8]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr{ ipb/udp_if/ipbus_rx_ram/CLK Jnet (fo=204776, routed)Xhq@X2Y4 (CLOCK_ROOT)k 51ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_0/CLKBWRCLK JRAMB36E2XhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr <8SFP_GEN[38].ngFEC_module/bram_array[9].buffer_server/CLK Jnet (fo=204776, routed)XhEF@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] NJSFP_GEN[38].ngFEC_module/bram_array[9].buffer_server/input_size_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhD=E Jinter-SLR compensationXhZþ@ Jclock uncertaintyXhڭ LHSFP_GEN[38].ngFEC_module/bram_array[9].buffer_server/input_size_i_reg[8]Setup_BFF_SLICEM_C_D JFDCEXh}=/ JXh< J required timeXh B; J arrival timeXh/ JXh4 JslackXhp?  refclk125 refclk125!)@1@9A@I@hq}?EE;  DRPclk_dcm DRPclk_dcm!)#@13@9A#@I3@hq}MAFF>  clk125_dcm clk125_dcm!)@1@9A@I@hq}L7@GG  clk250_dcm clk250_dcm!)?1@9A?I@hq}n@HH  clk62_5_dcm clk62_5_dcm!)@1/@9A@I/@eg`Ahq}>h=>>GII= rise - rise rise - rise  3/eth/phy/U0/transceiver_inst/txdata_int_reg[4]/Ceth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[4]"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj3clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000nsuMb>}F <3?F@h= D=&1>?o?V?H?e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_dcm clk62_5_dcm clk62_5_dcm(DCD - SCD - CPR) 3/eth/phy/U0/transceiver_inst/txdata_int_reg[4]/QProp_GFF_SLICEL_C_Q JFDREXhzrD= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[4] Jnet (fo=1, routed)Xh&1> eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[4] J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrK$>R  refclk125_o Jnet (fo=2, routed)Xht<D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr=M CLKIN1 Jnet (fo=1, routed)Xh#۹?F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrNbпR  clk62_5_dcm Jnet (fo=1, routed)Xh +>B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr/< '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)XhJ ?X5Y0 (CLOCK_ROOT)e 3/eth/phy/U0/transceiver_inst/txdata_int_reg[4]/C JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr~>R  refclk125_o Jnet (fo=2, routed)Xh)\=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh?C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrؿR  clk62_5_dcm Jnet (fo=1, routed)XhV>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr< eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh'1?X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh  eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST&Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[4] J GTHE3_CHANNELXh 0>/ JXh< J required timeXh; J arrival timeXh#@/ JXh4 JslackXhh=3/eth/phy/U0/transceiver_inst/txdata_int_reg[9]/Ceth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[9]"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj3clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000nsu`->}XFks ?F@=FD==?Z?V?H?e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_dcm clk62_5_dcm clk62_5_dcm(DCD - SCD - CPR) 3/eth/phy/U0/transceiver_inst/txdata_int_reg[9]/QProp_FFF2_SLICEM_C_Q JFDREXhzrD= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[9] Jnet (fo=1, routed)Xh= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[9] J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrK$>R  refclk125_o Jnet (fo=2, routed)Xht<D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr=M CLKIN1 Jnet (fo=1, routed)Xh#۹?F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrNbпR  clk62_5_dcm Jnet (fo=1, routed)Xh +>B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr/< '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xh!?X5Y0 (CLOCK_ROOT)e 3/eth/phy/U0/transceiver_inst/txdata_int_reg[9]/C JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr~>R  refclk125_o Jnet (fo=2, routed)Xh)\=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh?C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrؿR  clk62_5_dcm Jnet (fo=1, routed)XhV>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr< eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh'1?X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXhF eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST&Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[9] J GTHE3_CHANNELXh+>/ JXh< J required timeXhX; J arrival timeXhC?/ JXh4 JslackXh=;7eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/Ceth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXCTRL1[0]"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj3clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000nsuGa>}jFzB<E?F@!8=9H=/>??V?H?e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_dcm clk62_5_dcm clk62_5_dcm(DCD - SCD - CPR) ;7eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/QProp_EFF_SLICEL_C_Q JFDREXhzr9H= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txctrl1_in[0] Jnet (fo=1, routed)Xh/> eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXCTRL1[0] J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrK$>R  refclk125_o Jnet (fo=2, routed)Xht<D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr=M CLKIN1 Jnet (fo=1, routed)Xh#۹?F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrNbпR  clk62_5_dcm Jnet (fo=1, routed)Xh +>B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr/< '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xh\?X5Y0 (CLOCK_ROOT)m ;7eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/C JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr~>R  refclk125_o Jnet (fo=2, routed)Xh)\=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh?C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrؿR  clk62_5_dcm Jnet (fo=1, routed)XhV>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr< eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh'1?X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'Hold_GTHE3_CHANNEL_TXUSRCLK2_TXCTRL1[0] J GTHE3_CHANNELXhy&>/ JXh< J required timeXhj; J arrival timeXhU@/ JXh4 JslackXh!8=62eth/phy/U0/transceiver_inst/txcharisk_int_reg[1]/Ceth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXCTRL2[1]"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj3clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000nsuR>}Fks ?F@@=FD=!>?Z?V?H?e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_dcm clk62_5_dcm clk62_5_dcm(DCD - SCD - CPR) 62eth/phy/U0/transceiver_inst/txcharisk_int_reg[1]/QProp_EFF2_SLICEM_C_Q JFDREXhzrD= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txctrl2_in[1] Jnet (fo=1, routed)Xh!> eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXCTRL2[1] J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrK$>R  refclk125_o Jnet (fo=2, routed)Xht<D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr=M CLKIN1 Jnet (fo=1, routed)Xh#۹?F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrNbпR  clk62_5_dcm Jnet (fo=1, routed)Xh +>B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr/< '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xh!?X5Y0 (CLOCK_ROOT)h 62eth/phy/U0/transceiver_inst/txcharisk_int_reg[1]/C JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr~>R  refclk125_o Jnet (fo=2, routed)Xh)\=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh?C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrؿR  clk62_5_dcm Jnet (fo=1, routed)XhV>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr< eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh'1?X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXhF eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'Hold_GTHE3_CHANNEL_TXUSRCLK2_TXCTRL2[1] J GTHE3_CHANNELXh-2>/ JXh< J required timeXh; J arrival timeXh @/ JXh4 JslackXh@=3/eth/phy/U0/transceiver_inst/txdata_int_reg[5]/Ceth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[5]"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj3clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000nsu5,>}&FxcE?F@$@=JD==??V?H?e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_dcm clk62_5_dcm clk62_5_dcm(DCD - SCD - CPR) 3/eth/phy/U0/transceiver_inst/txdata_int_reg[5]/QProp_GFF2_SLICEM_C_Q JFDREXhzrD= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[5] Jnet (fo=1, routed)Xh= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[5] J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrK$>R  refclk125_o Jnet (fo=2, routed)Xht<D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr=M CLKIN1 Jnet (fo=1, routed)Xh#۹?F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrNbпR  clk62_5_dcm Jnet (fo=1, routed)Xh +>B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr/< '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xh\?X5Y0 (CLOCK_ROOT)e 3/eth/phy/U0/transceiver_inst/txdata_int_reg[5]/C JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr~>R  refclk125_o Jnet (fo=2, routed)Xh)\=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh?C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrؿR  clk62_5_dcm Jnet (fo=1, routed)XhV>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr< eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh'1?X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXhJ eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST&Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[5] J GTHE3_CHANNELXhp= >/ JXh< J required timeXh&; J arrival timeXhL?/ JXh4 JslackXh$@=yA=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync5/CA=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync6/D"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj3clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000nsun>}MA= ?@J=%D=[=?Z?V?&!?e(rising edge-triggered cell FDPE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})e(rising edge-triggered cell FDPE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_dcm clk62_5_dcm clk62_5_dcm(DCD - SCD - CPR) A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync5/QProp_EFF2_SLICEL_C_Q JFDPEXhzrD= C?eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync_reg5 Jnet (fo=1, routed)Xh[=s A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync6/D JFDPEXhzr O J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrK$>R  refclk125_o Jnet (fo=2, routed)Xht<D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr=M CLKIN1 Jnet (fo=1, routed)Xh#۹?F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrNbпR  clk62_5_dcm Jnet (fo=1, routed)Xh +>B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr/< ;7eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/userclk Jnet (fo=69, routed)Xh!?X5Y0 (CLOCK_ROOT)s A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync5/C JFDPEXhzr O J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr~>R  refclk125_o Jnet (fo=2, routed)Xh)\=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh?C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrؿR  clk62_5_dcm Jnet (fo=1, routed)XhV>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr< ;7eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/userclk Jnet (fo=69, routed)Xh?X5Y0 (CLOCK_ROOT)s A=eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync6/C JFDPEXhzr> Jclock pessimismXh% ?;eth/phy/U0/transceiver_inst/SYNC_ASYNC_RESET_TX/reset_sync6Hold_AFF2_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhJ=3/eth/phy/U0/transceiver_inst/txdata_int_reg[0]/Ceth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[0]"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj3clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000nsu433>}}FzB<E?F@UM=9H=%>??V?H?e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_dcm clk62_5_dcm clk62_5_dcm(DCD - SCD - CPR) 3/eth/phy/U0/transceiver_inst/txdata_int_reg[0]/QProp_FFF_SLICEL_C_Q JFDREXhzr9H= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[0] Jnet (fo=1, routed)Xh%> eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[0] J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrK$>R  refclk125_o Jnet (fo=2, routed)Xht<D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr=M CLKIN1 Jnet (fo=1, routed)Xh#۹?F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrNbпR  clk62_5_dcm Jnet (fo=1, routed)Xh +>B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr/< '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xh\?X5Y0 (CLOCK_ROOT)e 3/eth/phy/U0/transceiver_inst/txdata_int_reg[0]/C JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr~>R  refclk125_o Jnet (fo=2, routed)Xh)\=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh?C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrؿR  clk62_5_dcm Jnet (fo=1, routed)XhV>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr< eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh'1?X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST&Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[0] J GTHE3_CHANNELXhl=/ JXh< J required timeXh}; J arrival timeXh?/ JXh4 JslackXhUM=:6eth/phy/U0/transceiver_inst/txchardispval_int_reg[0]/Ceth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXCTRL0[0]"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj3clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000nsuSc>}XF <3?F@a= D=-2>?o?V?H?e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_dcm clk62_5_dcm clk62_5_dcm(DCD - SCD - CPR) :6eth/phy/U0/transceiver_inst/txchardispval_int_reg[0]/QProp_EFF2_SLICEL_C_Q JFDREXhzrD= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txctrl0_in[0] Jnet (fo=1, routed)Xh-2> eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXCTRL0[0] J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrK$>R  refclk125_o Jnet (fo=2, routed)Xht<D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr=M CLKIN1 Jnet (fo=1, routed)Xh#۹?F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrNbпR  clk62_5_dcm Jnet (fo=1, routed)Xh +>B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr/< '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)XhJ ?X5Y0 (CLOCK_ROOT)l :6eth/phy/U0/transceiver_inst/txchardispval_int_reg[0]/C JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr~>R  refclk125_o Jnet (fo=2, routed)Xh)\=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh?C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrؿR  clk62_5_dcm Jnet (fo=1, routed)XhV>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr< eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh'1?X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh  eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'Hold_GTHE3_CHANNEL_TXUSRCLK2_TXCTRL0[0] J GTHE3_CHANNELXh>/ JXh< J required timeXhX; J arrival timeXhY4@/ JXh4 JslackXha=3/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/Ceth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[2]"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj3clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000nsu"/]>}FzB<E?F@;j=D=1,>??V?H?e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_dcm clk62_5_dcm clk62_5_dcm(DCD - SCD - CPR) 3/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/QProp_HFF_SLICEL_C_Q JFDREXhzrD= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[2] Jnet (fo=1, routed)Xh1,> eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[2] J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrK$>R  refclk125_o Jnet (fo=2, routed)Xht<D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr=M CLKIN1 Jnet (fo=1, routed)Xh#۹?F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrNbпR  clk62_5_dcm Jnet (fo=1, routed)Xh +>B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr/< '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xh\?X5Y0 (CLOCK_ROOT)e 3/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/C JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr~>R  refclk125_o Jnet (fo=2, routed)Xh)\=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh?C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrؿR  clk62_5_dcm Jnet (fo=1, routed)XhV>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr< eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh'1?X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST&Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[2] J GTHE3_CHANNELXh+>/ JXh< J required timeXh; J arrival timeXh@/ JXh4 JslackXh;j=40eth/phy/U0/transceiver_inst/txdata_int_reg[10]/Ceth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[10]"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj3clk62_5_dcm rise@0.000ns - clk62_5_dcm rise@0.000nsuZ>}F <3?F@Cn= D=(>?o?V?H?e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Fast clk62_5_dcm clk62_5_dcm clk62_5_dcm(DCD - SCD - CPR) 40eth/phy/U0/transceiver_inst/txdata_int_reg[10]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userdata_tx_in[10] Jnet (fo=1, routed)Xh(> eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXDATA[10] J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrK$>R  refclk125_o Jnet (fo=2, routed)Xht<D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr=M CLKIN1 Jnet (fo=1, routed)Xh#۹?F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrNbпR  clk62_5_dcm Jnet (fo=1, routed)Xh +>B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr/< '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)XhJ ?X5Y0 (CLOCK_ROOT)f 40eth/phy/U0/transceiver_inst/txdata_int_reg[10]/C JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr~>R  refclk125_o Jnet (fo=2, routed)Xh)\=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh?C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrؿR  clk62_5_dcm Jnet (fo=1, routed)XhV>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr< eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh'1?X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr> Jclock pessimismXh  eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST'Hold_GTHE3_CHANNEL_TXUSRCLK2_TXDATA[10] J GTHE3_CHANNELXhV>/ JXh< J required timeXh; J arrival timeXh@/ JXh4 JslackXhCn=eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK284eth/phy/U0/transceiver_inst/rxbufstatus_reg_reg[2]/D"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj4clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000nsuA`?}Ag`AYi?-?gf&?C#@!?v@?n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_dcm clk62_5_dcm clk62_5_dcm((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXBUFSTATUS[2]+Prop_GTHE3_CHANNEL_RXUSRCLK2_RXBUFSTATUS[2] J GTHE3_CHANNELXhzr-? @R  refclk125_o Jnet (fo=2, routed)Xh5^=D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh|o@F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrUR  clk62_5_dcm Jnet (fo=1, routed)XhA?B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh|@X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrAC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrxV>R  refclk125_o Jnet (fo=2, routed)XhT=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>M CLKIN1 Jnet (fo=1, routed)XhW@C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzr{R  clk62_5_dcm Jnet (fo=1, routed)Xhb>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr5^= '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xhlg@X5Y0 (CLOCK_ROOT)j 84eth/phy/U0/transceiver_inst/rxbufstatus_reg_reg[2]/C JFDREXhzr> Jclock pessimismXhYi?@ Jclock uncertaintyXh* 62eth/phy/U0/transceiver_inst/rxbufstatus_reg_reg[2]Setup_EFF_SLICEL_C_D JFDREXho=/ JXh< J required timeXhaAzi?E?l?C#@-ݴ?v@?n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_dcm clk62_5_dcm clk62_5_dcm((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXBUFSTATUS[1]+Prop_GTHE3_CHANNEL_TXUSRCLK2_TXBUFSTATUS[1] J GTHE3_CHANNELXhzrE? A=eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i_n_118 Jnet (fo=1, routed)Xhl?j 84eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/D JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr5E>R  refclk125_o Jnet (fo=2, routed)Xh5^=D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh|o@F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrUR  clk62_5_dcm Jnet (fo=1, routed)XhA?B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh,}@X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2 J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrAC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrxV>R  refclk125_o Jnet (fo=2, routed)XhT=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>M CLKIN1 Jnet (fo=1, routed)XhW@C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzr{R  clk62_5_dcm Jnet (fo=1, routed)Xhb>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr5^= '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)XhAh@X5Y0 (CLOCK_ROOT)j 84eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/C JFDREXhzr> Jclock pessimismXhzi?@ Jclock uncertaintyXh* 62eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]Setup_AFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXh3A; J arrival timeXhM/ JXh4 JslackXhaA`eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK23/eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]/D"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj4clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000nsu?}A@A*$;=@*@A*=А=] >bA~|?O?oC?C#@!?v@Z?n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_dcm clk62_5_dcm clk62_5_dcm((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[0]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[0] J GTHE3_CHANNELXhzrO?p -)eth/phy/U0/transceiver_inst/rxdata_int[0] Jnet (fo=1, routed)XhoC?e 3/eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]/D JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr5E>R  refclk125_o Jnet (fo=2, routed)Xh5^=D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh|o@F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrUR  clk62_5_dcm Jnet (fo=1, routed)XhA?B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh|@X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrAC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrxV>R  refclk125_o Jnet (fo=2, routed)XhT=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>M CLKIN1 Jnet (fo=1, routed)XhW@C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzr{R  clk62_5_dcm Jnet (fo=1, routed)Xhb>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr5^= '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xh֣h@X5Y0 (CLOCK_ROOT)e 3/eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]/C JFDREXhzr> Jclock pessimismXh~|?@ Jclock uncertaintyXh*| 1-eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]Setup_AFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXh@A; J arrival timeXhU/ JXh4 JslackXhbAheth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK240eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]/D"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj4clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000nsu,?}APAQ R=@Q @A*=А=] >bA{?w?l;?C#@!?v@?n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_dcm clk62_5_dcm clk62_5_dcm((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[15]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[15] J GTHE3_CHANNELXhzrw?q .*eth/phy/U0/transceiver_inst/rxdata_int[15] Jnet (fo=1, routed)Xhl;?f 40eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]/D JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr5E>R  refclk125_o Jnet (fo=2, routed)Xh5^=D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh|o@F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrUR  clk62_5_dcm Jnet (fo=1, routed)XhA?B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh|@X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrAC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrxV>R  refclk125_o Jnet (fo=2, routed)XhT=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>M CLKIN1 Jnet (fo=1, routed)XhW@C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzr{R  clk62_5_dcm Jnet (fo=1, routed)Xhb>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr5^= '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xh%i@X5Y0 (CLOCK_ROOT)f 40eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]/C JFDREXhzr> Jclock pessimismXh{?@ Jclock uncertaintyXh*~ 2.eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]Setup_EFF2_SLICEM_C_D JFDREXh=/ JXh< J required timeXhPA; J arrival timeXhe/ JXh4 JslackXhbAgeth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK240eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]/D"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj4clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000nsur=?}A=5cAp|??>?C#@!?v@?n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_dcm clk62_5_dcm clk62_5_dcm((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[11]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[11] J GTHE3_CHANNELXhzr?q .*eth/phy/U0/transceiver_inst/rxdata_int[11] Jnet (fo=1, routed)Xh>?f 40eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]/D JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr5E>R  refclk125_o Jnet (fo=2, routed)Xh5^=D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh|o@F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrUR  clk62_5_dcm Jnet (fo=1, routed)XhA?B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh|@X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrAC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrxV>R  refclk125_o Jnet (fo=2, routed)XhT=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>M CLKIN1 Jnet (fo=1, routed)XhW@C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzr{R  clk62_5_dcm Jnet (fo=1, routed)Xhb>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr5^= '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xhh@X5Y0 (CLOCK_ROOT)f 40eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]/C JFDREXhzr> Jclock pessimismXhp|?@ Jclock uncertaintyXh*} 2.eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]Setup_FFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXhUcA{?d;?E6?C#@!?v@?n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_dcm clk62_5_dcm clk62_5_dcm((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[7]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[7] J GTHE3_CHANNELXhzrd;?p -)eth/phy/U0/transceiver_inst/rxdata_int[7] Jnet (fo=1, routed)XhE6?e 3/eth/phy/U0/transceiver_inst/rxdata_reg_reg[7]/D JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr5E>R  refclk125_o Jnet (fo=2, routed)Xh5^=D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh|o@F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrUR  clk62_5_dcm Jnet (fo=1, routed)XhA?B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh|@X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrAC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrxV>R  refclk125_o Jnet (fo=2, routed)XhT=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>M CLKIN1 Jnet (fo=1, routed)XhW@C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzr{R  clk62_5_dcm Jnet (fo=1, routed)Xhb>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr5^= '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xh%i@X5Y0 (CLOCK_ROOT)e 3/eth/phy/U0/transceiver_inst/rxdata_reg_reg[7]/C JFDREXhzr> Jclock pessimismXh{?@ Jclock uncertaintyXh*} 1-eth/phy/U0/transceiver_inst/rxdata_reg_reg[7]Setup_HFF2_SLICEM_C_D JFDREXho=/ JXh< J required timeXhNA; J arrival timeXh/ JXh4 JslackXhUcAaeth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK23/eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]/D"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj4clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000nsu$1?}APAQ R=@Q @A*=А=] >cA{?j?P7?C#@!?v@?n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_dcm clk62_5_dcm clk62_5_dcm((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[5]&Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[5] J GTHE3_CHANNELXhzrj?p -)eth/phy/U0/transceiver_inst/rxdata_int[5] Jnet (fo=1, routed)XhP7?e 3/eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]/D JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr5E>R  refclk125_o Jnet (fo=2, routed)Xh5^=D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh|o@F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrUR  clk62_5_dcm Jnet (fo=1, routed)XhA?B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh|@X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrAC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrxV>R  refclk125_o Jnet (fo=2, routed)XhT=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>M CLKIN1 Jnet (fo=1, routed)XhW@C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzr{R  clk62_5_dcm Jnet (fo=1, routed)Xhb>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr5^= '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xh%i@X5Y0 (CLOCK_ROOT)e 3/eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]/C JFDREXhzr> Jclock pessimismXh{?@ Jclock uncertaintyXh*} 1-eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]Setup_GFF2_SLICEM_C_D JFDREXh=/ JXh< J required timeXhPA; J arrival timeXhY/ JXh4 JslackXhcAeth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2:6eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[1]/D"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj4clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000nsu?}A>Aށ433=@ށ@A*=А=] >dAp|?(\o?M?C#@!?v@?n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_dcm clk62_5_dcm clk62_5_dcm((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXCTRL2[1]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXCTRL2[1] J GTHE3_CHANNELXhzr(\o?q .*eth/phy/U0/transceiver_inst/rxctrl2_out[1] Jnet (fo=1, routed)XhM?l :6eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[1]/D JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr5E>R  refclk125_o Jnet (fo=2, routed)Xh5^=D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh|o@F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrUR  clk62_5_dcm Jnet (fo=1, routed)XhA?B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh|@X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrAC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrxV>R  refclk125_o Jnet (fo=2, routed)XhT=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>M CLKIN1 Jnet (fo=1, routed)XhW@C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzr{R  clk62_5_dcm Jnet (fo=1, routed)Xhb>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr5^= '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xhh@X5Y0 (CLOCK_ROOT)l :6eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[1]/C JFDREXhzr> Jclock pessimismXhp|?@ Jclock uncertaintyXh* 84eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[1]Setup_EFF_SLICEM_C_D JFDREXho=/ JXh< J required timeXh>A; J arrival timeXh/ JXh4 JslackXhdAgeth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK240eth/phy/U0/transceiver_inst/rxdata_reg_reg[14]/D"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj4clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000nsu?}ANAQ R=@Q @A*=А=] >meA{?"??C#@!?v@?n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_dcm clk62_5_dcm clk62_5_dcm((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXDATA[14]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXDATA[14] J GTHE3_CHANNELXhzr"?q .*eth/phy/U0/transceiver_inst/rxdata_int[14] Jnet (fo=1, routed)Xh?f 40eth/phy/U0/transceiver_inst/rxdata_reg_reg[14]/D JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr5E>R  refclk125_o Jnet (fo=2, routed)Xh5^=D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh|o@F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrUR  clk62_5_dcm Jnet (fo=1, routed)XhA?B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh|@X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrAC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrxV>R  refclk125_o Jnet (fo=2, routed)XhT=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>M CLKIN1 Jnet (fo=1, routed)XhW@C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzr{R  clk62_5_dcm Jnet (fo=1, routed)Xhb>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr5^= '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xh%i@X5Y0 (CLOCK_ROOT)f 40eth/phy/U0/transceiver_inst/rxdata_reg_reg[14]/C JFDREXhzr> Jclock pessimismXh{?@ Jclock uncertaintyXh*} 2.eth/phy/U0/transceiver_inst/rxdata_reg_reg[14]Setup_EFF_SLICEM_C_D JFDREXho=/ JXh< J required timeXhNA; J arrival timeXhv_/ JXh4 JslackXhmeAqeth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK262eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]/D"#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT*X5Y02#RCLK_CLEL_R_L_X81Y89/CLK_VDISTR_BOT:X5Y0BJZj4clk62_5_dcm rise@16.000ns - clk62_5_dcm rise@0.000nsu?}A0A?j=@?@A*=А=] >oeA+|?jt?:?C#@!?v@m?n(rising edge-triggered cell GTHE3_CHANNEL clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})e(rising edge-triggered cell FDRE clocked by clk62_5_dcm {rise@0.000ns fall@8.000ns period=16.000ns})Slow clk62_5_dcm clk62_5_dcm clk62_5_dcm((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXCTRL0[1]'Prop_GTHE3_CHANNEL_RXUSRCLK2_RXCTRL0[1] J GTHE3_CHANNELXhzrjt?q .*eth/phy/U0/transceiver_inst/rxctrl0_out[1] Jnet (fo=1, routed)Xh:?h 62eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]/D JFDREXhzrO J(clock clk62_5_dcm rise edge)XhzrC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhD i_refclk125_ibuf/I JXhzr i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3Xhzr5E>R  refclk125_o Jnet (fo=2, routed)Xh5^=D i_refclk125_bufg/I JXhzrc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr>M CLKIN1 Jnet (fo=1, routed)Xh|o@F i_clk125_MMCM/CLKIN1 JXhzrw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzrUR  clk62_5_dcm Jnet (fo=1, routed)XhA?B i_clk62_5_bufg/I JXhzre i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr= eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxusrclk_in[0] Jnet (fo=69, routed)Xh|@X5Y0 (CLOCK_ROOT) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2 J GTHE3_CHANNELXhzr O J(clock clk62_5_dcm rise edge)XhzrAC  refclk125_p JXhzrJ  refclk125_p J net (fo=0)XhA i_refclk125_ibuf/I JXh i_refclk125_ibuf/ODIV2&Prop_IBUFDS0_GTE3_GTHE3_COMMON_I_ODIV2 J IBUFDS_GTE3XhzrxV>R  refclk125_o Jnet (fo=2, routed)XhT=A i_refclk125_bufg/I JXhc i_refclk125_bufg/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>M CLKIN1 Jnet (fo=1, routed)XhW@C i_clk125_MMCM/CLKIN1 JXhw i_clk125_MMCM/CLKOUT1Prop_MMCME3_ADV_CLKIN1_CLKOUT1 J MMCME3_ADVXhzr{R  clk62_5_dcm Jnet (fo=1, routed)Xhb>? i_clk62_5_bufg/I JXhe i_clk62_5_bufg/OProp_BUFCE_BUFGCE_I_O JBUFGCEXhzr5^= '#eth/phy/U0/transceiver_inst/userclk Jnet (fo=69, routed)Xhg@X5Y0 (CLOCK_ROOT)h 62eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]/C JFDREXhzr> Jclock pessimismXh+|?@ Jclock uncertaintyXh* 40eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]Setup_EFF2_SLICEM_C_D JFDREXh=/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhoeA  ipb_clk_dcm ipb_clk_dcm!)/@1?@9A/@I?@hq}MAJJB  tx_wordclk tx_wordclk!)M@1M @9AM@IM @eк9>hq}<K8>LL rise - rise rise - rise  9g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[9]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu/>}Pǿ ӿc=}?? ?<ފʡ=j=>?n>d;?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[9]/QProp_AFF_SLICEL_C_Q JFDPEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/Q[9] Jnet (fo=11, routed)Xh ף= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[7]_i_1__186/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[7]_i_1__186/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzr< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[7] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/D JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xh}??X2Y4 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[9]/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xh ?X2Y4 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXhފ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[7]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhPǿ; J arrival timeXh"?/ JXh4 JslackXh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16]/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(CARRY8=3 LUT1=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuo>}"ۿjܿ|.>?5?j?<+= W>j<=>v?n>Χ?c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0]/QProp_AFF_SLICEL_C_Q JFDREXhzf9H= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc[0]_i_3__43/I0 JXhzf g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc[0]_i_3__43/OProp_A6LUT_SLICEL_I0_O JLUT1Xhzru< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc[0]_i_3__43_n_0 Jnet (fo=1, routed)Xho: g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0]_i_2__43/S[0] JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0]_i_2__43/CO[7]Prop_CARRY8_SLICEL_S[0]_CO[7] JCARRY8Xhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0]_i_2__43_n_0 Jnet (fo=1, routed)Xh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[8]_i_1__43/CI JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[8]_i_1__43/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8Xhzro< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[8]_i_1__43_n_0 Jnet (fo=1, routed)Xh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16]_i_1__43/CI JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16]_i_1__43/O[0]Prop_CARRY8_SLICEL_CI_O[0] JCARRY8XhzrC = g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16]_i_1__43_n_15 Jnet (fo=1, routed)Xh #< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16]/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk Jnet (fo=27439, routed)Xh?5?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[0]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk Jnet (fo=27439, routed)Xhj?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16]/C JFDREXhzr> Jclock pessimismXh+ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[16]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh"ۿ; J arrival timeXh?/ JXh4 JslackXh<g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[9]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24]/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ (CARRY8=3)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu|>}V޿v޿2$>\?v?<xi8A>im=>В?n>#۩?c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[9]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg_n_0_[9] Jnet (fo=1, routed)XhD= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1__15/S[1] JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1__15/CO[7]Prop_CARRY8_SLICEL_S[1]_CO[7] JCARRY8XhzrQ= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1__15_n_0 Jnet (fo=1, routed)Xh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]_i_1__15/CI JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]_i_1__15/CO[7]Prop_CARRY8_SLICEL_CI_CO[7] JCARRY8Xhzro< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[16]_i_1__15_n_0 Jnet (fo=1, routed)Xh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24]_i_1__15/CI JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24]_i_1__15/O[0]Prop_CARRY8_SLICEL_CI_O[0] JCARRY8XhzrC = g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24]_i_1__15_n_15 Jnet (fo=1, routed)Xh #< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24]/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk Jnet (fo=27439, routed)Xh\?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[9]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk Jnet (fo=27439, routed)Xhv?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24]/C JFDREXhzr> Jclock pessimismXhxi g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[24]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhV޿; J arrival timeXh-?/ JXh4 JslackXh<g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[0]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[19]/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT5=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu #>}rп޿hN=A??A<U*o==>?n>5^?c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[0]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/Q[0] Jnet (fo=14, routed)Xh ף= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[19]_i_1__149/I3 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[19]_i_1__149/OProp_C6LUT_SLICEM_I3_O JLUT5Xhzru< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[19] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[19]/D JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)XhA?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXhU* g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[19]Hold_CFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhrп; J arrival timeXhk?/ JXh4 JslackXhA< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[28]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[28]/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu/>}C̿^ٿˊ=?^?<!9H=> =>/?n>?c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[28]/QProp_EFF_SLICEL_C_Q JFDREXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[28] Jnet (fo=2, routed)Xh> = g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[28]/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk Jnet (fo=27439, routed)Xh?X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_acc_reg[28]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk Jnet (fo=27439, routed)Xh^?X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[28]/C JFDREXhzr> Jclock pessimismXh! g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/phase_detector_o_reg[28]Hold_GFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhC̿; J arrival timeXhף?/ JXh4 JslackXh<Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[18]/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu(\>}0ݴµo>O?µ?<$F==>"[?n>&?c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]/QProp_CFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/Q[20] Jnet (fo=13, routed)Xh1= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[18]_i_1__76/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[18]_i_1__76/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzrrh= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[18] Jnet (fo=1, routed)XhD< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[18]/D JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)XhO?X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xhµ?X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[18]/C JFDPEXhzr> Jclock pessimismXh$ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[18]Hold_AFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh0ݴ; J arrival timeXhԸ?/ JXh4 JslackXh< mg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[1]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ (CARRY8=2)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsup>}6^ڿCۿP>A?C?<$}?5>im=>?n>?c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[1]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg_n_0_[1] Jnet (fo=1, routed)XhD= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[0]_i_1/S[1] JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[0]_i_1/CO[7]Prop_CARRY8_SLICEL_S[1]_CO[7] JCARRY8Xhzr= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[0]_i_1_n_0 Jnet (fo=1, routed)Xh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1/CI JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1/O[0]Prop_CARRY8_SLICEL_CI_O[0] JCARRY8XhzrC = g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]_i_1_n_15 Jnet (fo=1, routed)Xh #< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk Jnet (fo=27439, routed)XhA?X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[1]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/tx_wordclk Jnet (fo=27439, routed)XhC?X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]/C JFDREXhzr> Jclock pessimismXh$ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_fifo_fill_level_acc/hits_acc_reg[8]Hold_AFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXh6^ڿ; J arrival timeXhV?/ JXh4 JslackXh<g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/gen_drp_interface.phase_acc_reg[1]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPDI[1]"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu"[>}׿ۿL>Nb??<+9H=(>>أ?n>+?c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})l(rising edge-triggered cell GTHE3_CHANNEL clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/gen_drp_interface.phase_acc_reg[1]/QProp_BFF_SLICEL_C_Q JFDREXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/drpdi_in[1] Jnet (fo=9, routed)Xh(> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPDI[1] J GTHE3_CHANNELXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/tx_wordclk Jnet (fo=27439, routed)XhNb?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/gen_drp_interface.phase_acc_reg[1]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/drpclk_in[0] Jnet (fo=27439, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/DRPCLK J GTHE3_CHANNELXhzr> Jclock pessimismXh+ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST"Hold_GTHE3_CHANNEL_DRPCLK_DRPDI[1] J GTHE3_CHANNELXh)\=/ JXh< J required timeXh׿; J arrival timeXh?/ JXh4 JslackXh< {wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[89]/Cieg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9]/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT4=1 MUXF7=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuَ>}&1ؿ+׿D>r?+?#<Dsh>I >>:?n>\?c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR)  {wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[89]/QProp_DFF_SLICEL_C_Q JFDCEXhzr9H= _[g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/data4[9] Jnet (fo=1, routed)Xh= njg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O[9]_i_3__42/I0 JXhzr mig_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O[9]_i_3__42/OProp_C6LUT_SLICEM_I0_O JLUT4Xhzr)\= okg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O[9]_i_3__42_n_0 Jnet (fo=1, routed)Xh rng_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9]_i_1__42/I1 JXhzr qmg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9]_i_1__42/OProp_F7MUX_CD_SLICEM_I1_O JMUXF7Xhzrj< sog_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9]_i_1__42_n_0 Jnet (fo=1, routed)XhT< ieg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9]/D JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27439, routed)Xhr?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[89]/C JFDCEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27439, routed)Xh+?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ieg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9]/C JFDCEXhzr> Jclock pessimismXhD gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[0].gbt_txgearbox_inst/TX_WORD_O_reg[9]Hold_DFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXh&1ؿ; J arrival timeXh(?/ JXh4 JslackXh#<g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/FSM_sequential_phase_aligner_state_reg[1]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/ui_align_cntr_reg[1]/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT6=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu/>}yXԿ῭=n??\<r%o="=>!?n>O?c(rising edge-triggered cell FDSE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk tx_wordclk tx_wordclk(DCD - SCD - CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/FSM_sequential_phase_aligner_state_reg[1]/QProp_DFF2_SLICEM_C_Q JFDSEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/ui_align_cntr_reg[4][0] Jnet (fo=24, routed)Xhv= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/ui_align_cntr[1]_i_1__12/I3 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_pi_ctrl/ui_align_cntr[1]_i_1__12/OProp_G6LUT_SLICEL_I3_O JLUT6Xhzru< {g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/D[0] Jnet (fo=1, routed)XhA`e< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/ui_align_cntr_reg[1]/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_wordclk Jnet (fo=27439, routed)Xhn?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/FSM_sequential_phase_aligner_state_reg[1]/C JFDSEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_wordclk Jnet (fo=27439, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/ui_align_cntr_reg[1]/C JFDREXhzr> Jclock pessimismXhr% g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/ui_align_cntr_reg[1]Hold_GFF_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhyXԿ; J arrival timeXhQ?/ JXh4 JslackXh\<M !fabric_clk_div2_q_reg[3]__0/CTX_CLKEN_reg_replica_2/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu@}oA87A^K>lW@^@oA=А=$WN>к9>=H>~?@~j|?Q@+g?W%@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 3ƾ%^@-+g?5n !fabric_clk_div2_q_reg[3]__0/QProp_AFF_SLICEM_C_Q JFDREXhzr)\>\ fabric_clk_div2_q[3] Jnet (fo=64, routed)Xh @D JXhSLR Crossing[0->1]K TX_CLKEN_i_1_replica_2/I0 JXhzrl TX_CLKEN_i_1_replica_2/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzrgff>^ TX_CLKEN_i_1_n_0_repN_2 Jnet (fo=1, routed)Xh*\=N TX_CLKEN_reg_replica_2/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhlW@X2Y4 (CLOCK_ROOT)S !fabric_clk_div2_q_reg[3]__0/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)Xh^@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N TX_CLKEN_reg_replica_2/C JFDREXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh3ƾ@ Jclock uncertaintyXhڽe TX_CLKEN_reg_replica_2Setup_DFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXh87A; J arrival timeXhQ4/ JXh4 JslackXhк9>@M !fabric_clk_div2_q_reg[3]__0/CTX_CLKEN_reg_replica_3/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu@}oA87A^K>lW@^@oA=А=$WN>P<>=5^>/@~j|?Q@+g?W%@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 3ƾ%^@-+g?5n !fabric_clk_div2_q_reg[3]__0/QProp_AFF_SLICEM_C_Q JFDREXhzr)\>\ fabric_clk_div2_q[3] Jnet (fo=64, routed)Xh@D JXhSLR Crossing[0->1]K TX_CLKEN_i_1_replica_3/I0 JXhzrl TX_CLKEN_i_1_replica_3/OProp_C6LUT_SLICEM_I0_O JLUT2XhzrA`e>^ TX_CLKEN_i_1_n_0_repN_3 Jnet (fo=1, routed)Xh=N TX_CLKEN_reg_replica_3/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhlW@X2Y4 (CLOCK_ROOT)S !fabric_clk_div2_q_reg[3]__0/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)Xh^@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N TX_CLKEN_reg_replica_3/C JFDREXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh3ƾ@ Jclock uncertaintyXhڽe TX_CLKEN_reg_replica_3Setup_CFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXh87A; J arrival timeXhE4/ JXh4 JslackXhP<>@M !fabric_clk_div2_q_reg[3]__0/CTX_CLKEN_reg_replica_7/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsux@}oA47A^K>lW@^@oA=А=$WN>^>=im>Q@~j|?Q@+g?W%@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) 3ƾ%^@-+g?5n !fabric_clk_div2_q_reg[3]__0/QProp_AFF_SLICEM_C_Q JFDREXhzr)\>\ fabric_clk_div2_q[3] Jnet (fo=64, routed)Xhd;@D JXhSLR Crossing[0->1]K TX_CLKEN_i_1_replica_7/I0 JXhzrl TX_CLKEN_i_1_replica_7/OProp_B6LUT_SLICEM_I0_O JLUT2Xhzrj=^ TX_CLKEN_i_1_n_0_repN_7 Jnet (fo=1, routed)XhC =N TX_CLKEN_reg_replica_7/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhlW@X2Y4 (CLOCK_ROOT)S !fabric_clk_div2_q_reg[3]__0/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)Xh^@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]N TX_CLKEN_reg_replica_7/C JFDREXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh3ƾ@ Jclock uncertaintyXhڽe TX_CLKEN_reg_replica_7Setup_BFF_SLICEM_C_D JFDREXh}=/ JXh< J required timeXh47A; J arrival timeXh_3/ JXh4 JslackXh^>@W fabric_clk_div2_q_reg[4]/CTX_CLKEN_reg_replica_41/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu+@}oA3A&9&R^@&9@oA=А=$WN>'>=K>F@~j|?@+g?S?c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)k fabric_clk_div2_q_reg[4]/QProp_EFF_SLICEL_C_Q JFDREXhzrV>\ fabric_clk_div2_q[4] Jnet (fo=63, routed)Xh+@L TX_CLKEN_i_1_replica_41/I1 JXhzrm TX_CLKEN_i_1_replica_41/OProp_C6LUT_SLICEL_I1_O JLUT2XhzrA`>_ TX_CLKEN_i_1_n_0_repN_41 Jnet (fo=1, routed)XhP=O TX_CLKEN_reg_replica_41/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhR^@X2Y4 (CLOCK_ROOT)P fabric_clk_div2_q_reg[4]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)Xh&9@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_41/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽf TX_CLKEN_reg_replica_41Setup_CFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXh3A; J arrival timeXhC// JXh4 JslackXh'>?` !fabric_clk_div2_q_reg[3]__0/CTX_CLKEN_reg_replica_18/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuQ@}oA0;ATUq=lW@TU@oA=А=$WN>>=n>i@~j|?Q@+g?@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)n !fabric_clk_div2_q_reg[3]__0/QProp_AFF_SLICEM_C_Q JFDREXhzr)\>\ fabric_clk_div2_q[3] Jnet (fo=64, routed)Xhz@L TX_CLKEN_i_1_replica_18/I0 JXhzrm TX_CLKEN_i_1_replica_18/OProp_G6LUT_SLICEM_I0_O JLUT2Xhzr>_ TX_CLKEN_i_1_n_0_repN_18 Jnet (fo=1, routed)XhC =O TX_CLKEN_reg_replica_18/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhlW@X2Y4 (CLOCK_ROOT)S !fabric_clk_div2_q_reg[3]__0/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhTU@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_18/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽf TX_CLKEN_reg_replica_18Setup_GFF_SLICEM_C_D JFDREXho=/ JXh< J required timeXh0;A; J arrival timeXhK75/ JXh4 JslackXh>@W fabric_clk_div2_q_reg[4]/CTX_CLKEN_reg_replica_22/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsur@}oA4AG9R^@G9@oA=А=$WN>>=Cl>V@~j|?@+g??c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)k fabric_clk_div2_q_reg[4]/QProp_EFF_SLICEL_C_Q JFDREXhzrV>\ fabric_clk_div2_q[4] Jnet (fo=63, routed)Xh@L TX_CLKEN_i_1_replica_22/I1 JXhzrm TX_CLKEN_i_1_replica_22/OProp_D6LUT_SLICEM_I1_O JLUT2Xhzrj=_ TX_CLKEN_i_1_n_0_repN_22 Jnet (fo=1, routed)Xh*\=O TX_CLKEN_reg_replica_22/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhR^@X2Y4 (CLOCK_ROOT)P fabric_clk_div2_q_reg[4]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhG9@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_22/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽf TX_CLKEN_reg_replica_22Setup_DFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXh4A; J arrival timeXhl-/ JXh4 JslackXh>?W fabric_clk_div2_q_reg[4]/CTX_CLKEN_reg_replica_24/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsup@}oA4Az<l羵R^@z<@oA=А=$WN>Wm>=D>K@~j|?@+g? @c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)k fabric_clk_div2_q_reg[4]/QProp_EFF_SLICEL_C_Q JFDREXhzrV>\ fabric_clk_div2_q[4] Jnet (fo=63, routed)Xh-@L TX_CLKEN_i_1_replica_24/I1 JXhzrm TX_CLKEN_i_1_replica_24/OProp_D6LUT_SLICEL_I1_O JLUT2XhzrY=_ TX_CLKEN_i_1_n_0_repN_24 Jnet (fo=1, routed)Xh*\=O TX_CLKEN_reg_replica_24/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhR^@X2Y4 (CLOCK_ROOT)P fabric_clk_div2_q_reg[4]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)Xhz<@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_24/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽf TX_CLKEN_reg_replica_24Setup_DFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXh4A; J arrival timeXhgf./ JXh4 JslackXhWm>?` !fabric_clk_div2_q_reg[3]__0/CTX_CLKEN_reg_replica_16/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuA}oA 4?Afd;>lW@f@oA=А=$WN>>=d;>v@~j|?Q@+g?X9,@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)n !fabric_clk_div2_q_reg[3]__0/QProp_AFF_SLICEM_C_Q JFDREXhzr)\>\ fabric_clk_div2_q[3] Jnet (fo=64, routed)Xh@L TX_CLKEN_i_1_replica_16/I0 JXhzrm TX_CLKEN_i_1_replica_16/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzr/>_ TX_CLKEN_i_1_n_0_repN_16 Jnet (fo=1, routed)Xh*\=O TX_CLKEN_reg_replica_16/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhlW@X2Y4 (CLOCK_ROOT)S !fabric_clk_div2_q_reg[3]__0/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)Xhf@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_16/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽf TX_CLKEN_reg_replica_16Setup_DFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXh 4?A; J arrival timeXh98/ JXh4 JslackXh>@6 fabric_clk_div2_q_reg[4]/CTX_CLKEN_reg_replica/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu`@}oA4b5AEV|HR^@EV@oA=А=$WN>->=>/@~j|?@+g?z@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ƻ%EV@-+g?5k fabric_clk_div2_q_reg[4]/QProp_EFF_SLICEL_C_Q JFDREXhzrV>\ fabric_clk_div2_q[4] Jnet (fo=63, routed)Xh@D JXhSLR Crossing[0->1]I TX_CLKEN_i_1_replica/I1 JXhzrj TX_CLKEN_i_1_replica/OProp_B6LUT_SLICEL_I1_O JLUT2Xhzr!r>\ TX_CLKEN_i_1_n_0_repN Jnet (fo=1, routed)Xh+=L TX_CLKEN_reg_replica/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhR^@X2Y4 (CLOCK_ROOT)P fabric_clk_div2_q_reg[4]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhEV@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]L TX_CLKEN_reg_replica/C JFDREXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhƻ@ Jclock uncertaintyXhڽc TX_CLKEN_reg_replicaSetup_BFF_SLICEL_C_D JFDREXh}=/ JXh< J required timeXh4b5A; J arrival timeXh ./ JXh4 JslackXh->?` !fabric_clk_div2_q_reg[3]__0/CTX_CLKEN_reg_replica_21/D"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsut@}oA 9?=A>p@~j|?Q@+g?P@c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)n !fabric_clk_div2_q_reg[3]__0/QProp_AFF_SLICEM_C_Q JFDREXhzr)\>\ fabric_clk_div2_q[3] Jnet (fo=64, routed)XhQ@L TX_CLKEN_i_1_replica_21/I0 JXhzrm TX_CLKEN_i_1_replica_21/OProp_H6LUT_SLICEM_I0_O JLUT2Xhzr&1>_ TX_CLKEN_i_1_n_0_repN_21 Jnet (fo=1, routed)Xh*\=O TX_CLKEN_reg_replica_21/D JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhlW@X2Y4 (CLOCK_ROOT)S !fabric_clk_div2_q_reg[3]__0/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhXY@X2Y4 (CLOCK_ROOT)O TX_CLKEN_reg_replica_21/C JFDREXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽf TX_CLKEN_reg_replica_21Setup_HFF_SLICEM_C_D JFDREXh%=/ JXh< J required timeXh [d{?O?Q>А=>=a=D=#?lG?'1?nR?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)q #ctrl_regs_inst/regs_reg[7][5]/QProp_GFF2_SLICEM_C_Q JFDCEXhzrD=x 51stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[5] Jnet (fo=2, routed)Xh#?h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh[d{?X2Y4 (CLOCK_ROOT)U #ctrl_regs_inst/regs_reg[7][5]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)XhO?X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]Hold_EFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhο; J arrival timeXhˡ?/ JXh4 JslackXha=! $ ctrl_regs_inst/regs_reg[7][31]/C2.stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT5=1)j*clk250 rise@0.000ns - ipb_clk rise@0.000nsu6A?}Ͽvo>[d{?v?Q>А=>=y=>7!?lG?'1?kT?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDPE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)q $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H=y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)XhR?a 3/stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_i_1/I2 JXhzr 2.stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_i_1/OProp_D5LUT_SLICEL_I2_O JLUT5Xhzr㥛=w 40stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_i_1_n_0 Jnet (fo=1, routed)XhX94<d 2.stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg/D JFDPEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh[d{?X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xhv?X3Y3 (CLOCK_ROOT)d 2.stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ>{ 0,stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_regHold_DFF2_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXhϿ; J arrival timeXhv?/ JXh4 JslackXhy= #ctrl_regs_inst/regs_reg[7][2]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsuSC?}Ͽ@5]>"{?@5?Q>А=>==9H=6?+G?'1?Z9T?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)p #ctrl_regs_inst/regs_reg[7][2]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H=x 51stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[2] Jnet (fo=2, routed)Xh6?h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh"{?X2Y4 (CLOCK_ROOT)U #ctrl_regs_inst/regs_reg[7][2]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh@5?X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ>~ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[2]Hold_FFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhϿ; J arrival timeXhe;?/ JXh4 JslackXh= #ctrl_regs_inst/regs_reg[7][6]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsu2L?}οO>z?O?Q>А=>=$>D=v??F?'1?nR?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)p #ctrl_regs_inst/regs_reg[7][6]/QProp_GFF_SLICEM_C_Q JFDCEXhzrD=x 51stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[6] Jnet (fo=2, routed)Xhv??h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xhz?X2Y4 (CLOCK_ROOT)U #ctrl_regs_inst/regs_reg[7][6]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)XhO?X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ>~ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]Hold_FFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXhο; J arrival timeXhS?/ JXh4 JslackXh$> #ctrl_regs_inst/regs_reg[7][3]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsuFS?}fϿ>[d{??Q>А=>=R<>D=lG?lG?'1?T?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)q #ctrl_regs_inst/regs_reg[7][3]/QProp_FFF2_SLICEM_C_Q JFDCEXhzrD=x 51stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[3] Jnet (fo=2, routed)XhlG?h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh[d{?X2Y4 (CLOCK_ROOT)U #ctrl_regs_inst/regs_reg[7][3]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ>~ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]Hold_EFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhfϿ; J arrival timeXhP?/ JXh4 JslackXhR<>f %!stat_regs_inst/ipb_clk_div2_reg/C'#stat_regs_inst/ipb_clk_div2_r_reg/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsush1?}öɿQw>X?Q?Q>А=>=5B>D=%?R^?'1?rH?b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)r %!stat_regs_inst/ipb_clk_div2_reg/QProp_GFF_SLICEM_C_Q JFDREXhzrD=b stat_regs_inst/ipb_clk_div2 Jnet (fo=3, routed)Xh%?Y '#stat_regs_inst/ipb_clk_div2_r_reg/D JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr stat_regs_inst/CLK Jnet (fo=204776, routed)XhX?X2Y4 (CLOCK_ROOT)W %!stat_regs_inst/ipb_clk_div2_reg/C JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzrt stat_regs_inst/clk250 Jnet (fo=17714, routed)XhQ?X3Y3 (CLOCK_ROOT)Y '#stat_regs_inst/ipb_clk_div2_r_reg/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ>o %!stat_regs_inst/ipb_clk_div2_r_regHold_AFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhöɿ; J arrival timeXhJ ?/ JXh4 JslackXh5B> #ctrl_regs_inst/regs_reg[7][0]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsup]?}Ͽ@5>z?@5?Q>А=>=pc>D=&Q?F?'1?Z9T?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)p #ctrl_regs_inst/regs_reg[7][0]/QProp_HFF_SLICEM_C_Q JFDCEXhzrD=x 51stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[0] Jnet (fo=2, routed)Xh&Q?h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xhz?X2Y4 (CLOCK_ROOT)U #ctrl_regs_inst/regs_reg[7][0]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh@5?X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ>~ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[0]Hold_EFF_SLICEM_C_D JFDCEXhA`e=/ JXh< J required timeXhϿ; J arrival timeXh2?/ JXh4 JslackXhpc>5 $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[2]/CE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j*clk250 rise@0.000ns - ipb_clk rise@0.000nsuU?}ǿOv>[d{?O?Q>А=>=&>`=;?lG?'1?nR?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)q $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H=y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xhq=>e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT3XhzrY=q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)XhV>i 73stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[2]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh[d{?X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)XhO?X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[2]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 40stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[2]Hold_EFF_SLICEL_C_CE JFDCEXh/ JXh< J required timeXhǿ; J arrival timeXhv?/ JXh4 JslackXh&>5 $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[4]/CE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j*clk250 rise@0.000ns - ipb_clk rise@0.000nsuU?}ǿOv>[d{?O?Q>А=>=&>`=;?lG?'1?nR?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)q $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H=y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xhq=>e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT3XhzrY=q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)XhV>i 73stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[4]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh[d{?X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)XhO?X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[4]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 40stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[4]Hold_FFF_SLICEL_C_CE JFDCEXh/ JXh< J required timeXhǿ; J arrival timeXhv?/ JXh4 JslackXh&> #ctrl_regs_inst/regs_reg[7][7]/C62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/D"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZj*clk250 rise@0.000ns - ipb_clk rise@0.000nsuZd?}οOv>[d{?O?Q>А=>=!->D=bX?lG?'1?nR?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Fastclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR)p #ctrl_regs_inst/regs_reg[7][7]/QProp_HFF_SLICEM_C_Q JFDCEXhzrD=x 51stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[7] Jnet (fo=2, routed)XhbX?h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/D JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh[d{?X2Y4 (CLOCK_ROOT)U #ctrl_regs_inst/regs_reg[7][7]/C JFDCEXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)XhO?X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]Hold_FFF2_SLICEL_C_D JFDCEXhGa=/ JXh< J required timeXhο; J arrival timeXh $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]/CE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsuh5@}@{@9@Q>А=>=mf?(>I "@c?@+?j?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PEq $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh%a?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT3Xhzr)>q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xh?i 73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh9@X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh9@X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[5]Setup_EFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh{@; J arrival timeXh/ JXh4 JslackXhmf? $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/CE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsuh5@}@{@9@Q>А=>=mf?(>I "@c?@+?j?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PEq $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh%a?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT3Xhzr)>q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xh?i 73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh9@X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh9@X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[7]Setup_FFF2_SLICEL_C_CE JFDCEXhim/ JXh< J required timeXh{@; J arrival timeXh/ JXh4 JslackXhmf? $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/CE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsuB`5@}@\@9@Q>А=>=g?(>#!@c?@+?j?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PEq $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh%a?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT3Xhzr)>q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xh33?i 73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh9@X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh9@X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[4]Setup_EFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh\@; J arrival timeXh/ JXh4 JslackXhg? $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/CE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsuB`5@}@\@9@Q>А=>=g?(>#!@c?@+?j?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PEq $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh%a?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT3Xhzr)>q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xh33?i 73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh9@X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh9@X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[6]Setup_FFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh\@; J arrival timeXh/ JXh4 JslackXhg? $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]/CE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsuB`5@}@\@9@Q>А=>=g?(>#!@c?@+?j?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PEq $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh%a?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT3Xhzr)>q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xh33?i 73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh9@X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh9@X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[8]Setup_GFF_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh\@; J arrival timeXh/ JXh4 JslackXhg?8 $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/CE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsu*@}@G@:6T<9@:@@Q>А=>=H ?(>l@c?@+?z?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)q $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh%a?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT3Xhzr)>q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)XhV?i 73stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh9@X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh:@X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[0]Setup_EFF2_SLICEM_C_CE JFDCEXhim/ JXh< J required timeXhG@; J arrival timeXh5^/ JXh4 JslackXhH ?7 $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/CE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsu*@}@@:6T<9@:@@Q>А=>=?(>d;@c?@+?z?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)q $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh%a?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT3Xhzr)>q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xh?i 73stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh9@X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh:@X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_addr_reg[3]Setup_EFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh@; J arrival timeXhE/ JXh4 JslackXh?7 $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/CE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsu*@}@@:6T<9@:@@Q>А=>=?(>d;@c?@+?z?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)q $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh%a?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT3Xhzr)>q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)Xh?i 73stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh9@X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh:@X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/reset_type_reg[1]Setup_FFF_SLICEM_C_CE JFDCEXhGa/ JXh< J required timeXh@; J arrival timeXhE/ JXh4 JslackXh?8 $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]/CE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsu@}@@9j9@9@@Q>А=>=@?(>rh @c?@+?(?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)q $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh%a?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT3Xhzr)>q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)XhM?i 73stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh9@X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh9@X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[1]Setup_AFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh@; J arrival timeXh)\/ JXh4 JslackXh@?8 $ ctrl_regs_inst/regs_reg[7][31]/C73stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[7]/CE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT:X3Y3BJZ(LUT3=1)j*clk250 rise@4.000ns - ipb_clk rise@0.000nsu@}@@9j9@9@@Q>А=>=@?(>rh @c?@+?(?b(rising edge-triggered cell FDCE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(rising edge-triggered cell FDCE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})Slowclk250ipb_clkclk250((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)q $ ctrl_regs_inst/regs_reg[7][31]/QProp_EFF_SLICEM_C_Q JFDCEXhzrV>y 62stat_regs_inst/i_cntr_rst_ctrl/rst_cycle_reg_0[11] Jnet (fo=3, routed)Xh%a?e 73stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/I1 JXhzr 62stat_regs_inst/i_cntr_rst_ctrl/start_addr[8]_i_1/OProp_B6LUT_SLICEL_I1_O JLUT3Xhzr)>q -)stat_regs_inst/i_cntr_rst_ctrl/reset_type Jnet (fo=20, routed)XhM?i 73stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[7]/CE JFDCEXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrr ctrl_regs_inst/CLK Jnet (fo=204776, routed)Xh9@X2Y4 (CLOCK_ROOT)V $ ctrl_regs_inst/regs_reg[7][31]/C JFDCEXhzrJ J(clock clk250 rise edge)Xhzr@M i_clk250_bufg/O JBUFGCEXhzr )%stat_regs_inst/i_cntr_rst_ctrl/clk250 Jnet (fo=17714, routed)Xh9@X3Y3 (CLOCK_ROOT)h 62stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[7]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ 40stat_regs_inst/i_cntr_rst_ctrl/start_addr_reg[7]Setup_BFF2_SLICEL_C_CE JFDCEXhGa/ JXh< J required timeXh@; J arrival timeXh)\/ JXh4 JslackXh@? clk250ipb_clk!)?1@9A/@I?@eZ ?hq}6֨<6BD rise - rise rise - rise  [ =9g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[1]/C;7g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[1]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu>}h׿"=Q??Q>А=>=֨<9H=!>E>U?gff>L7?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) =9g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[1]/QProp_DFF_SLICEM_C_Q JFDREXhzr9H= @m ;7g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[1]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[18].i_rate_ngccm_status2/clk250 Jnet (fo=17714, routed)XhQ?X3Y3 (CLOCK_ROOT)o =9g_clock_rate_din[18].i_rate_ngccm_status2/rate_i_reg[1]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[18].i_rate_ngccm_status2/CLK Jnet (fo=204776, routed)Xh?X2Y4 (CLOCK_ROOT)m ;7g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[1]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> 95g_clock_rate_din[18].i_rate_ngccm_status2/rate_reg[1]Hold_EFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhh׿; J arrival timeXhC?/ JXh4 JslackXh֨<e >:g_clock_rate_din[43].i_rate_ngccm_status2/rate_i_reg[47]/C<8g_clock_rate_din[43].i_rate_ngccm_status2/rate_reg[47]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsuC>}h׿=r??Q>А=>=֨<D=!>E>U?gff>L7?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[43].i_rate_ngccm_status2/rate_i_reg[47]/QProp_CFF2_SLICEL_C_Q JFDREXhzrD= A=g_clock_rate_din[43].i_rate_ngccm_status2/rate_i_reg_n_0_[47] Jnet (fo=1, routed)Xh!>n <8g_clock_rate_din[43].i_rate_ngccm_status2/rate_reg[47]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[43].i_rate_ngccm_status2/clk250 Jnet (fo=17714, routed)Xhr?X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[43].i_rate_ngccm_status2/rate_i_reg[47]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[43].i_rate_ngccm_status2/CLK Jnet (fo=204776, routed)Xh?X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[43].i_rate_ngccm_status2/rate_reg[47]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[43].i_rate_ngccm_status2/rate_reg[47]Hold_GFF2_SLICEL_C_D JFDREXhA`e=/ JXh< J required timeXhh׿; J arrival timeXhC?/ JXh4 JslackXh֨<c >:g_clock_rate_din[45].i_rate_ngccm_status1/rate_i_reg[21]/C<8g_clock_rate_din[45].i_rate_ngccm_status1/rate_reg[21]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsuҍ>}@˷gf_e'1?gf?Q>А=>=֨<9H=xi>E>~?5?gff>53s?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[45].i_rate_ngccm_status1/rate_i_reg[21]/QProp_AFF_SLICEM_C_Q JFDREXhzr9H= A=g_clock_rate_din[45].i_rate_ngccm_status1/rate_i_reg_n_0_[21] Jnet (fo=1, routed)Xhxi>n <8g_clock_rate_din[45].i_rate_ngccm_status1/rate_reg[21]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[45].i_rate_ngccm_status1/clk250 Jnet (fo=17714, routed)Xh'1?X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[45].i_rate_ngccm_status1/rate_i_reg[21]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[45].i_rate_ngccm_status1/CLK Jnet (fo=204776, routed)Xhgf?X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[45].i_rate_ngccm_status1/rate_reg[21]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[45].i_rate_ngccm_status1/rate_reg[21]Hold_EFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXh@˷; J arrival timeXh㥻?/ JXh4 JslackXh֨<( 84g_clock_rate_din[4].i_rate_test_comm/rate_i_reg[0]/C62g_clock_rate_din[4].i_rate_test_comm/rate_reg[0]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsut>}D!ֿk-=?k?Q>А=>=֨<9H=5^>E>O?gff>?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) 84g_clock_rate_din[4].i_rate_test_comm/rate_i_reg[0]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H=~ ;7g_clock_rate_din[4].i_rate_test_comm/rate_i_reg_n_0_[0] Jnet (fo=1, routed)Xh5^>h 62g_clock_rate_din[4].i_rate_test_comm/rate_reg[0]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr /+g_clock_rate_din[4].i_rate_test_comm/clk250 Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT)j 84g_clock_rate_din[4].i_rate_test_comm/rate_i_reg[0]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr ,(g_clock_rate_din[4].i_rate_test_comm/CLK Jnet (fo=204776, routed)Xhk?X2Y4 (CLOCK_ROOT)h 62g_clock_rate_din[4].i_rate_test_comm/rate_reg[0]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ>~ 40g_clock_rate_din[4].i_rate_test_comm/rate_reg[0]Hold_EFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhD!ֿ; J arrival timeXh?/ JXh4 JslackXh֨<d >:g_clock_rate_din[13].i_rate_ngccm_status2/rate_i_reg[19]/C<8g_clock_rate_din[13].i_rate_ngccm_status2/rate_reg[19]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu+>}ҿ8@=?8?Q>А=>=<9H={>E>N?gff>k?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[13].i_rate_ngccm_status2/rate_i_reg[19]/QProp_DFF2_SLICEM_C_Q JFDREXhzr9H= A=g_clock_rate_din[13].i_rate_ngccm_status2/rate_i_reg_n_0_[19] Jnet (fo=1, routed)Xh{>n <8g_clock_rate_din[13].i_rate_ngccm_status2/rate_reg[19]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[13].i_rate_ngccm_status2/clk250 Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[13].i_rate_ngccm_status2/rate_i_reg[19]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[13].i_rate_ngccm_status2/CLK Jnet (fo=204776, routed)Xh8?X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[13].i_rate_ngccm_status2/rate_reg[19]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[13].i_rate_ngccm_status2/rate_reg[19]Hold_EFF_SLICEM_C_D JFDREXhA`e=/ JXh< J required timeXhҿ; J arrival timeXh?/ JXh4 JslackXh<e >:g_clock_rate_din[28].i_rate_ngccm_status1/rate_i_reg[33]/C<8g_clock_rate_din[28].i_rate_ngccm_status1/rate_reg[33]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu>}ĿТG=k?Т?Q>А=>=<9H=F>E>V.?gff>?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[28].i_rate_ngccm_status1/rate_i_reg[33]/QProp_AFF2_SLICEM_C_Q JFDREXhzr9H= A=g_clock_rate_din[28].i_rate_ngccm_status1/rate_i_reg_n_0_[33] Jnet (fo=1, routed)XhF>n <8g_clock_rate_din[28].i_rate_ngccm_status1/rate_reg[33]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[28].i_rate_ngccm_status1/clk250 Jnet (fo=17714, routed)Xhk?X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[28].i_rate_ngccm_status1/rate_i_reg[33]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[28].i_rate_ngccm_status1/CLK Jnet (fo=204776, routed)XhТ?X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[28].i_rate_ngccm_status1/rate_reg[33]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[28].i_rate_ngccm_status1/rate_reg[33]Hold_EFF2_SLICEM_C_D JFDREXhGa=/ JXh< J required timeXhĿ; J arrival timeXh?/ JXh4 JslackXh<d >:g_clock_rate_din[31].i_rate_ngccm_status1/rate_i_reg[20]/C<8g_clock_rate_din[31].i_rate_ngccm_status1/rate_reg[20]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu>}¿Ġ"/=?Ġ?Q>А=>=<9H=!>E>*?gff>?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[31].i_rate_ngccm_status1/rate_i_reg[20]/QProp_EFF_SLICEL_C_Q JFDREXhzr9H= A=g_clock_rate_din[31].i_rate_ngccm_status1/rate_i_reg_n_0_[20] Jnet (fo=1, routed)Xh!>n <8g_clock_rate_din[31].i_rate_ngccm_status1/rate_reg[20]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[31].i_rate_ngccm_status1/clk250 Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[31].i_rate_ngccm_status1/rate_i_reg[20]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[31].i_rate_ngccm_status1/CLK Jnet (fo=204776, routed)XhĠ?X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[31].i_rate_ngccm_status1/rate_reg[20]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[31].i_rate_ngccm_status1/rate_reg[20]Hold_FFF2_SLICEL_C_D JFDREXhGa=/ JXh< J required timeXh¿; J arrival timeXhT?/ JXh4 JslackXh<d >:g_clock_rate_din[38].i_rate_ngccm_status2/rate_i_reg[30]/C<8g_clock_rate_din[38].i_rate_ngccm_status2/rate_reg[30]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu>}ֿ~?=r?~??Q>А=>=<D=>E>U?gff>r?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[38].i_rate_ngccm_status2/rate_i_reg[30]/QProp_CFF_SLICEM_C_Q JFDREXhzrD= A=g_clock_rate_din[38].i_rate_ngccm_status2/rate_i_reg_n_0_[30] Jnet (fo=1, routed)Xh>n <8g_clock_rate_din[38].i_rate_ngccm_status2/rate_reg[30]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[38].i_rate_ngccm_status2/clk250 Jnet (fo=17714, routed)Xhr?X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[38].i_rate_ngccm_status2/rate_i_reg[30]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[38].i_rate_ngccm_status2/CLK Jnet (fo=204776, routed)Xh~??X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[38].i_rate_ngccm_status2/rate_reg[30]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[38].i_rate_ngccm_status2/rate_reg[30]Hold_FFF2_SLICEM_C_D JFDREXhGa=/ JXh< J required timeXhֿ; J arrival timeXh5^?/ JXh4 JslackXh<e >:g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[34]/C<8g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[34]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu>}'=??Q>А=>=<9H=>E>*?gff>F?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[34]/QProp_DFF2_SLICEL_C_Q JFDREXhzr9H= A=g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg_n_0_[34] Jnet (fo=1, routed)Xh>n <8g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[34]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[43].i_rate_ngccm_status1/clk250 Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[43].i_rate_ngccm_status1/rate_i_reg[34]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[43].i_rate_ngccm_status1/CLK Jnet (fo=204776, routed)Xh?X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[34]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[43].i_rate_ngccm_status1/rate_reg[34]Hold_EFF2_SLICEL_C_D JFDREXhGa=/ JXh< J required timeXh'; J arrival timeXhˡ?/ JXh4 JslackXh<e >:g_clock_rate_din[45].i_rate_ngccm_status2/rate_i_reg[15]/C<8g_clock_rate_din[45].i_rate_ngccm_status2/rate_reg[15]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj*ipb_clk rise@0.000ns - clk250 rise@0.000nsu>}?׿,=?,?Q>А=>=<9H=>E>V?gff>_?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fastipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) >:g_clock_rate_din[45].i_rate_ngccm_status2/rate_i_reg[15]/QProp_AFF2_SLICEL_C_Q JFDREXhzr9H= A=g_clock_rate_din[45].i_rate_ngccm_status2/rate_i_reg_n_0_[15] Jnet (fo=1, routed)Xh>n <8g_clock_rate_din[45].i_rate_ngccm_status2/rate_reg[15]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[45].i_rate_ngccm_status2/clk250 Jnet (fo=17714, routed)Xh?X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[45].i_rate_ngccm_status2/rate_i_reg[15]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[45].i_rate_ngccm_status2/CLK Jnet (fo=204776, routed)Xh,?X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[45].i_rate_ngccm_status2/rate_reg[15]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ> :6g_clock_rate_din[45].i_rate_ngccm_status2/rate_reg[15]Hold_EFF2_SLICEL_C_D JFDREXhGa=/ JXh< J required timeXh?׿; J arrival timeXh?/ JXh4 JslackXh<h >:g_clock_rate_din[27].i_rate_ngccm_status1/rate_i_reg[17]/C<8g_clock_rate_din[27].i_rate_ngccm_status1/rate_reg[17]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsu/@}@F B}?-yN@A}?-@BQ>А=>=Z ?O >'@?? ?M @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >:g_clock_rate_din[27].i_rate_ngccm_status1/rate_i_reg[17]/QProp_EFF2_SLICEL_C_Q JFDREXhzrO > A=g_clock_rate_din[27].i_rate_ngccm_status1/rate_i_reg_n_0_[17] Jnet (fo=1, routed)Xh'@n <8g_clock_rate_din[27].i_rate_ngccm_status1/rate_reg[17]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[27].i_rate_ngccm_status1/clk250 Jnet (fo=17714, routed)XhN@X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[27].i_rate_ngccm_status1/rate_i_reg[17]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[27].i_rate_ngccm_status1/CLK Jnet (fo=204776, routed)Xh}?-@X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[27].i_rate_ngccm_status1/rate_reg[17]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ :6g_clock_rate_din[27].i_rate_ngccm_status1/rate_reg[17]Setup_DFF2_SLICEL_C_D JFDREXhL7=/ JXh< J required timeXhF B; J arrival timeXh/ JXh4 JslackXhZ ?f >:g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg[19]/C<8g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[19]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsu@}@` B^!Ηʡm@A^!@BQ>А=>=Y6?)\>ˡ??@ ?g?_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >:g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg[19]/QProp_AFF_SLICEM_C_Q JFDREXhzr)\> A=g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg_n_0_[19] Jnet (fo=1, routed)Xhˡ?n <8g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[19]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[34].i_rate_ngccm_status1/clk250 Jnet (fo=17714, routed)Xhʡm@X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[34].i_rate_ngccm_status1/rate_i_reg[19]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[34].i_rate_ngccm_status1/CLK Jnet (fo=204776, routed)Xh^!@X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[19]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ :6g_clock_rate_din[34].i_rate_ngccm_status1/rate_reg[19]Setup_EFF_SLICEM_C_D JFDREXho=/ JXh< J required timeXh` B; J arrival timeXh/ JXh4 JslackXhY6?\ =9g_clock_rate_din[3].i_rate_ngccm_status1/rate_i_reg[12]/C;7g_clock_rate_din[3].i_rate_ngccm_status1/rate_reg[12]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsu= /@}@< B,GM@A,@BQ>А=>=~?V>$&@?E? ?# @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) =9g_clock_rate_din[3].i_rate_ngccm_status1/rate_i_reg[12]/QProp_BFF_SLICEM_C_Q JFDREXhzrV> @ Jclock pessimismXh@ Jclock uncertaintyXhQ 95g_clock_rate_din[3].i_rate_ngccm_status1/rate_reg[12]Setup_EFF_SLICEM_C_D JFDREXho=/ JXh< J required timeXh< B; J arrival timeXh/ JXh4 JslackXh~?f >:g_clock_rate_din[24].i_rate_ngccm_status1/rate_i_reg[23]/C<8g_clock_rate_din[24].i_rate_ngccm_status1/rate_reg[23]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsuV.@}@A B}?-L@A}?-@BQ>А=>=#?V>p%@?? ?M @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >:g_clock_rate_din[24].i_rate_ngccm_status1/rate_i_reg[23]/QProp_FFF_SLICEL_C_Q JFDREXhzrV> A=g_clock_rate_din[24].i_rate_ngccm_status1/rate_i_reg_n_0_[23] Jnet (fo=1, routed)Xhp%@n <8g_clock_rate_din[24].i_rate_ngccm_status1/rate_reg[23]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[24].i_rate_ngccm_status1/clk250 Jnet (fo=17714, routed)XhL@X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[24].i_rate_ngccm_status1/rate_i_reg[23]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[24].i_rate_ngccm_status1/CLK Jnet (fo=204776, routed)Xh}?-@X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[24].i_rate_ngccm_status1/rate_reg[23]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ :6g_clock_rate_din[24].i_rate_ngccm_status1/rate_reg[23]Setup_BFF_SLICEL_C_D JFDREXh}=/ JXh< J required timeXhA B; J arrival timeXh?/ JXh4 JslackXh#?f >:g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg[23]/C<8g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[23]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsu33+@}@@[ B.` L7Q@A.@BQ>А=>=%%?V>M"@?v? ? @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >:g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg[23]/QProp_BFF_SLICEL_C_Q JFDREXhzrV> A=g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg_n_0_[23] Jnet (fo=1, routed)XhM"@n <8g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[23]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[21].i_rate_ngccm_status1/clk250 Jnet (fo=17714, routed)XhL7Q@X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg[23]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[21].i_rate_ngccm_status1/CLK Jnet (fo=204776, routed)Xh.@X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[23]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ :6g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[23]Setup_FFF_SLICEL_C_D JFDREXh%=/ JXh< J required timeXh@[ B; J arrival timeXh/ JXh4 JslackXh%%?^ =9g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[0]/C;7g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[0]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsuA(@}@y Bף@_/d@Aף@@BQ>А=>=&*?)\>K@?H@ ?.@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) =9g_clock_rate_din[10].i_rate_ngccm_status2/rate_i_reg[0]/QProp_AFF_SLICEL_C_Q JFDREXhzr)\> @ Jclock pessimismXh@ Jclock uncertaintyXhQ 95g_clock_rate_din[10].i_rate_ngccm_status2/rate_reg[0]Setup_EFF_SLICEL_C_D JFDREXho=/ JXh< J required timeXhy B; J arrival timeXh/ JXh4 JslackXh&*?^ =9g_clock_rate_din[8].i_rate_ngccm_status0/rate_i_reg[10]/C;7g_clock_rate_din[8].i_rate_ngccm_status0/rate_reg[10]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsuOb(@}@| B9@N7  c@A9@@BQ>А=>=o1?I >@?%@ ?@_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) =9g_clock_rate_din[8].i_rate_ngccm_status0/rate_i_reg[10]/QProp_DFF2_SLICEM_C_Q JFDREXhzrI > @ Jclock pessimismXh@ Jclock uncertaintyXhQ 95g_clock_rate_din[8].i_rate_ngccm_status0/rate_reg[10]Setup_EFF2_SLICEM_C_D JFDREXh=/ JXh< J required timeXh| B; J arrival timeXhF/ JXh4 JslackXho1?g >:g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg[22]/C<8g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[22]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsuE&@}@L] B.` L7Q@A.@BQ>А=>=H_9?O >p@?v? ? @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >:g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg[22]/QProp_CFF_SLICEL_C_Q JFDREXhzrO > A=g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg_n_0_[22] Jnet (fo=1, routed)Xhp@n <8g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[22]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[21].i_rate_ngccm_status1/clk250 Jnet (fo=17714, routed)XhL7Q@X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[21].i_rate_ngccm_status1/rate_i_reg[22]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[21].i_rate_ngccm_status1/CLK Jnet (fo=204776, routed)Xh.@X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[22]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ :6g_clock_rate_din[21].i_rate_ngccm_status1/rate_reg[22]Setup_EFF2_SLICEL_C_D JFDREXh=/ JXh< J required timeXhL] B; J arrival timeXhw/ JXh4 JslackXhH_9?f >:g_clock_rate_din[23].i_rate_ngccm_status0/rate_i_reg[29]/C<8g_clock_rate_din[23].i_rate_ngccm_status0/rate_reg[29]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsuV%@}@R B$.MbP@A$.@BQ>А=>=k;?O >V@?? ?23 @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >:g_clock_rate_din[23].i_rate_ngccm_status0/rate_i_reg[29]/QProp_CFF_SLICEM_C_Q JFDREXhzrO > A=g_clock_rate_din[23].i_rate_ngccm_status0/rate_i_reg_n_0_[29] Jnet (fo=1, routed)XhV@n <8g_clock_rate_din[23].i_rate_ngccm_status0/rate_reg[29]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[23].i_rate_ngccm_status0/clk250 Jnet (fo=17714, routed)XhMbP@X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[23].i_rate_ngccm_status0/rate_i_reg[29]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[23].i_rate_ngccm_status0/CLK Jnet (fo=204776, routed)Xh$.@X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[23].i_rate_ngccm_status0/rate_reg[29]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ :6g_clock_rate_din[23].i_rate_ngccm_status0/rate_reg[29]Setup_GFF_SLICEM_C_D JFDREXho=/ JXh< J required timeXhR B; J arrival timeXhZd/ JXh4 JslackXhk;?g >:g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg[20]/C<8g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[20]/D"$RCLK_CLEL_R_L_X50Y269/CLK_VDISTR_BOT*X3Y32$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZj,ipb_clk rise@32.000ns - clk250 rise@28.000nsu%@}@-X B+.'1uP@A+.@BQ>А=>=D@?/? ? @_(rising edge-triggered cell FDRE clocked by clk250 {rise@0.000ns fall@2.000ns period=4.000ns})b(rising edge-triggered cell FDRE clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Slowipb_clkclk250ipb_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) >:g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg[20]/QProp_DFF2_SLICEL_C_Q JFDREXhzrI > A=g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg_n_0_[20] Jnet (fo=1, routed)Xh@n <8g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[20]/D JFDREXhzrJ J(clock clk250 rise edge)XhzrAM i_clk250_bufg/O JBUFGCEXhzr 40g_clock_rate_din[22].i_rate_ngccm_status1/clk250 Jnet (fo=17714, routed)XhuP@X3Y3 (CLOCK_ROOT)p >:g_clock_rate_din[22].i_rate_ngccm_status1/rate_i_reg[20]/C JFDREXhzrK J(clock ipb_clk rise edge)XhzrBN i_ipb_clk_bufg/O JBUFGCEXhzr 1-g_clock_rate_din[22].i_rate_ngccm_status1/CLK Jnet (fo=204776, routed)Xh+.@X2Y4 (CLOCK_ROOT)n <8g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[20]/C JFDREXhzr> Jclock pessimismXh@ Jclock uncertaintyXhQ :6g_clock_rate_din[22].i_rate_ngccm_status1/rate_reg[20]Setup_GFF_SLICEL_C_D JFDREXho=/ JXh< J required timeXh-X B; J arrival timeXh`e/ JXh4 JslackXhD(@1Ë>8@9AM@IM @e?hq}ɑ<CL rise - rise rise - rise  E-)SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[40]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT5=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsuY9?}v޿Iz>?v?}>А={>=ɑ<A`=>>*\?n>#۩?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) z -)SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[40]/QProp_GFF_SLICEL_C_Q JFDREXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/TX_DATA_I[19] Jnet (fo=1, routed)Xhx> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[19]_i_1__124/I4 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[19]_i_1__124/OProp_C6LUT_SLICEL_I4_O JLUT5Xhzro= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[19] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[22].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[22].ngCCM_gbt/TX_Word_o_reg[40]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xhv?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[10].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]Hold_CFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh; J arrival timeXh@/ JXh4 JslackXhɑ<W-)SFP_GEN[23].ngCCM_gbt/TX_Word_o_reg[35]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsu?}ˡտ&y>ff?ˡ?}>А={>=ɑ<=X9>>?n>%?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) { -)SFP_GEN[23].ngCCM_gbt/TX_Word_o_reg[35]/QProp_FFF2_SLICEL_C_Q JFDREXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[14] Jnet (fo=1, routed)Xh{> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[14]_i_1__156/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[14]_i_1__156/OProp_A6LUT_SLICEL_I0_O JLUT3XhzrY= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[14] Jnet (fo=1, routed)XhD< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[23].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhff?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[23].ngCCM_gbt/TX_Word_o_reg[35]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xhˡ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[14]Hold_AFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh; J arrival timeXh'1@/ JXh4 JslackXhɑ<,(SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[2]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsuY9?}{ӿIz>X9??}>А={>=ɑ<=2>>z?n>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) y ,(SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[2]/QProp_HFF_SLICEL_C_Q JFDREXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[2] Jnet (fo=1, routed)Xh > g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[2]_i_1__159/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[2]_i_1__159/OProp_H6LUT_SLICEL_I0_O JLUT3Xhzr)\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[2] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[13].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhX9?X2Y4 (CLOCK_ROOT)^ ,(SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[2]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xh?X2Y4 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[2]Hold_HFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh{; J arrival timeXhV?/ JXh4 JslackXhɑ<-)SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[60]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsuOb?}-Gѿ k> ׳?G?}>А={>=ɑ<=V>>?n>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) { -)SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[60]/QProp_GFF2_SLICEL_C_Q JFDREXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[16] Jnet (fo=1, routed)XhA`> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[18]_i_1__161/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[18]_i_1__161/OProp_B6LUT_SLICEL_I2_O JLUT3XhzrY= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[18] Jnet (fo=1, routed)Xhu< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[13].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh ׳?X2Y4 (CLOCK_ROOT)_ -)SFP_GEN[13].ngCCM_gbt/TX_Word_o_reg[60]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)XhG?X2Y4 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[18]Hold_BFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh-; J arrival timeXh2?/ JXh4 JslackXhɑ<-)SFP_GEN[14].ngCCM_gbt/TX_Word_o_reg[37]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[16]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsu=?}ҿxi>µ??}>А={>=ɑ<F=>>?n>V?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) { -)SFP_GEN[14].ngCCM_gbt/TX_Word_o_reg[37]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[16] Jnet (fo=1, routed)Xh"> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[16]_i_1__152/I2 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[16]_i_1__152/OProp_B6LUT_SLICEL_I2_O JLUT3Xhzrrh= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[16] Jnet (fo=1, routed)Xhu< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[16]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[14].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhµ?X2Y4 (CLOCK_ROOT)_ -)SFP_GEN[14].ngCCM_gbt/TX_Word_o_reg[37]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xh?X2Y4 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[16]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[2].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[16]Hold_BFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh; J arrival timeXh.?/ JXh4 JslackXhɑ<N-)SFP_GEN[16].ngCCM_gbt/TX_Word_o_reg[12]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsu?} /ݿ}>p?/?}>А={>=ɑ<v=4^>>-?n>u?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) { -)SFP_GEN[16].ngCCM_gbt/TX_Word_o_reg[12]/QProp_HFF2_SLICEL_C_Q JFDREXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[12] Jnet (fo=1, routed)Xh -> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[12]_i_1__119/I1 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[12]_i_1__119/OProp_C6LUT_SLICEL_I1_O JLUT3XhzrQ8= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[12] Jnet (fo=1, routed)Xho< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[16].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhp?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[16].ngCCM_gbt/TX_Word_o_reg[12]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xh/?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]Hold_CFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh ; J arrival timeXh@/ JXh4 JslackXhɑ<B,(SFP_GEN[24].ngCCM_gbt/TX_Word_o_reg[8]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[8]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsuW9?}׿Iz>u??}>А={>=ɑ<=k>>Ԉ?n>S?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) y ,(SFP_GEN[24].ngCCM_gbt/TX_Word_o_reg[8]/QProp_HFF_SLICEM_C_Q JFDREXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[8] Jnet (fo=1, routed)Xhi> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[8]_i_1__283/I2 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[8]_i_1__283/OProp_G6LUT_SLICEL_I2_O JLUT3XhzrY= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[8] Jnet (fo=1, routed)XhA`e< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[8]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[24].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhu?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]^ ,(SFP_GEN[24].ngCCM_gbt/TX_Word_o_reg[8]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[8]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[8]Hold_GFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh; J arrival timeXhX@/ JXh4 JslackXhɑ<M-)SFP_GEN[24].ngCCM_gbt/TX_Word_o_reg[36]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[15]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsuP?}(8Qؿ>K?Q?}>А={>=ɑ<F= ->>Q?n>F?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) z -)SFP_GEN[24].ngCCM_gbt/TX_Word_o_reg[36]/QProp_HFF_SLICEL_C_Q JFDREXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[15] Jnet (fo=1, routed)Xh1> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[15]_i_1__248/I1 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[15]_i_1__248/OProp_A6LUT_SLICEL_I1_O JLUT3Xhzrrh= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[15] Jnet (fo=1, routed)XhD< g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[15]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[24].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhK?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[24].ngCCM_gbt/TX_Word_o_reg[36]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)XhQ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[15]Hold_AFF_SLICEL_C_D JFDCEXhA`e=/ JXh< J required timeXh(8; J arrival timeXh8@/ JXh4 JslackXhɑ<M-)SFP_GEN[37].ngCCM_gbt/TX_Word_o_reg[80]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsu$?}_ڿ/>t??}>А={>=ɑ<l=+?>G?n>$?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) z -)SFP_GEN[37].ngCCM_gbt/TX_Word_o_reg[80]/QProp_EFF_SLICEL_C_Q JFDREXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]_2[13] Jnet (fo=1, routed)Xho? g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[17]_i_1__330/I1 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[17]_i_1__330/OProp_C6LUT_SLICEL_I1_O JLUT3Xhzro= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[37].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xht?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[37].ngCCM_gbt/TX_Word_o_reg[80]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[1].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]Hold_CFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXh_; J arrival timeXh@/ JXh4 JslackXhɑ<N-)SFP_GEN[39].ngCCM_gbt/TX_Word_o_reg[80]/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - fabric_clk rise@0.000nsu?}u\ҿq>Z?\?}>А={>=ɑ<%=?>?n>?e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD - CPR) { -)SFP_GEN[39].ngCCM_gbt/TX_Word_o_reg[80]/QProp_CFF2_SLICEM_C_Q JFDREXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[20]_2[13] Jnet (fo=1, routed)Xh[d> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[17]_i_1__318/I1 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister[17]_i_1__318/OProp_C6LUT_SLICEL_I1_O JLUT3Xhzru< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/p_41_out[17] Jnet (fo=1, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[39].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhZ?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[39].ngCCM_gbt/TX_Word_o_reg[80]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xh\?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh}> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[17]Hold_CFF_SLICEL_C_D JFDPEXhA`e=/ JXh< J required timeXhu; J arrival timeXhO?/ JXh4 JslackXhɑ<d !fabric_clk_div2_reg_replica/C#fabric_clk_div2_q_reg[2]_srl3/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsuZ@}oA'AM:I&a@M:@oA}>А={>=?V>m@~j|?!@+g?@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})e(rising edge-triggered cell SRL16E clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ߾%M:@-5n !fabric_clk_div2_reg_replica/QProp_EFF_SLICEM_C_Q JFDREXhzrV>j &"fabric_clk_div2_bufg_place_replica Jnet (fo=51, routed)Xhm@D JXhSLR Crossing[1->0]W #fabric_clk_div2_q_reg[2]_srl3/D JSRL16EXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzrj  fabric_clk Jnet (fo=103803, routed)Xh&a@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]S !fabric_clk_div2_reg_replica/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzri  tx_wordclk Jnet (fo=27439, routed)XhM:@X2Y4 (CLOCK_ROOT)Y %!fabric_clk_div2_q_reg[2]_srl3/CLK JSRL16EXhzr> Jclock pessimismXhE Jinter-SLR compensationXh߾@ Jclock uncertaintyXh}r !fabric_clk_div2_q_reg[2]_srl3Setup_A6LUT_SLICEM_CLK_D JSRL16EXhGa/ JXh< J required timeXh'A; J arrival timeXhn/ JXh4 JslackXh?3,(SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[22]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT5=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsuTe@}oA7AVT׾^q@V@oA}>А={>=;@Z>XQ@~j|?2@+g?@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) y ,(SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[22]/QProp_EFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[1] Jnet (fo=2, routed)XhˡM@ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[20]_i_1__72/I1 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[20]_i_1__72/OProp_B5LUT_SLICEL_I1_O JLUT5Xhzr5^:> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[20] Jnet (fo=1, routed)Xhim= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[4].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh^q@X2Y4 (CLOCK_ROOT)^ ,(SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[22]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)XhV@X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]Setup_BFF2_SLICEL_C_D JFDCEXh+=/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXh;@,(SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[22]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsuJ b@}oA)7AVT׾^q@V@oA}>А={>=@n>wO@~j|?2@+g?@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) y ,(SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[22]/QProp_EFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[1] Jnet (fo=2, routed)XhˡM@ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[1]_i_1__60/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[1]_i_1__60/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzr+> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[1] Jnet (fo=1, routed)Xh+= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[4].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh^q@X2Y4 (CLOCK_ROOT)^ ,(SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[22]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)XhV@X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[1]Setup_BFF_SLICEL_C_D JFDCEXh}=/ JXh< J required timeXh)7A; J arrival timeXhT/ JXh4 JslackXh@,(SFP_GEN[6].ngCCM_gbt/TX_Word_o_reg[27]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[6]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsu[R@}oA7AV= o@V@oA}>А={>=J@>9@~j|?/@+g?/@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) y ,(SFP_GEN[6].ngCCM_gbt/TX_Word_o_reg[27]/QProp_EFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[6] Jnet (fo=1, routed)Xh8@ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[6]_i_1__36/I1 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[6]_i_1__36/OProp_F6LUT_SLICEM_I1_O JLUT3XhzrGz> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[6] Jnet (fo=1, routed)Xh< g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[6]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[6].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh= o@X2Y4 (CLOCK_ROOT)^ ,(SFP_GEN[6].ngCCM_gbt/TX_Word_o_reg[27]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)XhV@X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[6]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[6]Setup_FFF_SLICEM_C_D JFDPEXh%=/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXhJ@,(SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[19]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[19]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT5=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsuQN@}oAm7ApUihѾo@pU@oA}>А={>=׏@>}?5@~j|?0@+g?@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) z ,(SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[19]/QProp_HFF2_SLICEL_C_Q JFDREXhzrI > g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[19] Jnet (fo=1, routed)Xh"1@ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[19]_i_1__59/I4 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[19]_i_1__59/OProp_A5LUT_SLICEL_I4_O JLUT5Xhzrˡ> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[19] Jnet (fo=1, routed)XhY= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[19]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[4].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xho@X2Y4 (CLOCK_ROOT)^ ,(SFP_GEN[4].ngCCM_gbt/TX_Word_o_reg[19]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)XhpU@X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[19]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[4].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[19]Setup_AFF2_SLICEL_C_D JFDPEXh=/ JXh< J required timeXhm7A; J arrival timeXh+/ JXh4 JslackXh׏@+'SFP_GEN[6].ngCCM_gbt/TX_Word_o_reg[5]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[5]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsu%1@@}oA߾7A+V>5޾Mr@+V@oA}>А={>=A>@5^>`(@~j|?333@+g?k@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) x +'SFP_GEN[6].ngCCM_gbt/TX_Word_o_reg[5]/QProp_GFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_1[5] Jnet (fo=1, routed)Xh&@ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[5]_i_1__35/I2 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[5]_i_1__35/OProp_D6LUT_SLICEM_I2_O JLUT3Xhzrgff> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[5] Jnet (fo=1, routed)Xh*\= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[5]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[6].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhMr@X2Y4 (CLOCK_ROOT)] +'SFP_GEN[6].ngCCM_gbt/TX_Word_o_reg[5]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xh+V@X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[5]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[5]Setup_DFF_SLICEM_C_D JFDPEXh%=/ JXh< J required timeXh߾7A; J arrival timeXh|?/ JXh4 JslackXhA>@-)SFP_GEN[35].ngCCM_gbt/TX_Word_o_reg[40]/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT5=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsun;@}oA6A"S"q@"S@oA}>А={>=J@>1$@~j|?2@+g?X@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) { -)SFP_GEN[35].ngCCM_gbt/TX_Word_o_reg[40]/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[19] Jnet (fo=1, routed)Xh!@ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[19]_i_1__240/I4 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister[19]_i_1__240/OProp_C6LUT_SLICEL_I4_O JLUT5Xhzr֣p> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/p_41_out[19] Jnet (fo=1, routed)XhP= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[35].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh"q@X2Y4 (CLOCK_ROOT)_ -)SFP_GEN[35].ngCCM_gbt/TX_Word_o_reg[40]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xh"S@X2Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[19]Setup_CFF_SLICEL_C_D JFDPEXh%=/ JXh< J required timeXh6A; J arrival timeXhH/ JXh4 JslackXhJ@M-)SFP_GEN[18].ngCCM_gbt/TX_Word_o_reg[12]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsuC;@}oA=y3ApE辵\b@pE@oA}>А={>= @>Zd#@~j|?t#@+g? @e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDCE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) { -)SFP_GEN[18].ngCCM_gbt/TX_Word_o_reg[12]/QProp_FFF2_SLICEL_C_Q JFDREXhzrO > g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[20]_1[12] Jnet (fo=1, routed)Xh%!@ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[12]_i_1__95/I1 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister[12]_i_1__95/OProp_C6LUT_SLICEL_I1_O JLUT3Xhzr֣p> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/p_41_out[12] Jnet (fo=1, routed)XhP= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]/D JFDCEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[18].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh\b@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]_ -)SFP_GEN[18].ngCCM_gbt/TX_Word_o_reg[12]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)XhpE@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[6].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[0].gbtTxScrambler21bit/feedbackRegister_reg[12]Setup_CFF_SLICEL_C_D JFDCEXh%=/ JXh< J required timeXh=y3A; J arrival timeXhy/ JXh4 JslackXh @-)SFP_GEN[12].ngCCM_gbt/TX_Word_o_reg[56]/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsu1<@}oA7A+W;_p@+W@oA}>А={>=X@>#@~j|?1@+g?B`@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) z -)SFP_GEN[12].ngCCM_gbt/TX_Word_o_reg[56]/QProp_EFF_SLICEM_C_Q JFDREXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[12] Jnet (fo=1, routed)XhG!@ g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[14]_i_1__165/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[14]_i_1__165/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzr"y> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[14] Jnet (fo=1, routed)Xh*\= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[12].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh_p@X2Y4 (CLOCK_ROOT)_ -)SFP_GEN[12].ngCCM_gbt/TX_Word_o_reg[56]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xh+W@X2Y4 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[14]Setup_DFF_SLICEM_C_D JFDPEXh%=/ JXh< J required timeXh7A; J arrival timeXhv/ JXh4 JslackXhX@-)SFP_GEN[11].ngCCM_gbt/TX_Word_o_reg[59]/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[17]/D"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@8.317ns - fabric_clk rise@0.000nsu8@}oA7AVپ&q@V@oA}>А={>=_@5^>K7!@~j|?K 2@+g?W9@e(rising edge-triggered cell FDRE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow tx_wordclk fabric_clk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) z -)SFP_GEN[11].ngCCM_gbt/TX_Word_o_reg[59]/QProp_FFF_SLICEL_C_Q JFDREXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[20]_0[15] Jnet (fo=1, routed)Xh= @ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[17]_i_1__73/I1 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister[17]_i_1__73/OProp_B6LUT_SLICEM_I1_O JLUT3Xhzrgff> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/p_41_out[17] Jnet (fo=1, routed)XhC = g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[17]/D JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[11].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh&q@X2Y4 (CLOCK_ROOT)_ -)SFP_GEN[11].ngCCM_gbt/TX_Word_o_reg[59]/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)XhV@X2Y4 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[17]/C JFDPEXhzr> Jclock pessimismXh@ Jclock uncertaintyXh} g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[11].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[2].gbtTxScrambler21bit/feedbackRegister_reg[17]Setup_BFF_SLICEM_C_D JFDPEXh}=/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXh_@ **async_default**DRPclkDRPclk!)#@13@9A#@I3@eDwAhq}Vc>d rise - rise rise - rise  YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C{wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuҍ>}F пTL=\? ?Vc>Z9ʡ=J>>o?>Zd?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/QProp_BFF_SLICEL_C_Q JFDREXhzf9H= PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_4 Jnet (fo=2, routed)Xh)\= SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/I1 JXhzf RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/OProp_D6LUT_SLICEL_I1_O JLUT2Xhzf< njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xho> {wg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/DRPclk Jnet (fo=3888, routed)Xh\?X3Y4 (CLOCK_ROOT) YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh ?X3Y4 (CLOCK_ROOT) yug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXhZ9 wsg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_regRemov_HFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhF; J arrival timeXh?/ JXh4 JslackXhVc>  YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/Czvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuҍ>}F пTL=\? ?Vc>Z9ʡ=J>>o?>Zd?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/QProp_BFF_SLICEL_C_Q JFDREXhzf9H= PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_4 Jnet (fo=2, routed)Xh)\= SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/I1 JXhzf RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/OProp_D6LUT_SLICEL_I1_O JLUT2Xhzf< njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xho> zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/DRPclk Jnet (fo=3888, routed)Xh\?X3Y4 (CLOCK_ROOT) YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh ?X3Y4 (CLOCK_ROOT) xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXhZ9 vrg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_regRemov_EFF_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhF; J arrival timeXh?/ JXh4 JslackXhVc>  YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C|xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuҍ>}F пTL=\? ?Vc>Z9ʡ=J>>o?>Zd?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/QProp_BFF_SLICEL_C_Q JFDREXhzf9H= PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_4 Jnet (fo=2, routed)Xh)\= SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/I1 JXhzf RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/OProp_D6LUT_SLICEL_I1_O JLUT2Xhzf< njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xho> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/DRPclk Jnet (fo=3888, routed)Xh\?X3Y4 (CLOCK_ROOT) YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh ?X3Y4 (CLOCK_ROOT) zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXhZ9 xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_regRemov_EFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhF; J arrival timeXh?/ JXh4 JslackXhVc>  YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C|xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuҍ>}F пTL=\? ?Vc>Z9ʡ=J>>o?>Zd?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/QProp_BFF_SLICEL_C_Q JFDREXhzf9H= PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_4 Jnet (fo=2, routed)Xh)\= SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/I1 JXhzf RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/OProp_D6LUT_SLICEL_I1_O JLUT2Xhzf< njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xho> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/DRPclk Jnet (fo=3888, routed)Xh\?X3Y4 (CLOCK_ROOT) YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh ?X3Y4 (CLOCK_ROOT) zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXhZ9 xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_regRemov_FFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhF; J arrival timeXh?/ JXh4 JslackXhVc>  YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C|xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuҍ>}F пTL=\? ?Vc>Z9ʡ=J>>o?>Zd?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/QProp_BFF_SLICEL_C_Q JFDREXhzf9H= PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_4 Jnet (fo=2, routed)Xh)\= SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/I1 JXhzf RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27/OProp_D6LUT_SLICEL_I1_O JLUT2Xhzf< njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xho> |xg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/DRPclk Jnet (fo=3888, routed)Xh\?X3Y4 (CLOCK_ROOT) YUg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh ?X3Y4 (CLOCK_ROOT) zvg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXhZ9 xtg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_regRemov_GFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhF; J arrival timeXh?/ JXh4 JslackXhVc> (YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C{wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuG>}Qÿ+ֿ9=> ?+?v>E=}>>P?>ʡ?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/QProp_BFF_SLICEM_C_Q JFDREXhzf9H= PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_1 Jnet (fo=2, routed)Xh ף= SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf #= njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh1,> {wg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/DRPclk Jnet (fo=3888, routed)Xh> ?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh+?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] yug_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXh wsg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_regRemov_DFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhQÿ; J arrival timeXh-?/ JXh4 JslackXhv> ,YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C|xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuG>}Qÿ+ֿ9=> ?+?v>E=}>>P?>ʡ?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/QProp_BFF_SLICEM_C_Q JFDREXhzf9H= PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_1 Jnet (fo=2, routed)Xh ף= SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf #= njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh1,> |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/DRPclk Jnet (fo=3888, routed)Xh> ?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh+?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXh xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_regRemov_AFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhQÿ; J arrival timeXh-?/ JXh4 JslackXhv> ,YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C|xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuG>}Qÿ+ֿ9=> ?+?v>E=}>>P?>ʡ?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/QProp_BFF_SLICEM_C_Q JFDREXhzf9H= PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_1 Jnet (fo=2, routed)Xh ף= SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf #= njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh1,> |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/DRPclk Jnet (fo=3888, routed)Xh> ?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh+?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXh xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_regRemov_BFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhQÿ; J arrival timeXh-?/ JXh4 JslackXhv> ,YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C|xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuG>}Qÿ+ֿ9=> ?+?v>E=}>>P?>ʡ?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/QProp_BFF_SLICEM_C_Q JFDREXhzf9H= PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_1 Jnet (fo=2, routed)Xh ף= SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf #= njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh1,> |xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/DRPclk Jnet (fo=3888, routed)Xh> ?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh+?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXh xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_regRemov_CFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhQÿ; J arrival timeXh-?/ JXh4 JslackXhv> #YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/Czvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j)DRPclk rise@0.000ns - DRPclk rise@0.000nsuj>}rÿֿ K=> ??w> E=>>P?>?a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})^(removal check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Fast**async_default**DRPclkDRPclk(DCD - SCD - CPR) YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/QProp_BFF_SLICEM_C_Q JFDREXhzf9H= PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_1 Jnet (fo=2, routed)Xh ף= SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/I1 JXhzf RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf #= njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh{.> zvg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/DRPclk Jnet (fo=3888, routed)Xh> ?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh?X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] xtg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXh  vrg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_regRemov_AFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhrÿ; J arrival timeXhn?/ JXh4 JslackXhw> YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/Czvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuV@}AAV=k %Y@V=@A =А=k>DwA>X>u@ |?#@lg?33@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/QProp_HFF_SLICEM_C_Q JFDREXhzfO > MIg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_out Jnet (fo=2, routed)XhH? SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/I1 JXhzf RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/OProp_A6LUT_SLICEM_I1_O JLUT2XhzfA`e> njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xhb@ zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/DRPclk Jnet (fo=3888, routed)Xh%Y@X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)XhV=@X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh  vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_regRecov_AFF_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhA; J arrival timeXh/ JXh4 JslackXhDwA YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C{wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu@}A{A<r"%Y@<@A =А=k> wAW>X>/t@ |?#@lg?o@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/QProp_HFF_SLICEM_C_Q JFDREXhzfO > MIg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_out Jnet (fo=2, routed)XhH? SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/I1 JXhzf RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/OProp_A6LUT_SLICEM_I1_O JLUT2XhzfA`e> njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh? {wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/DRPclk Jnet (fo=3888, routed)Xh%Y@X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh<@X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] yug_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh  wsg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_regRecov_HFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh{A; J arrival timeXh,/ JXh4 JslackXh wA YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C|xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu@}A{A<r"%Y@<@A =А=k> wAW>X>/t@ |?#@lg?o@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/QProp_HFF_SLICEM_C_Q JFDREXhzfO > MIg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_out Jnet (fo=2, routed)XhH? SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/I1 JXhzf RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/OProp_A6LUT_SLICEM_I1_O JLUT2XhzfA`e> njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh? |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/DRPclk Jnet (fo=3888, routed)Xh%Y@X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh<@X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh  xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_regRecov_EFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh{A; J arrival timeXh,/ JXh4 JslackXh wA YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C|xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu@}A{A<r"%Y@<@A =А=k> wAW>X>/t@ |?#@lg?o@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/QProp_HFF_SLICEM_C_Q JFDREXhzfO > MIg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_out Jnet (fo=2, routed)XhH? SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/I1 JXhzf RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/OProp_A6LUT_SLICEM_I1_O JLUT2XhzfA`e> njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh? |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/DRPclk Jnet (fo=3888, routed)Xh%Y@X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh<@X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh  xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_regRecov_FFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh{A; J arrival timeXh,/ JXh4 JslackXh wA YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C|xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu@}A{A<r"%Y@<@A =А=k> wAW>X>/t@ |?#@lg?o@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/QProp_HFF_SLICEM_C_Q JFDREXhzfO > MIg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_out Jnet (fo=2, routed)XhH? SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/I1 JXhzf RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11/OProp_A6LUT_SLICEM_I1_O JLUT2XhzfA`e> njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh? |xg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr LHg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/DRPclk Jnet (fo=3888, routed)Xh%Y@X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh<@X3Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh  xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_regRecov_GFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh{A; J arrival timeXh,/ JXh4 JslackXh wA ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C|xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu2L@}AAUi彵ffv@U@A =А=k>;9AJ->S>'18@ |?d;7@lg?@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV> QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 Jnet (fo=2, routed)XhX?} OKg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/I1 JXhzf NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf/> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh> ? |xg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr MIg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/DRPclk Jnet (fo=3888, routed)Xhffv@X3Y4 (CLOCK_ROOT) ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)XhU@X3Y4 (CLOCK_ROOT) zvg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXhJ->@ Jclock uncertaintyXh  xtg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_regRecov_DFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhA; J arrival timeXhL7/ JXh4 JslackXh;9A ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C}yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu2L@}AAUi彵ffv@U@A =А=k>;9AJ->S>'18@ |?d;7@lg?@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV> QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 Jnet (fo=2, routed)XhX?} OKg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/I1 JXhzf NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf/> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh> ? }yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr MIg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/DRPclk Jnet (fo=3888, routed)Xhffv@X3Y4 (CLOCK_ROOT) ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)XhU@X3Y4 (CLOCK_ROOT) {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXhJ->@ Jclock uncertaintyXh  yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_regRecov_AFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhA; J arrival timeXhL7/ JXh4 JslackXh;9A ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C}yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu2L@}AAUi彵ffv@U@A =А=k>;9AJ->S>'18@ |?d;7@lg?@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV> QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 Jnet (fo=2, routed)XhX?} OKg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/I1 JXhzf NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf/> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh> ? }yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr MIg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/DRPclk Jnet (fo=3888, routed)Xhffv@X3Y4 (CLOCK_ROOT) ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)XhU@X3Y4 (CLOCK_ROOT) {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXhJ->@ Jclock uncertaintyXh  yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_regRecov_BFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhA; J arrival timeXhL7/ JXh4 JslackXh;9A ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C}yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsu2L@}AAUi彵ffv@U@A =А=k>;9AJ->S>'18@ |?d;7@lg?@a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV> QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 Jnet (fo=2, routed)XhX?} OKg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/I1 JXhzf NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf/> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh> ? }yg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr MIg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/DRPclk Jnet (fo=3888, routed)Xhffv@X3Y4 (CLOCK_ROOT) ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)XhU@X3Y4 (CLOCK_ROOT) {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXhJ->@ Jclock uncertaintyXh  yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_regRecov_CFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhA; J arrival timeXhL7/ JXh4 JslackXh;9A  ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C{wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE"$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X60Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT2=1)j*DRPclk rise@20.000ns - DRPclk rise@0.000nsuYdK@}AA-U齵ffv@-U@A =А=k>IA&5>S>P7@ |?d;7@lg? @a(rising edge-triggered cell FDRE clocked by DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})_(recovery check against rising-edge clock DRPclk {rise@0.000ns fall@10.000ns period=20.000ns})Slow**async_default**DRPclkDRPclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/QProp_DFF_SLICEL_C_Q JFDREXhzfV> QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/reset_all_init_11 Jnet (fo=2, routed)XhX?} OKg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/I1 JXhzf NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3/OProp_D5LUT_SLICEM_I1_O JLUT2Xhzf/> okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh? {wg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock DRPclk rise edge)XhzrM i_DRPclk_bufg/O JBUFGCEXhzr MIg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/DRPclk Jnet (fo=3888, routed)Xhffv@X3Y4 (CLOCK_ROOT) ZVg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_all_out_reg/C JFDREXhzrJ J(clock DRPclk rise edge)XhzrAM i_DRPclk_bufg/O JBUFGCEXhzr okg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3888, routed)Xh-U@X3Y4 (CLOCK_ROOT) yug_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXh&5>@ Jclock uncertaintyXh  wsg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_regRecov_EFF_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhA; J arrival timeXh_/ JXh4 JslackXhIA  **async_default** TTC_rxusrclk TTC_rxusrclk!)Ë>?1Ë>@9AË>?IË>@e<>hq}>d rise - rise rise - rise  j d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/CEAi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg/PRE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuSc>}ۿNbog= ?Nb?>X+D=-2>`0?*\o?ʡE?h?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= >:i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n Jnet (fo=6, routed)Xh-2>w EAi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg/PRE JFDPEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr >:i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] Jnet (fo=1861, routed)Xh ?X3Y2 (CLOCK_ROOT) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 Jnet (fo=1861, routed)XhNb?X3Y2 (CLOCK_ROOT)u C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXhX+ A=i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_regRemov_EFF_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhۿ; J arrival timeXhD?/ JXh4 JslackXh>o d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/CFBi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg/PRE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsurh>}ۿ֣9= ?֣?a >U+D=K7>`0?*\o?ʡE?ҍ?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= >:i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n Jnet (fo=6, routed)XhK7>x FBi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg/PRE JFDPEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr >:i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] Jnet (fo=1861, routed)Xh ?X3Y2 (CLOCK_ROOT) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 Jnet (fo=1861, routed)Xh֣?X3Y2 (CLOCK_ROOT)v D@i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXhU+ B>i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_meta_regRemov_DFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhۿ; J arrival timeXh/?/ JXh4 JslackXha >s d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/CGCi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg/PRE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsurh>}ۿ֣9= ?֣?a >U+D=K7>`0?*\o?ʡE?ҍ?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= >:i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n Jnet (fo=6, routed)XhK7>y GCi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg/PRE JFDPEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr >:i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] Jnet (fo=1861, routed)Xh ?X3Y2 (CLOCK_ROOT) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 Jnet (fo=1861, routed)Xh֣?X3Y2 (CLOCK_ROOT)w EAi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXhU+ C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync1_regRemov_AFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhۿ; J arrival timeXh/?/ JXh4 JslackXha >s d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/CGCi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg/PRE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsurh>}ۿ֣9= ?֣?a >U+D=K7>`0?*\o?ʡE?ҍ?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= >:i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n Jnet (fo=6, routed)XhK7>y GCi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg/PRE JFDPEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr >:i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] Jnet (fo=1861, routed)Xh ?X3Y2 (CLOCK_ROOT) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 Jnet (fo=1861, routed)Xh֣?X3Y2 (CLOCK_ROOT)w EAi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXhU+ C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync2_regRemov_BFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhۿ; J arrival timeXh/?/ JXh4 JslackXha >s d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/CGCi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync3_reg/PRE"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsurh>}ۿ֣9= ?֣?a >U+D=K7>`0?*\o?ʡE?ҍ?e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/QProp_BFF2_SLICEL_C_Q JFDCEXhzrD= >:i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rx_active_n Jnet (fo=6, routed)XhK7>y GCi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync3_reg/PRE JFDPEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr >:i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] Jnet (fo=1861, routed)Xh ?X3Y2 (CLOCK_ROOT) d`i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_sync_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_out_reg_0 Jnet (fo=1861, routed)Xh֣?X3Y2 (CLOCK_ROOT)w EAi_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXhU+ C?i_tcds2_if/i_mgt_wrapper/i_buffbypass_rx_reset/rst_in_sync3_regRemov_CFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhۿ; J arrival timeXh/?/ JXh4 JslackXha > ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C[Wi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[41]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuA`>}Rڿ￭Ӎ=`??>c+D=/>`0?_p?ʡE?I?e(rising edge-triggered cell FDPE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/QProp_HFF2_SLICEL_C_Q JFDPEXhzfD= TPi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s Jnet (fo=549, routed)Xh/> [Wi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[41]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh`?X3Y2 (CLOCK_ROOT) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C JFDPEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) YUi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[41]/C JFDCEXhzr> Jclock pessimismXhc+ WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[41]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhRڿ; J arrival timeXh?/ JXh4 JslackXh> ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C[Wi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[53]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuA`>}Rڿ￭Ӎ=`??>c+D=/>`0?_p?ʡE?I?e(rising edge-triggered cell FDPE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/QProp_HFF2_SLICEL_C_Q JFDPEXhzfD= TPi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s Jnet (fo=549, routed)Xh/> [Wi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[53]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh`?X3Y2 (CLOCK_ROOT) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C JFDPEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) YUi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[53]/C JFDCEXhzr> Jclock pessimismXhc+ WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[53]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhRڿ; J arrival timeXh?/ JXh4 JslackXh> ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C[Wi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[61]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuA`>}Rڿ￭Ӎ=`??>c+D=/>`0?_p?ʡE?I?e(rising edge-triggered cell FDPE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/QProp_HFF2_SLICEL_C_Q JFDPEXhzfD= TPi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s Jnet (fo=549, routed)Xh/> [Wi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[61]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh`?X3Y2 (CLOCK_ROOT) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C JFDPEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) YUi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[61]/C JFDCEXhzr> Jclock pessimismXhc+ WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[61]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhRڿ; J arrival timeXh?/ JXh4 JslackXh> ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C[Wi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[63]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuA`>}Rڿ￭Ӎ=`??>c+D=/>`0?_p?ʡE?I?e(rising edge-triggered cell FDPE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/QProp_HFF2_SLICEL_C_Q JFDPEXhzfD= TPi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s Jnet (fo=549, routed)Xh/> [Wi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[63]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh`?X3Y2 (CLOCK_ROOT) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C JFDPEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) YUi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[63]/C JFDCEXhzr> Jclock pessimismXhc+ WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg0_reg[63]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhRڿ; J arrival timeXh?/ JXh4 JslackXh> ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C[Wi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[41]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@0.000ns - TTC_rxusrclk rise@0.000nsuA`>}Rڿ￭Ӎ=`??>c+D=/>`0?_p?ʡE?I?e(rising edge-triggered cell FDPE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})b(removal check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Fast**async_default** TTC_rxusrclk TTC_rxusrclk(DCD - SCD - CPR) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/QProp_HFF2_SLICEL_C_Q JFDPEXhzfD= TPi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s Jnet (fo=549, routed)Xh/> [Wi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[41]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh`?X3Y2 (CLOCK_ROOT) ZVi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/gbReset_s_reg/C JFDPEXhzrP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xh?X3Y2 (CLOCK_ROOT) YUi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[41]/C JFDCEXhzr> Jclock pessimismXhc+ WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/reg1_reg[41]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhRڿ; J arrival timeXh?/ JXh4 JslackXh> \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CB>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[186]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu3@}G@_@IlCC x@Il@G@=А=<> >)\>!*@)\?@/?- @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh!*@t B>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[186]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)XhIl@X3Y2 (CLOCK_ROOT)r @ Jclock pessimismXh >@ Jclock uncertaintyXh >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[186]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh_@; J arrival timeXhz/ JXh4 JslackXh<> \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CB>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[188]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu3@}G@_@IlCC x@Il@G@=А=<> >)\>!*@)\?@/?- @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh!*@t B>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[188]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)XhIl@X3Y2 (CLOCK_ROOT)r @ Jclock pessimismXh >@ Jclock uncertaintyXh >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[188]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh_@; J arrival timeXhz/ JXh4 JslackXh<> \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CA=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[37]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu3@}G@_@IlCC x@Il@G@=А=<> >)\>!*@)\?@/?- @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh!*@s A=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[37]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)XhIl@X3Y2 (CLOCK_ROOT)q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[37]/C JFDCEXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[37]Recov_FFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh_@; J arrival timeXhz/ JXh4 JslackXh<> \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CA=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[79]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu3@}G@_@IlCC x@Il@G@=А=<> >)\>!*@)\?@/?- @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xh!*@s A=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[79]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)XhIl@X3Y2 (CLOCK_ROOT)q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[79]/C JFDCEXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[79]Recov_FFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh_@; J arrival timeXhz/ JXh4 JslackXh<> \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CB>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[121]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu4@}G@q@pm(x@pm@G@=А=H> >)\>F+@)\?@/?@e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)XhF+@t B>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[121]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhpm@X3Y2 (CLOCK_ROOT)r @ Jclock pessimismXh >@ Jclock uncertaintyXh >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[121]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhq@; J arrival timeXh/ JXh4 JslackXhH> \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CB>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[111]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu/4@}G@ʚ@m84x@m@G@=А=BU> >)\>l+@)\?@/?+@e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xhl+@t B>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[111]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhm@X3Y2 (CLOCK_ROOT)r @ Jclock pessimismXh >@ Jclock uncertaintyXh >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[111]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhʚ@; J arrival timeXh / JXh4 JslackXhBU> \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CB>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[153]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu/4@}G@ʚ@m84x@m@G@=А=BU> >)\>l+@)\?@/?+@e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xhl+@t B>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[153]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhm@X3Y2 (CLOCK_ROOT)r @ Jclock pessimismXh >@ Jclock uncertaintyXh >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[153]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhʚ@; J arrival timeXh / JXh4 JslackXhBU> \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CB>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[154]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu/4@}G@ʚ@m84x@m@G@=А=BU> >)\>l+@)\?@/?+@e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xhl+@t B>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[154]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhm@X3Y2 (CLOCK_ROOT)r @ Jclock pessimismXh >@ Jclock uncertaintyXh >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[154]Recov_FFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhʚ@; J arrival timeXh / JXh4 JslackXhBU> \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CA=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu/4@}G@ʚ@m84x@m@G@=А=BU> >)\>l+@)\?@/?+@e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xhl+@s A=i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)Xhm@X3Y2 (CLOCK_ROOT)q ?;i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]/C JFDCEXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh =9i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[91]Recov_FFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhʚ@; J arrival timeXh / JXh4 JslackXhBU> \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/CB>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[160]/CLR"$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT*X3Y22$RCLK_CLEL_R_L_X49Y209/CLK_VDISTR_BOT:X3Y2BJZj5TTC_rxusrclk rise@3.119ns - TTC_rxusrclk rise@0.000nsu5^2@}G@@Ek 0x@Ek@G@=А=2$> >)\>rh)@)\?@/? @e(rising edge-triggered cell FDCE clocked by TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})c(recovery check against rising-edge clock TTC_rxusrclk {rise@0.000ns fall@1.559ns period=3.119ns})Slow**async_default** TTC_rxusrclk TTC_rxusrclk#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\>p +'i_tcds2_if/cmp_lpgbtfpga_uplink/reset_i Jnet (fo=731, routed)Xhrh)@t B>i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[160]/CLR JFDCEXhzfP J(clock TTC_rxusrclk rise edge)Xhzr WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr WSi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/rxusrclk_out Jnet (fo=1861, routed)Xhx@X3Y2 (CLOCK_ROOT) \Xi_tcds2_if/cmp_lpgbtfpga_uplink/rxgearbox_10g_gen.rxGearbox_10g24_inst/sta_gbRdy_o_reg/C JFDCEXhzrP J(clock TTC_rxusrclk rise edge)XhzrG@ WSi_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O JBUFG_GTXhzr 0,i_tcds2_if/cmp_lpgbtfpga_uplink/rxusrclk_out Jnet (fo=1861, routed)XhEk@X3Y2 (CLOCK_ROOT)r @ Jclock pessimismXh >@ Jclock uncertaintyXh >:i_tcds2_if/cmp_lpgbtfpga_uplink/frame_pipelined_s_reg[160]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh@; J arrival timeXhp/ JXh4 JslackXh2$>  **async_default**clk125clk125!)@1@9A@I@ec&@hq}+/L>+d rise - rise rise - rise  # IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Ckgi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsux>}U0)\Ͽ =?)\?/L>X}.D=G>X9>P?>p?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_HFF2_SLICEL_C_Q JFDREXhzfD= ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in Jnet (fo=7, routed)XhG> kgi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in Jnet (fo=3804, routed)Xh)\?X3Y4 (CLOCK_ROOT) iei_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXhX}. gci_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_regRemov_HFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhU0; J arrival timeXhF?/ JXh4 JslackXh/L> IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Cjfi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsux>}U0)\Ͽ =?)\?/L>X}.D=G>X9>P?>p?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_HFF2_SLICEL_C_Q JFDREXhzfD= ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in Jnet (fo=7, routed)XhG> jfi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in Jnet (fo=3804, routed)Xh)\?X3Y4 (CLOCK_ROOT) hdi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXhX}. fbi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_regRemov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhU0; J arrival timeXhF?/ JXh4 JslackXh/L>' IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Clhi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsux>}U0)\Ͽ =?)\?/L>X}.D=G>X9>P?>p?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_HFF2_SLICEL_C_Q JFDREXhzfD= ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in Jnet (fo=7, routed)XhG> lhi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in Jnet (fo=3804, routed)Xh)\?X3Y4 (CLOCK_ROOT) jfi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXhX}. hdi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_regRemov_EFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhU0; J arrival timeXhF?/ JXh4 JslackXh/L>' IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Clhi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsux>}U0)\Ͽ =?)\?/L>X}.D=G>X9>P?>p?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_HFF2_SLICEL_C_Q JFDREXhzfD= ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in Jnet (fo=7, routed)XhG> lhi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in Jnet (fo=3804, routed)Xh)\?X3Y4 (CLOCK_ROOT) jfi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXhX}. hdi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_regRemov_FFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhU0; J arrival timeXhF?/ JXh4 JslackXh/L>' IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Clhi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZj)clk125 rise@0.000ns - clk125 rise@0.000nsux>}U0)\Ͽ =?)\?/L>X}.D=G>X9>P?>p?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_HFF2_SLICEL_C_Q JFDREXhzfD= ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in Jnet (fo=7, routed)XhG> lhi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/clk_in Jnet (fo=3804, routed)Xh)\?X3Y4 (CLOCK_ROOT) jfi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXhX}. hdi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_regRemov_GFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhU0; J arrival timeXhF?/ JXh4 JslackXh/L> IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/Ceai_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT4=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsuv>}5꽿)\Ͽ=?)\?<>Yv=َ>X9>P?>p?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/QProp_HFF2_SLICEL_C_Q JFDREXhzfD= KGi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg_n_0 Jnet (fo=7, routed)Xht= YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/I0 JXhzf XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1/OProp_D6LUT_SLICEL_I0_O JLUT4XhzfQ8= YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in Jnet (fo=5, routed)XhS> eai_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT){ IEi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_rx_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/clk_in Jnet (fo=3804, routed)Xh)\?X3Y4 (CLOCK_ROOT) c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXhY a]i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_regRemov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh5꽿; J arrival timeXhX9?/ JXh4 JslackXh<> QMi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/Cfbi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu>}&ѿ=?&?Y0>v=R>X9>P?>d;?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) QMi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/QProp_GFF2_SLICEL_C_Q JFDREXhzfD= SOi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 Jnet (fo=2, routed)Xh= YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1/I0 JXhzf XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf< YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in Jnet (fo=10, routed)XhD> fbi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT) QMi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/clk_in Jnet (fo=3804, routed)Xh&?X3Y4 (CLOCK_ROOT) d`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXh b^i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_regRemov_HFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhE?/ JXh4 JslackXhY0>  QMi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/Ceai_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu>}&ѿ=?&?Y0>v=R>X9>P?>d;?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) QMi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/QProp_GFF2_SLICEL_C_Q JFDREXhzfD= SOi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 Jnet (fo=2, routed)Xh= YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1/I0 JXhzf XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf< YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in Jnet (fo=10, routed)XhD> eai_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT) QMi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/clk_in Jnet (fo=3804, routed)Xh&?X3Y4 (CLOCK_ROOT) c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXh a]i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_regRemov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhE?/ JXh4 JslackXhY0>  QMi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/Cgci_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu>}&ѿ=?&?Y0>v=R>X9>P?>d;?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) QMi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/QProp_GFF2_SLICEL_C_Q JFDREXhzfD= SOi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 Jnet (fo=2, routed)Xh= YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1/I0 JXhzf XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf< YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in Jnet (fo=10, routed)XhD> gci_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT) QMi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/clk_in Jnet (fo=3804, routed)Xh&?X3Y4 (CLOCK_ROOT) eai_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXh c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_regRemov_EFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhE?/ JXh4 JslackXhY0>  QMi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/Cgci_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@0.000ns - clk125 rise@0.000nsu>}&ѿ=?&?Y0>v=R>X9>P?>d;?_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})\(removal check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Fast**async_default**clk125clk125(DCD - SCD - CPR) QMi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/QProp_GFF2_SLICEL_C_Q JFDREXhzfD= SOi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg_n_0 Jnet (fo=2, routed)Xh= YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1/I0 JXhzf XTi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf< YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in Jnet (fo=10, routed)XhD> gci_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr /+i_tcds2_if/i_mgt_wrapper/i_reset_sm/CLKFBIN Jnet (fo=3804, routed)Xh?X3Y4 (CLOCK_ROOT) QMi_tcds2_if/i_mgt_wrapper/i_reset_sm/gtwiz_reset_tx_pll_and_datapath_int_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzr YUi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/clk_in Jnet (fo=3804, routed)Xh&?X3Y4 (CLOCK_ROOT) eai_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXh c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_regRemov_FFF2_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhE?/ JXh4 JslackXhY0>   ipb_rst_reg/Cc_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsuv@}Av5A`Xj<c@`X@AY=А==c&@=>@ -r?'@R^?K7!@_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)^  ipb_rst_reg/QProp_EFF_SLICEM_C_Q JFDREXhzfV>] ctrl_regs_inst/lopt Jnet (fo=1953, routed)XhV~@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I1 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_H5LUT_SLICEL_I1_O JLUT3Xhzfˡ> VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in Jnet (fo=10, routed)XhS? c_i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzre CLKFBIN Jnet (fo=3804, routed)Xhc@X3Y4 (CLOCK_ROOT)C  ipb_rst_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in Jnet (fo=3804, routed)Xh`X@X3Y4 (CLOCK_ROOT) a]i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhY _[i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_regRecov_DFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhv5A; J arrival timeXh$ / JXh4 JslackXhc&@  ipb_rst_reg/Cd`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsuv@}Av5A`Xj<c@`X@AY=А==c&@=>@ -r?'@R^?K7!@_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)^  ipb_rst_reg/QProp_EFF_SLICEM_C_Q JFDREXhzfV>] ctrl_regs_inst/lopt Jnet (fo=1953, routed)XhV~@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I1 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_H5LUT_SLICEL_I1_O JLUT3Xhzfˡ> VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in Jnet (fo=10, routed)XhS? d`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzre CLKFBIN Jnet (fo=3804, routed)Xhc@X3Y4 (CLOCK_ROOT)C  ipb_rst_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in Jnet (fo=3804, routed)Xh`X@X3Y4 (CLOCK_ROOT) b^i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhY `\i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_regRecov_AFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhv5A; J arrival timeXh$ / JXh4 JslackXhc&@  ipb_rst_reg/Cd`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsuv@}Av5A`Xj<c@`X@AY=А==c&@=>@ -r?'@R^?K7!@_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)^  ipb_rst_reg/QProp_EFF_SLICEM_C_Q JFDREXhzfV>] ctrl_regs_inst/lopt Jnet (fo=1953, routed)XhV~@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I1 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_H5LUT_SLICEL_I1_O JLUT3Xhzfˡ> VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in Jnet (fo=10, routed)XhS? d`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzre CLKFBIN Jnet (fo=3804, routed)Xhc@X3Y4 (CLOCK_ROOT)C  ipb_rst_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in Jnet (fo=3804, routed)Xh`X@X3Y4 (CLOCK_ROOT) b^i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhY `\i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_regRecov_BFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhv5A; J arrival timeXh$ / JXh4 JslackXhc&@  ipb_rst_reg/Cd`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsuv@}Av5A`Xj<c@`X@AY=А==c&@=>@ -r?'@R^?K7!@_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)^  ipb_rst_reg/QProp_EFF_SLICEM_C_Q JFDREXhzfV>] ctrl_regs_inst/lopt Jnet (fo=1953, routed)XhV~@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I1 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_H5LUT_SLICEL_I1_O JLUT3Xhzfˡ> VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in Jnet (fo=10, routed)XhS? d`i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzre CLKFBIN Jnet (fo=3804, routed)Xhc@X3Y4 (CLOCK_ROOT)C  ipb_rst_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in Jnet (fo=3804, routed)Xh`X@X3Y4 (CLOCK_ROOT) b^i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhY `\i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_regRecov_CFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhv5A; J arrival timeXh$ / JXh4 JslackXhc&@  ipb_rst_reg/Cb^i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu$@}AD5AXDc@X@AY=А==uI'@=>X@ -r?'@R^?!@_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)^  ipb_rst_reg/QProp_EFF_SLICEM_C_Q JFDREXhzfV>] ctrl_regs_inst/lopt Jnet (fo=1953, routed)XhV~@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I1 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_H5LUT_SLICEL_I1_O JLUT3Xhzfˡ> VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in Jnet (fo=10, routed)XhshQ? b^i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzre CLKFBIN Jnet (fo=3804, routed)Xhc@X3Y4 (CLOCK_ROOT)C  ipb_rst_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr VRi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/clk_in Jnet (fo=3804, routed)XhX@X3Y4 (CLOCK_ROOT) `\i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhY ^Zi_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_regRecov_EFF_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhD5A; J arrival timeXh / JXh4 JslackXhuI'@  ipb_rst_reg/C\Xi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsuL7@}A5AXuc@X@AY=А==_0@=>~j@ -r?'@R^?Q @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)^  ipb_rst_reg/QProp_EFF_SLICEM_C_Q JFDREXhzfV>] ctrl_regs_inst/lopt Jnet (fo=1953, routed)XhV~@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I1 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_H5LUT_SLICEL_I1_O JLUT3Xhzfˡ> PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh)? \Xi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzre CLKFBIN Jnet (fo=3804, routed)Xhc@X3Y4 (CLOCK_ROOT)C  ipb_rst_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3804, routed)XhX@X3Y4 (CLOCK_ROOT) ZVi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/C JFDPEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhY XTi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_regRecov_EFF_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh5A; J arrival timeXh / JXh4 JslackXh_0@  ipb_rst_reg/C]Yi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu@}A5AXuc@X@AY=А==6@=>/@ -r?'@R^?Q @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)^  ipb_rst_reg/QProp_EFF_SLICEM_C_Q JFDREXhzfV>] ctrl_regs_inst/lopt Jnet (fo=1953, routed)XhV~@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I1 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_H5LUT_SLICEL_I1_O JLUT3Xhzfˡ> PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh ? ]Yi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzre CLKFBIN Jnet (fo=3804, routed)Xhc@X3Y4 (CLOCK_ROOT)C  ipb_rst_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3804, routed)XhX@X3Y4 (CLOCK_ROOT) [Wi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/C JFDPEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhY YUi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_regRecov_HFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh5A; J arrival timeXhm/ JXh4 JslackXh6@  ipb_rst_reg/C^Zi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu@}A5AXuc@X@AY=А==6@=>/@ -r?'@R^?Q @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)^  ipb_rst_reg/QProp_EFF_SLICEM_C_Q JFDREXhzfV>] ctrl_regs_inst/lopt Jnet (fo=1953, routed)XhV~@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I1 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_H5LUT_SLICEL_I1_O JLUT3Xhzfˡ> PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh ? ^Zi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzre CLKFBIN Jnet (fo=3804, routed)Xhc@X3Y4 (CLOCK_ROOT)C  ipb_rst_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3804, routed)XhX@X3Y4 (CLOCK_ROOT) \Xi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/C JFDPEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhY ZVi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_regRecov_EFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh5A; J arrival timeXhm/ JXh4 JslackXh6@  ipb_rst_reg/C^Zi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu@}A5AXuc@X@AY=А==6@=>/@ -r?'@R^?Q @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)^  ipb_rst_reg/QProp_EFF_SLICEM_C_Q JFDREXhzfV>] ctrl_regs_inst/lopt Jnet (fo=1953, routed)XhV~@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I1 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_H5LUT_SLICEL_I1_O JLUT3Xhzfˡ> PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh ? ^Zi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzre CLKFBIN Jnet (fo=3804, routed)Xhc@X3Y4 (CLOCK_ROOT)C  ipb_rst_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3804, routed)XhX@X3Y4 (CLOCK_ROOT) \Xi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/C JFDPEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhY ZVi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_regRecov_FFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh5A; J arrival timeXhm/ JXh4 JslackXh6@  ipb_rst_reg/C^Zi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE"$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT*X3Y42$RCLK_CLEL_R_L_X56Y329/CLK_VDISTR_BOT:X3Y4BJZ(LUT3=1)j)clk125 rise@8.000ns - clk125 rise@0.000nsu@}A5AXuc@X@AY=А==6@=>/@ -r?'@R^?Q @_(rising edge-triggered cell FDRE clocked by clk125 {rise@0.000ns fall@4.000ns period=8.000ns})](recovery check against rising-edge clock clk125 {rise@0.000ns fall@4.000ns period=8.000ns})Slow**async_default**clk125clk125((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR)^  ipb_rst_reg/QProp_EFF_SLICEM_C_Q JFDREXhzfV>] ctrl_regs_inst/lopt Jnet (fo=1953, routed)XhV~@i ;7ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/I1 JXhzf :6ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1/OProp_H5LUT_SLICEL_I1_O JLUT3Xhzfˡ> PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in Jnet (fo=10, routed)Xh ? ^Zi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE JFDPEXhzfJ J(clock clk125 rise edge)XhzrM i_clk125_bufg/O JBUFGCEXhzre CLKFBIN Jnet (fo=3804, routed)Xhc@X3Y4 (CLOCK_ROOT)C  ipb_rst_reg/C JFDREXhzrJ J(clock clk125 rise edge)XhzrAM i_clk125_bufg/O JBUFGCEXhzr PLi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/clk_in Jnet (fo=3804, routed)XhX@X3Y4 (CLOCK_ROOT) \Xi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/C JFDPEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhY ZVi_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_regRecov_GFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh5A; J arrival timeXhm/ JXh4 JslackXh6@ **async_default** fabric_clk fabric_clk!)Ë>(@1Ë>8@9AË>(@IË>8@eAhq}Y@ >Yd rise - rise rise - rise  73SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C84SFP_GEN[27].ngCCM_gbt/recv_RX_to_TX_data_dly_reg/CLR"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu9>}񲿭e=??@ >D=Q>>J?sh>/}?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=e SFP_GEN[27].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhQ>j 84SFP_GEN[27].ngCCM_gbt/recv_RX_to_TX_data_dly_reg/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)i 73SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[27].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)h 62SFP_GEN[27].ngCCM_gbt/recv_RX_to_TX_data_dly_reg/C JFDCEXhzr> Jclock pessimismXh 40SFP_GEN[27].ngCCM_gbt/recv_RX_to_TX_data_dly_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh@ > 62SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]/PRE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsuGa>} 2̿.R=-?2?> D= 0>>n?sh>?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 62SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=d SFP_GEN[3].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xh 0>o =9SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh-?X2Y4 (CLOCK_ROOT)h 62SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[3].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh2?X2Y4 (CLOCK_ROOT)m ;7SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]/C JFDPEXhzr> Jclock pessimismXh  95SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]Remov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh ; J arrival timeXhV?/ JXh4 JslackXh>u 73SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[39].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][4]/PRE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsurh>}¿xٿns=X?x?G#>n@D=K7>>?sh>?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=e SFP_GEN[39].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhK7>o =9SFP_GEN[39].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][4]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)XhX?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]i 73SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[39].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhx?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[39].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][4]/C JFDPEXhzr> Jclock pessimismXhn@ 95SFP_GEN[39].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][4]Remov_EFF_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXh¿; J arrival timeXhhf?/ JXh4 JslackXhG#> 73SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C>:SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]/PRE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsuأp>}3#ɿ =?#?C$>7~D=|?>>S~?sh>?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=e SFP_GEN[12].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xh|?>p >:SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)i 73SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[12].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh#?X2Y4 (CLOCK_ROOT)n <8SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]/C JFDPEXhzr> Jclock pessimismXh7~ :6SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][11]Remov_AFF_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXh3; J arrival timeXh/?/ JXh4 JslackXhC$> 62SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]/PRE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsui;_>}ÿڿvL=̼??&>v;D=|.>>V?sh>E?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=d SFP_GEN[9].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xh|.>n <8SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh̼?X2Y4 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[9].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)l :6SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]/C JFDPEXhzr> Jclock pessimismXhv; 84SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]Remov_EFF_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhÿ; J arrival timeXh:?/ JXh4 JslackXh&> 62SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][2]/PRE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsui;_>}ÿڿvL=̼??&>v;D=|.>>V?sh>E?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=d SFP_GEN[9].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xh|.>n <8SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][2]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh̼?X2Y4 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[9].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)l :6SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][2]/C JFDPEXhzr> Jclock pessimismXhv; 84SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][2]Remov_EFF2_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhÿ; J arrival timeXh:?/ JXh4 JslackXh&> 62SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][3]/PRE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsui;_>}ÿڿvL=̼??&>v;D=|.>>V?sh>E?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=d SFP_GEN[9].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xh|.>n <8SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][3]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh̼?X2Y4 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[9].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)l :6SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][3]/C JFDPEXhzr> Jclock pessimismXhv; 84SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][3]Remov_FFF_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhÿ; J arrival timeXh:?/ JXh4 JslackXh&> 73SFP_GEN[35].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[35].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]/PRE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu(\>}nݱǿ].=ƫ??r+>4D= +>>dx?sh>t?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[35].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=e SFP_GEN[35].ngCCM_gbt/out[0] Jnet (fo=377, routed)Xh +>o =9SFP_GEN[35].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[35].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xhƫ?X2Y4 (CLOCK_ROOT)i 73SFP_GEN[35].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[35].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)m ;7SFP_GEN[35].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]/C JFDPEXhzr> Jclock pessimismXh4 95SFP_GEN[35].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_scl][2]Remov_AFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhnݱ; J arrival timeXhK?/ JXh4 JslackXhr+>u 73SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][9]/PRE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu>}_ɿοX->t??&1>zj<D=>>G?sh>?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=e SFP_GEN[36].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xh>o =9SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][9]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xht?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]i 73SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[36].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][9]/C JFDPEXhzr> Jclock pessimismXhzj< 95SFP_GEN[36].ngCCM_gbt/ngccmPinsOutReg_reg[bkt_sda][9]Remov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh_ɿ; J arrival timeXh=?/ JXh4 JslackXh&1> 73SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C3/SFP_GEN[27].ngCCM_gbt/clr_fetch_RX_data_reg/CLR"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj1fabric_clk rise@0.000ns - fabric_clk rise@0.000nsu> >}1|S#=?S?(3>D=|>>J?sh>}?e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})b(removal check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Fast**async_default** fabric_clk fabric_clk(DCD - SCD - CPR) 73SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=e SFP_GEN[27].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xh|>e 3/SFP_GEN[27].ngCCM_gbt/clr_fetch_RX_data_reg/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 2.SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh?X2Y4 (CLOCK_ROOT)i 73SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr $ SFP_GEN[27].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhS?X2Y4 (CLOCK_ROOT)c 1-SFP_GEN[27].ngCCM_gbt/clr_fetch_RX_data_reg/C JFDCEXhzr> Jclock pessimismXh| /+SFP_GEN[27].ngCCM_gbt/clr_fetch_RX_data_regRemov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh1|; J arrival timeXhH?/ JXh4 JslackXh(3>: 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][19]/CLR"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsu~|A}AAZ.r+n@Z@A~>А={>A=V>$yA~j|?l/@lg?A @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) N%Z@-lg?5 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[1].ngCCM_gbt/out[0] Jnet (fo=375, routed)Xh$yAD JXhSLR Crossing[0->1]o =9SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][19]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh+n@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[1].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhZ@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][19]/C JFDCEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhN@ Jclock uncertaintyXh~ 95SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][19]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhA; J arrival timeXh$ۛ/ JXh4 JslackXhA: 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/PRE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsujA}A}ATEj +n@TE@A~>А={>A=V>gA~j|?l/@lg?1 @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %TE@-lg?5 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[1].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhgAD JXhSLR Crossing[0->1]o =9SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh+n@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[1].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhTE@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/C JFDPEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh @ Jclock uncertaintyXh~ 95SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]Recov_EFF_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh}A; J arrival timeXhҒ/ JXh4 JslackXhA: 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/PRE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsucA}A;pAX9D[9+n@X9D@A~>А={>>A=V>aA~j|?l/@lg?5^ @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %X9D@-lg?5 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[1].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhaAD JXhSLR Crossing[0->1]o =9SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh+n@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[1].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhX9D@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/C JFDPEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh @ Jclock uncertaintyXh~ 95SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]Recov_EFF_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh;pA; J arrival timeXhЏ/ JXh4 JslackXh>A7 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/CLR"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsucA}A;pAX9D[9+n@X9D@A~>А={>>A=V>aA~j|?l/@lg?5^ @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %X9D@-lg?5 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[1].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhaAD JXhSLR Crossing[0->1]n <8SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh+n@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[1].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhX9D@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]l :6SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/C JFDCEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh @ Jclock uncertaintyXh~ 84SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]Recov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh;pA; J arrival timeXhЏ/ JXh4 JslackXh>A6 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]/CLR"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsucA}A;pAX9D[9+n@X9D@A~>А={>>A=V>aA~j|?l/@lg?5^ @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %X9D@-lg?5 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[1].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhaAD JXhSLR Crossing[0->1]n <8SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh+n@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[1].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhX9D@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]l :6SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]/C JFDCEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh @ Jclock uncertaintyXh~ 84SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][3]Recov_FFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh;pA; J arrival timeXhЏ/ JXh4 JslackXh>A7 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]/CLR"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsucA}A;pAX9D[9+n@X9D@A~>А={>>A=V>aA~j|?l/@lg?5^ @e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %X9D@-lg?5 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[1].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhaAD JXhSLR Crossing[0->1]n <8SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh+n@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[1].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)XhX9D@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]l :6SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]/C JFDCEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh @ Jclock uncertaintyXh~ 84SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][7]Recov_FFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh;pA; J arrival timeXhЏ/ JXh4 JslackXh>A: 62SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/PRE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsuo]A}AA;SRu@;@A~>А={>A=V>ZA~j|?6@lg?@e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %;@-lg?5 62SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfV>d SFP_GEN[0].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhZAD JXhSLR Crossing[0->1]o =9SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)XhRu@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[0].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh;@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]/C JFDPEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh@ Jclock uncertaintyXh~ 95SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][17]Recov_EFF_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhA; J arrival timeXhE/ JXh4 JslackXhA6 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]/CLR"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsu\^A}AA(<z4+n@(<@A~>А={>A=V>V\A~j|?l/@lg?M@e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) b]%(<@-lg?5 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfV>d SFP_GEN[1].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhV\AD JXhSLR Crossing[0->1]n <8SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)Xh+n@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[1].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xh(<@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]l :6SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]/C JFDCEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhb]@ Jclock uncertaintyXh~ 84SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][8]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhA; J arrival timeXh/ JXh4 JslackXhA: 62SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C=9SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/PRE"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsu9\A}AڛAj<[PRu@j<@A~>А={> A=V>zZA~j|?6@lg?\@e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %j<@-lg?5 62SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfV>d SFP_GEN[0].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhzZAD JXhSLR Crossing[0->1]o =9SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/PRE JFDPEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)XhRu@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[0].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhj<@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]m ;7SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]/C JFDPEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh@ Jclock uncertaintyXh~ 95SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][15]Recov_EFF_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXhڛA; J arrival timeXh/ JXh4 JslackXh A7 62SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C<8SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/CLR"#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT*X2Y42#RCLK_CLE_M_L_X47Y329/CLK_VDISTR_BOT:X2Y4BJZj2fabric_clk rise@24.952ns - fabric_clk rise@0.000nsu9\A}AڛAj<[PRu@j<@A~>А={> A=V>zZA~j|?6@lg?\@e(rising edge-triggered cell FDPE clocked by fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})c(recovery check against rising-edge clock fabric_clk {rise@0.000ns fall@12.476ns period=24.952ns})Slow**async_default** fabric_clk fabric_clk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) %j<@-lg?5 62SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfV>d SFP_GEN[0].ngCCM_gbt/out[0] Jnet (fo=375, routed)XhzZAD JXhSLR Crossing[0->1]n <8SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/CLR JFDCEXhzfN J(clock fabric_clk rise edge)XhzrO fabric_clk_bufg/O JBUFGCEXhzr 1-SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/fabric_clk Jnet (fo=103803, routed)XhRu@X2Y4 (CLOCK_ROOT)h 62SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/sync_m_reg[3]/C JFDPEXhzrN J(clock fabric_clk rise edge)XhzrAO fabric_clk_bufg/O JBUFGCEXhzr #SFP_GEN[0].ngCCM_gbt/fabric_clk Jnet (fo=103803, routed)Xhj<@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1]l :6SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]/C JFDCEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXh@ Jclock uncertaintyXh~ 84SFP_GEN[0].ngCCM_gbt/ngccmPinsOutReg_reg[prbs_rx][2]Recov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhڛA; J arrival timeXh/ JXh4 JslackXh A> **async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]!)y@1y @9Ay@Iy @ebWm@hq}[>d rise - rise rise - rise  62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu> >}iZĿp=?Z?[>ݢ,D=|>(?<?;/?.?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|>c 1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT)h 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[19]/C JFDCEXhzr> Jclock pessimismXhݢ,z -)SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[19]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXhI?/ JXh4 JslackXh[>462SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu> >}iZĿp=?Z?[>ݢ,D=|>(?<?;/?.?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|>c 1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT)h 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr> Jclock pessimismXhݢ,{ -)SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[23]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXhI?/ JXh4 JslackXh[>462SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu> >}iZĿp=?Z?[>ݢ,D=|>(?<?;/?.?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|>c 1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT)h 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[26]/C JFDCEXhzr> Jclock pessimismXhݢ,z -)SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[26]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXhI?/ JXh4 JslackXh[>462SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu> >}iZĿp=?Z?[>ݢ,D=|>(?<?;/?.?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|>c 1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT)h 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzr> Jclock pessimismXhݢ,{ -)SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[27]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXhI?/ JXh4 JslackXh[>462SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu> >}iZĿp=?Z?[>ݢ,D=|>(?<?;/?.?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|>c 1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT)h 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXhݢ,z -)SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[28]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXhI?/ JXh4 JslackXh[>462SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu> >}iZĿp=?Z?[>ݢ,D=|>(?<?;/?.?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|>c 1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT)h 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[31]/C JFDCEXhzr> Jclock pessimismXhݢ,{ -)SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[31]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXhI?/ JXh4 JslackXh[>462SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu>}0Ŀ=?0?s^>b,D=I >(?<?;/?/?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhI >c 1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT)h 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[29]/C JFDCEXhzr> Jclock pessimismXhb,z -)SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[29]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhs^>462SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu>}0Ŀ=?0?s^>b,D=I >(?<?;/?/?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhI >c 1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT)h 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[30]/C JFDCEXhzr> Jclock pessimismXhb,{ -)SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[30]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhs^>462SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu>}0Ŀ=?0?s^>b,D=I >(?<?;/?/?w(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[0].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhI >c 1-SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT)h 62SFP_GEN[0].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[0].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X3Y0 (CLOCK_ROOT)a /+SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[81]/C JFDCEXhzr> Jclock pessimismXhb,z -)SFP_GEN[0].ngCCM_gbt/RX_Word_rx40_reg[81]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhs^>4d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZjYgtwiz_userclk_rx_srcclk_out[0] rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu奛>}c(Ŀn8=??j>>,D=o>(?ף?;/?}.?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})t(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0](DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xho> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhff?X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh>, g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhc(; J arrival timeXhj?/ JXh4 JslackXhj>Rg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT2=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuzt@}A|8AD)ף@D@A=А=bWm@0>㥛>%a@H?p@??w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1/I0 JXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1/OProp_C6LUT_SLICEL_I0_O JLUT2Xhzf(> WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 Jnet (fo=2, routed)Xh'1? TPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh"+@X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh0>@ Jclock uncertaintyXh PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh|8A; J arrival timeXhG/ JXh4 JslackXhbWm@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT2=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsuzt@}A|8AD)ף@D@A=А=bWm@0>㥛>%a@H?p@??w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh>@ b^g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1/I0 JXhzr a]g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1/OProp_C6LUT_SLICEL_I0_O JLUT2Xhzf(> WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 Jnet (fo=2, routed)Xh'1? YUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh"+@X3Y0 (CLOCK_ROOT) WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh0>@ Jclock uncertaintyXh UQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh|8A; J arrival timeXhG/ JXh4 JslackXhbWm@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu.m@}A 8AD+ף@D@A=А=Os@;>Q>V@H?p@?~?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhrh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/OProp_F6LUT_SLICEL_I0_O JLUT3XhzfMb> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh*@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/C JFDCEXhzr> Jclock pessimismXh;>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 8A; J arrival timeXh|/ JXh4 JslackXhOs@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu.m@}A 8AD+ף@D@A=А=Os@;>Q>V@H?p@?~?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhrh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/OProp_F6LUT_SLICEL_I0_O JLUT3XhzfMb> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh*@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/C JFDCEXhzr> Jclock pessimismXh;>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 8A; J arrival timeXh|/ JXh4 JslackXhOs@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu.m@}A 8AD+ף@D@A=А=Os@;>Q>V@H?p@?~?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhrh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/OProp_F6LUT_SLICEL_I0_O JLUT3XhzfMb> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh*@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/C JFDCEXhzr> Jclock pessimismXh;>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 8A; J arrival timeXh|/ JXh4 JslackXhOs@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu.m@}A 8AD+ף@D@A=А=Os@;>Q>V@H?p@?~?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhrh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/OProp_F6LUT_SLICEL_I0_O JLUT3XhzfMb> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh*@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/C JFDCEXhzr> Jclock pessimismXh;>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]Recov_AFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 8A; J arrival timeXh|/ JXh4 JslackXhOs@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu.m@}A 8AD+ף@D@A=А=Os@;>Q>V@H?p@?~?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhrh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/OProp_F6LUT_SLICEL_I0_O JLUT3XhzfMb> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh*@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/C JFDCEXhzr> Jclock pessimismXh;>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 8A; J arrival timeXh|/ JXh4 JslackXhOs@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu.m@}A 8AD+ף@D@A=А=Os@;>Q>V@H?p@?~?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhrh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/OProp_F6LUT_SLICEL_I0_O JLUT3XhzfMb> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh*@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C JFDCEXhzr> Jclock pessimismXh;>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 8A; J arrival timeXh|/ JXh4 JslackXhOs@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsue;g@}AC8AZDY*ף@ZD@A=А=Uz@5>Q>&1P@H?p@? ?w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhrh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/OProp_F6LUT_SLICEL_I0_O JLUT3XhzfMb> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] Jnet (fo=674, routed)XhH*@X3Y0 (CLOCK_ROOT)y GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C JFDCEXhzr> Jclock pessimismXh5>@ Jclock uncertaintyXh EAg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhC8A; J arrival timeXhA/ JXh4 JslackXhUz@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR"#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT*X3Y02#RCLK_CLEL_R_L_X61Y89/CLK_VDISTR_BOT:X3Y0BJZ(LUT3=1)jYgtwiz_userclk_rx_srcclk_out[0] rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0] rise@0.000nsu+g@}A|8AD)ף@D@A=А=Az@0>Q> P@H?p@??w(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})u(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0] {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**gtwiz_userclk_rx_srcclk_out[0]gtwiz_userclk_rx_srcclk_out[0]#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhrh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2/OProp_F6LUT_SLICEL_I0_O JLUT3XhzfMb> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR JFDCEXhzfb J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhHb@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr b J0(clock gtwiz_userclk_rx_srcclk_out[0] rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[0] Jnet (fo=674, routed)Xh"+@X3Y0 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/C JFDCEXhzr> Jclock pessimismXh0>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh|8A; J arrival timeXhX9/ JXh4 JslackXhAz@ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1!)y@1y @9Ay@Iy @eUL@hq}U=d rise - rise rise - rise  73SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuM>}y`=c??U=D=>̌>>w>d;?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) 73SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[10].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh>d 2.SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`E?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xho?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[80]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[80]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhy; J arrival timeXh?/ JXh4 JslackXhU=473SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuM>}y`=c??U=D=>̌>>w>d;?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) 73SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[10].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh>d 2.SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`E?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xho?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[81]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[81]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhy; J arrival timeXh?/ JXh4 JslackXhU=473SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuM>}y`=c??U=D=>̌>>w>d;?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) 73SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[10].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh>d 2.SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`E?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xho?X4Y3 (CLOCK_ROOT)b 0,SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhy; J arrival timeXh?/ JXh4 JslackXhU=473SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuM>}y`=c??U=D=>̌>>w>d;?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) 73SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[10].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh>` .*SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`E?X4Y3 (CLOCK_ROOT)i 73SFP_GEN[10].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[10].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xho?X4Y3 (CLOCK_ROOT)^ ,(SFP_GEN[10].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhw *&SFP_GEN[10].ngCCM_gbt/pwr_good_pre_regRemov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhy; J arrival timeXh?/ JXh4 JslackXhU=4eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsurh>}w|@5=Te?@5?*~ >F9H=E6>̌>G?w>M"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhE6> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-r?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXhF g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhw|; J arrival timeXh?/ JXh4 JslackXh*~ >Reag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsurh>}w|@5=Te?@5?*~ >F9H=E6>̌>G?w>M"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhE6> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-r?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXhF g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhw|; J arrival timeXh?/ JXh4 JslackXh*~ >Reag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsurh>}w|@5=Te?@5?*~ >F9H=E6>̌>G?w>M"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhE6> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-r?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXhF g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhw|; J arrival timeXh?/ JXh4 JslackXh*~ >Reag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsurh>}w|@5=Te?@5?*~ >F9H=E6>̌>G?w>M"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhE6> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-r?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXhF g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhw|; J arrival timeXh?/ JXh4 JslackXh*~ >Reag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuxi>}w|@5=Te?@5?M >F9H=K7>̌>G?w>M"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhK7> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-r?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXhF g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhw|; J arrival timeXh ?/ JXh4 JslackXhM >Reag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuxi>}w|@5=Te?@5?M >F9H=K7>̌>G?w>M"?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1(DCD - SCD - CPR) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhK7> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhG?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh-r?X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXhF g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhw|; J arrival timeXh ?/ JXh4 JslackXhM >Rg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CUQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsutC@}AD*Al|V$1@l@A=А=UL@X>>t+@!?Z? ?\?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? fbg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__9/I0 JXhzr eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__9/OProp_C6LUT_SLICEL_I0_O JLUT2Xhzf֣p> XTg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhF? UQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhl?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhD*A; J arrival timeXhq=/ JXh4 JslackXhUL@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CZVg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsutC@}AD*Al|V$1@l@A=А=UL@X>>t+@!?Z? ?\?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? fbg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__9/I0 JXhzr eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__9/OProp_C6LUT_SLICEL_I0_O JLUT2Xhzf֣p> XTg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhF? ZVg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhl?X4Y3 (CLOCK_ROOT) XTg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh VRg_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhD*A; J arrival timeXhq=/ JXh4 JslackXhUL@ $g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu@@}A?,AiL$1@i@A=А=e@j>8>Q(@!?Z? ?ٮ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfFs> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh#9?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh(1?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C JFDCEXhzr> Jclock pessimismXhj>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh?,A; J arrival timeXhĸ/ JXh4 JslackXhe@ %g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu@@}A?,AiL$1@i@A=А=e@j>8>Q(@!?Z? ?ٮ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfFs> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh#9?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh(1?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C JFDCEXhzr> Jclock pessimismXhj>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh?,A; J arrival timeXhĸ/ JXh4 JslackXhe@ $g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsu@@}A?,AiL$1@i@A=А=e@j>8>Q(@!?Z? ?ٮ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfFs> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh#9?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh(1?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/C JFDCEXhzr> Jclock pessimismXhj>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh?,A; J arrival timeXhĸ/ JXh4 JslackXhe@ $g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsub@@}A# ,ApǜN$1@p@A=А=@Cj>8><'@!?Z? ??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfFs> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhc8?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/C JFDCEXhzr> Jclock pessimismXhCj>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh# ,A; J arrival timeXhC/ JXh4 JslackXh@ %g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsub@@}A# ,ApǜN$1@p@A=А=@Cj>8><'@!?Z? ??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfFs> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhc8?z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr> Jclock pessimismXhCj>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]Recov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh# ,A; J arrival timeXhC/ JXh4 JslackXh@ 0g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CKGg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR""RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0*X4Y32"RCLK_DSP_L_X75Y269/CLK_VDISTR_BOT0:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_1 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_1 rise@0.000nsuV>@}A+A/zW$1@/@A=А=4#@j>8>$&@!?Z? ?p?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfFs> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh&1?} KGg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT){ IEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C JFDCEXhzr> Jclock pessimismXhj>@ Jclock uncertaintyXh GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh4#@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@8>?5@!?Z? ?ٮ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfFs> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhrh?r @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh(1?X4Y3 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C JFDCEXhzr> Jclock pessimismXhj>@ Jclock uncertaintyXh <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh?,A; J arrival timeXhE/ JXh4 JslackXh9t@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@8>?5@!?Z? ?ٮ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_1 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_1 gtwiz_userclk_rx_srcclk_out[0]_1#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfFs> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhrh?r @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_1 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[10] Jnet (fo=674, routed)Xh(1?X4Y3 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C JFDCEXhzr> Jclock pessimismXhj>@ Jclock uncertaintyXh <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh?,A; J arrival timeXhE/ JXh4 JslackXh9t@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10!)y@1y @9Ay@Iy @e@hq}@ >d rise - rise rise - rise  RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu0^:>}Tvأ(=~j?أ?@ >09H='1>̌>T?Ġ>&?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh'1> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhIL?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh? w?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]/C JFDCEXhzr> Jclock pessimismXh0 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[81]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhTv; J arrival timeXhC?/ JXh4 JslackXh@ >RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu0^:>}Tvأ(=~j?أ?@ >09H='1>̌>T?Ġ>&?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh'1> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhIL?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh? w?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]/C JFDCEXhzr> Jclock pessimismXh0 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[83]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhTv; J arrival timeXhC?/ JXh4 JslackXh@ >RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu0^:>}Tvأ(=~j?أ?@ >09H='1>̌>T?Ġ>&?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh'1> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhIL?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh? w?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]/C JFDCEXhzr> Jclock pessimismXh0 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[81]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhTv; J arrival timeXhC?/ JXh4 JslackXh@ >RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[83]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu0^:>}Tvأ(=~j?أ?@ >09H='1>̌>T?Ġ>&?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh'1> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[83]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhIL?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh? w?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[83]/C JFDCEXhzr> Jclock pessimismXh0 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[83]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhTv; J arrival timeXhC?/ JXh4 JslackXh@ >RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[41]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsup=>}va吿k11=~j?a? >09H=C >̌>T?Ġ>+'?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhC > gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[41]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhIL?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhPw?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[41]/C JFDCEXhzr> Jclock pessimismXh0 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[41]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhv; J arrival timeXh?/ JXh4 JslackXh >RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[49]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsup=>}va吿k11=~j?a? >09H=C >̌>T?Ġ>+'?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhC > gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[49]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhIL?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhPw?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[49]/C JFDCEXhzr> Jclock pessimismXh0 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[49]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhv; J arrival timeXh?/ JXh4 JslackXh >RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[56]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsup=>}va吿k11=~j?a? >09H=C >̌>T?Ġ>+'?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhC > gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[56]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhIL?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhPw?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[56]/C JFDCEXhzr> Jclock pessimismXh0 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[56]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhv; J arrival timeXh?/ JXh4 JslackXh >RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[57]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsup=>}va吿k11=~j?a? >09H=C >̌>T?Ġ>+'?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhC > gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[57]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhIL?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhPw?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[57]/C JFDCEXhzr> Jclock pessimismXh0 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg0_reg[57]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhv; J arrival timeXh?/ JXh4 JslackXh >RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[41]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsup=>}va吿k11=~j?a? >09H=C >̌>T?Ġ>+'?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhC > gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[41]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhIL?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhPw?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[41]/C JFDCEXhzr> Jclock pessimismXh0 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[41]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhv; J arrival timeXh?/ JXh4 JslackXh >RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[49]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsup=>}va吿k11=~j?a? >09H=C >̌>T?Ġ>+'?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhC > gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[49]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhIL?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhPw?X4Y3 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[49]/C JFDCEXhzr> Jclock pessimismXh0 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/reg1_reg[49]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhv; J arrival timeXh?/ JXh4 JslackXh >g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuOb(@}A1*A= de;/@= @A=А=@8IZ>k>@I "?ף?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhz? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh"?X4Y3 (CLOCK_ROOT)y GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/C JFDCEXhzr> Jclock pessimismXh8IZ>@ Jclock uncertaintyXh EAg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1*A; J arrival timeXhΫ/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu)@}Av*A%e;/@%@A=А=<@Y>xi>o@I "?ף?n?T?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ? eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__7/I0 JXhzr d`g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__7/OProp_C6LUT_SLICEL_I0_O JLUT2XhzfX9= WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh#? TPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhv*A; J arrival timeXhr/ JXh4 JslackXh<@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu)@}Av*A%e;/@%@A=А=<@Y>xi>o@I "?ף?n?T?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ? eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__7/I0 JXhzr d`g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__7/OProp_C6LUT_SLICEL_I0_O JLUT2XhzfX9= WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh#? YUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT) WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh UQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhv*A; J arrival timeXhr/ JXh4 JslackXh<@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu1$@}A1*A= de;/@= @A=А=@8IZ>k>O@I "?ף?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhz? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh"?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/C JFDCEXhzr> Jclock pessimismXh8IZ>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1*A; J arrival timeXhˡ/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuE@}AA*AK]e;/@K@A=А=qí@>Z>k>P@I "?ף?n?n?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhz? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/C JFDCEXhzr> Jclock pessimismXh>Z>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhA*A; J arrival timeXh/ JXh4 JslackXhqí@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuE@}AA*AK]e;/@K@A=А=qí@>Z>k>P@I "?ף?n?n?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhz? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/C JFDCEXhzr> Jclock pessimismXh>Z>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhA*A; J arrival timeXh/ JXh4 JslackXhqí@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuE@}AA*AK]e;/@K@A=А=qí@>Z>k>P@I "?ף?n?n?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhz? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/C JFDCEXhzr> Jclock pessimismXh>Z>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhA*A; J arrival timeXh/ JXh4 JslackXhqí@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsuE@}AA*AK]e;/@K@A=А=qí@>Z>k>P@I "?ף?n?n?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhz? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C JFDCEXhzr> Jclock pessimismXh>Z>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhA*A; J arrival timeXh/ JXh4 JslackXhqí@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu@}A=*Ad;Sߒe;/@d;@A=А=@\AZ>k>@I "?ף?n?M?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhz? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/C JFDCEXhzr> Jclock pessimismXh\AZ>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh=*A; J arrival timeXh,/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR"$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT*X4Y32$RCLK_CLEL_R_L_X76Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_10 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_10 rise@0.000nsu@}A=*Ad;Sߒe;/@d;@A=А=@\AZ>k>@I "?ף?n?M?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_10 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_10!gtwiz_userclk_rx_srcclk_out[0]_10#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEM_C_Q JFDCEXhzr)\> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhz? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_10 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[8] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/C JFDCEXhzr> Jclock pessimismXh\AZ>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh=*A; J arrival timeXh,/ JXh4 JslackXh@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11!)y@1y @9Ay@Iy @e"f@hq}>d rise - rise rise - rise  62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C0,SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsulg>}|zO =lg?O?>GD=E6>I>o?A>A ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhE6>b 0,SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhNbp?X4Y3 (CLOCK_ROOT)` .*SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXhGy ,(SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[0]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh|z; J arrival timeXhأ?/ JXh4 JslackXh>462SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C0,SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsulg>}|zO =lg?O?>GD=E6>I>o?A>A ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhE6>b 0,SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhNbp?X4Y3 (CLOCK_ROOT)` .*SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXhGz ,(SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[2]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh|z; J arrival timeXhأ?/ JXh4 JslackXh>4 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsulg>}|zO =lg?O?>GD=E6>I>o?A>A ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhE6>c 1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhNbp?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzr> Jclock pessimismXhGz -)SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[40]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh|z; J arrival timeXhأ?/ JXh4 JslackXh>4 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsulg>}|zO =lg?O?>GD=E6>I>o?A>A ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhE6>c 1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhNbp?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[42]/C JFDCEXhzr> Jclock pessimismXhG{ -)SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[42]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh|z; J arrival timeXhأ?/ JXh4 JslackXh>4 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu^>}}َvܩ=lg?َ?g9>N(D=Mb>I>o?A>S#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhMb>c 1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhts?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[68]/C JFDCEXhzr> Jclock pessimismXhN(z -)SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[68]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXh$?/ JXh4 JslackXhg9>4 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu^>}}َvܩ=lg?َ?g9>N(D=Mb>I>o?A>S#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhMb>c 1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhts?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[70]/C JFDCEXhzr> Jclock pessimismXhN({ -)SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[70]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}; J arrival timeXh$?/ JXh4 JslackXhg9>4 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[48]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsǔ>}~d; =lg?d;?t<>#D=rh>I>o?A>$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhrh>c 1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[48]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhX9t?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[48]/C JFDCEXhzr> Jclock pessimismXh#z -)SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[48]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh~; J arrival timeXhy?/ JXh4 JslackXht<>4 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsǔ>}~d; =lg?d;?t<>#D=rh>I>o?A>$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhrh>c 1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhX9t?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]/C JFDCEXhzr> Jclock pessimismXh#{ -)SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh~; J arrival timeXhy?/ JXh4 JslackXht<>4 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsǔ>}s~A=lg??}=>%D=rh>I>o?A> #?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhrh>c 1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhs?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/C JFDCEXhzr> Jclock pessimismXh%z -)SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhs~; J arrival timeXhy?/ JXh4 JslackXh}=>4 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[46]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsǔ>}s~A=lg??}=>%D=rh>I>o?A> #?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11(DCD - SCD - CPR) 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[9].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhrh>c 1-SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[46]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7I?X4Y3 (CLOCK_ROOT)h 62SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[9].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhs?X4Y3 (CLOCK_ROOT)a /+SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[46]/C JFDCEXhzr> Jclock pessimismXh%{ -)SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[46]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhs~; J arrival timeXhy?/ JXh4 JslackXh}=>4g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuX!@}A+AX9>?V.@X9@A=А="f@b>#۹> @!??n?I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xho? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfA`e> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh ק/ JXh4 JslackXh"f@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuX!@}A+AX9>?V.@X9@A=А="f@b>#۹> @!??n?I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xho? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfA`e> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh ק/ JXh4 JslackXh"f@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuX!@}A+AX9>?V.@X9@A=А="f@b>#۹> @!??n?I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xho? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfA`e> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh ק/ JXh4 JslackXh"f@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu9 @}A{+AEAV.@@A=А=ק@b>#۹>x @!??n?1?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xho? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfA`e> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh}??X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh{+A; J arrival timeXh/ JXh4 JslackXhק@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsu9 @}A{+AEAV.@@A=А=ק@b>#۹>x @!??n?1?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xho? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfA`e> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh}??X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh{+A; J arrival timeXh/ JXh4 JslackXhק@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuP@}A+AB`,V.@B`@A=А=~ݴ@]b>#۹>Q@!??n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xho? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfA`e> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C JFDCEXhzr> Jclock pessimismXh]b>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh~ݴ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuP@}A+AB`,V.@B`@A=А=~ݴ@]b>#۹>Q@!??n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xho? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfA`e> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/C JFDCEXhzr> Jclock pessimismXh]b>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh~ݴ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuQ@}A1+AC4V.@@A=А=7@ob>#۹>?!??n?.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xho? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfA`e> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xhy?X4Y3 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/C JFDCEXhzr> Jclock pessimismXhob>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1+A; J arrival timeXh+/ JXh4 JslackXh7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuQ@}A1+AC4V.@@A=А=7@ob>#۹>?!??n?.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xho? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfA`e> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)Xhy?X4Y3 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/C JFDCEXhzr> Jclock pessimismXhob>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1+A; J arrival timeXh+/ JXh4 JslackXh7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR"#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1*X4Y32#RCLK_BRAM_L_X78Y269/CLK_VDISTR_BOT1:X4Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_11 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_11 rise@0.000nsuy@}Ax+A~?/V.@~?@A=А=1@bb>#۹>(\?!??n?V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_11 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_11!gtwiz_userclk_rx_srcclk_out[0]_11#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xho? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfA`e> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_11 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[9] Jnet (fo=674, routed)XhP?X4Y3 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C JFDCEXhzr> Jclock pessimismXhbb>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhx+A; J arrival timeXh/ JXh4 JslackXh1@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12!)y@1y @9Ay@Iy @ecޒ@hq}M# >d rise - rise rise - rise  d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuD`e>}y<=V??M# >*s9H=333>">V.? >33S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh333> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl{?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhˡ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh*s g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh_?/ JXh4 JslackXhM# >Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuD`e>}y<=V??M# >*s9H=333>">V.? >33S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh333> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl{?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhˡ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh*s g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh_?/ JXh4 JslackXhM# >Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu>}y<=V??5>*s9H="[>">V.? >33S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh"[> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl{?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhˡ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXh*s g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhS?/ JXh4 JslackXh5>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu>}y<=V??5>*s9H="[>">V.? >33S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh"[> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl{?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhˡ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXh*s g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhS?/ JXh4 JslackXh5>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu>}y<=V??5>*s9H="[>">V.? >33S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh"[> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl{?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhˡ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXh*s g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhS?/ JXh4 JslackXh5>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu>}y<=V??5>*s9H="[>">V.? >33S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh"[> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl{?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhˡ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh*s g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhS?/ JXh4 JslackXh5>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu>}y<=V??5>*s9H="[>">V.? >33S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh"[> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl{?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhˡ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXh*s g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhS?/ JXh4 JslackXh5>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu>}y<=V??5>*s9H="[>">V.? >33S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh"[> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl{?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhˡ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh*s g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhS?/ JXh4 JslackXh5>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu>}y<=V??5>*s9H="[>">V.? >33S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh"[> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl{?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhˡ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXh*s g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhS?/ JXh4 JslackXh5>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu>}y<=V??5>*s9H="[>">V.? >33S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh"[> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl{?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhˡ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh*s g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[0].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhS?/ JXh4 JslackXh5>R/g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsug@}Ae0A'1(c<4@'1(@A=А=cޒ@d>Cl>%Y@*??? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhG1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhR@X4Y7 (CLOCK_ROOT)y GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh EAg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhe0A; J arrival timeXhhf/ JXh4 JslackXhcޒ@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu+g@}A40Ac(-T<4@c(@A=А=@d>Cl>NbX@*??? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhG1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh40A; J arrival timeXh|/ JXh4 JslackXh@ $g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu+g@}A40Ac(-T<4@c(@A=А=@d>Cl>NbX@*??? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhG1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh40A; J arrival timeXh|/ JXh4 JslackXh@ $g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsu+g@}A40Ac(-T<4@c(@A=А=@d>Cl>NbX@*??? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhG1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]Recov_GFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh40A; J arrival timeXh|/ JXh4 JslackXh@ #g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuKg@}A0ANb(I<4@Nb(@A=А=8@d>Cl>X@*????z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhG1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh$/ JXh4 JslackXh8@ $g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuKg@}A0ANb(I<4@Nb(@A=А=8@d>Cl>X@*????z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhG1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh$/ JXh4 JslackXh8@ #g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuKg@}A0ANb(I<4@Nb(@A=А=8@d>Cl>X@*????z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhG1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh$/ JXh4 JslackXh8@ #g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsuKg@}A0ANb(I<4@Nb(@A=А=8@d>Cl>X@*????z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhG1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhy@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh$/ JXh4 JslackXh8@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsua@}A`0A+';4@+'@A=А=D@d>Cl>33S@*???z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhG1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh- @X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh`0A; J arrival timeXh|/ JXh4 JslackXhD@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR""RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0*X4Y72"RCLK_DSP_L_X75Y509/CLK_VDISTR_BOT0:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_12 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_12 rise@0.000nsua@}A`0A+';4@+'@A=А=D@d>Cl>33S@*???z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_12 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_12!gtwiz_userclk_rx_srcclk_out[0]_12#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhG1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfj= @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_12 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[1].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh- @X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh`0A; J arrival timeXh|/ JXh4 JslackXhD@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13!)y@1y @9Ay@Iy @e*&@hq}7>d rise - rise rise - rise  eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuhff>}:z둿ڐ=im??7>9H=X94>> ?d;>)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhX94> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh)\O?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh:z; J arrival timeXh?/ JXh4 JslackXh7>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuhff>}:z둿ڐ=im??7>9H=X94>> ?d;>)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhX94> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh)\O?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh:z; J arrival timeXh?/ JXh4 JslackXh7>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuhff>}:z둿ڐ=im??7>9H=X94>> ?d;>)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhX94> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh)\O?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh:z; J arrival timeXh?/ JXh4 JslackXh7>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuhff>}:z둿ڐ=im??7>9H=X94>> ?d;>)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhX94> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh)\O?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh:z; J arrival timeXh?/ JXh4 JslackXh7>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuhff>}:z둿ڐ=im??7>9H=X94>> ?d;>)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhX94> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh)\O?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh:z; J arrival timeXh?/ JXh4 JslackXh7>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuhff>}:z둿ڐ=im??7>9H=X94>> ?d;>)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhX94> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh)\O?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh:z; J arrival timeXh?/ JXh4 JslackXh7>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuhff>}:z둿ڐ=im??7>9H=X94>> ?d;>)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhX94> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh)\O?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh:z; J arrival timeXh?/ JXh4 JslackXh7>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuhff>}:z둿ڐ=im??7>9H=X94>> ?d;>)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhX94> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh)\O?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh:z; J arrival timeXh?/ JXh4 JslackXh7>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuD`e>} 8Է=im??>U9H=433>> ?d;>x)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh433> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh)\O?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXhU g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh 8; J arrival timeXht?/ JXh4 JslackXh>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsuD`e>} 8Է=im??>U9H=433>> ?d;>x)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh433> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh)\O?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXhU g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh 8; J arrival timeXht?/ JXh4 JslackXh>RNg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsul@}AL+ARd)\/@@A=А=*&@d>5^>A@|?-?`?r=?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh@z HDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh!?X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhL+A; J arrival timeXh/ JXh4 JslackXh*&@ Og_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsul@}AL+ARd)\/@@A=А=*&@d>5^>A@|?-?`?r=?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh@z HDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh!?X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhL+A; J arrival timeXh/ JXh4 JslackXh*&@ Ng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsul@}AL+ARd)\/@@A=А=*&@d>5^>A@|?-?`?r=?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh@z HDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh!?X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhL+A; J arrival timeXh/ JXh4 JslackXh*&@ Ng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsul@}AL+ARd)\/@@A=А=*&@d>5^>A@|?-?`?r=?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh@z HDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh!?X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhL+A; J arrival timeXh/ JXh4 JslackXh*&@ /g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@5^>X@|?-?`??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh% @r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh8?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/C JFDCEXhzr> Jclock pessimismXh|d>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhK(+A; J arrival timeXhV/ JXh4 JslackXhI+@ .g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@5^>X@|?-?`??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh% @r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh8?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/C JFDCEXhzr> Jclock pessimismXh|d>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhK(+A; J arrival timeXhV/ JXh4 JslackXhI+@ /g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@5^>X@|?-?`??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh% @r @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh8?X4Y9 (CLOCK_ROOT)p >:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C JFDCEXhzr> Jclock pessimismXh|d>@ Jclock uncertaintyXh <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]Recov_BFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhK(+A; J arrival timeXhV/ JXh4 JslackXhI+@ Zg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CKGg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu@}A. +A:o)\/@@A=А=+@d>5^>%@|?-?`?Ԩ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhNb@} KGg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT){ IEg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh. +A; J arrival timeXh-/ JXh4 JslackXh+@ Ng_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu@}A. +A:o)\/@@A=А=+@d>5^>%@|?-?`?Ԩ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhNb@z HDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh. +A; J arrival timeXh-/ JXh4 JslackXh+@ Og_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1*X4Y92#RCLK_BRAM_L_X78Y569/CLK_VDISTR_TOP1:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_13 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_13 rise@0.000nsu@}A. +A:o)\/@@A=А=+@d>5^>%@|?-?`?Ԩ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_13 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_13!gtwiz_userclk_rx_srcclk_out[0]_13#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)XhNb@z HDg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_13 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT)x FBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]/C JFDCEXhzr> Jclock pessimismXhd>@ Jclock uncertaintyXh D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh. +A; J arrival timeXh-/ JXh4 JslackXh+@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14!)y@1y @9Ay@Iy @e#@hq}gh>d rise - rise rise - rise  SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu>}?o팿.n<$f??gh>S/9H="[>p=>?.> ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh"[> hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhG?X4Y9 (CLOCK_ROOT) SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xho?X4Y9 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXhS/ d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh?o; J arrival timeXhk?/ JXh4 JslackXhgh>eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuM>}x1=ˡe?1?x>`<9H=L7>p=>M?.>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhL7> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhlG?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhm?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXh`< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXhZd?/ JXh4 JslackXhx>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuM>}x1=ˡe?1?x>`<9H=L7>p=>M?.>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhL7> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhlG?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhm?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXh`< g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXhZd?/ JXh4 JslackXhx>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuµ>}Oyj0=ˡe?j? g>49H=>p=>M?.>w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhlG?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhn?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh4 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhOy; J arrival timeXhA?/ JXh4 JslackXh g>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuµ>}Oyj0=ˡe?j? g>49H=>p=>M?.>w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhlG?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhn?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXh4 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhOy; J arrival timeXhA?/ JXh4 JslackXh g>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuµ>}Oyj0=ˡe?j? g>49H=>p=>M?.>w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhlG?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhn?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXh4 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhOy; J arrival timeXhA?/ JXh4 JslackXh g>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuµ>}Oyj0=ˡe?j? g>49H=>p=>M?.>w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhlG?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhn?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXh4 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhOy; J arrival timeXhA?/ JXh4 JslackXh g>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuµ>}Oyj0=ˡe?j? g>49H=>p=>M?.>w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhlG?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhn?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh4 g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhOy; J arrival timeXhA?/ JXh4 JslackXh g>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu7^>}{OL=ˡe?O? d>'"9H=G>p=>M?.>7!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhG> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhlG?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhNbp?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXh'" g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh{; J arrival timeXhsh?/ JXh4 JslackXh d>Reag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu7^>}{OL=ˡe?O? d>'"9H=G>p=>M?.>7!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14(DCD - SCD - CPR) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhG> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhlG?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhNbp?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXh'" g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh{; J arrival timeXhsh?/ JXh4 JslackXh d>R73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsupe@}A<)A 4V&@ @A=А=#@"U>V>D\@R??Mb?Nb?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhD\@d 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[72]/C JFDCEXhzr> Jclock pessimismXh"U>@ Jclock uncertaintyXh{ .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[72]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh<)A; J arrival timeXhT/ JXh4 JslackXh#@473SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsupe@}A<)A 4V&@ @A=А=#@"U>V>D\@R??Mb?Nb?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhD\@d 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[74]/C JFDCEXhzr> Jclock pessimismXh"U>@ Jclock uncertaintyXh| .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[74]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh<)A; J arrival timeXhT/ JXh4 JslackXh#@473SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu`@}A.)A- "5V&@- @A=А=y@B%U>V>cX@R??Mb?A?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhcX@d 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[64]/C JFDCEXhzr> Jclock pessimismXhB%U>@ Jclock uncertaintyXh{ .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[64]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh.)A; J arrival timeXh/ JXh4 JslackXhy@473SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu`@}A.)A- "5V&@- @A=А=y@B%U>V>cX@R??Mb?A?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhcX@d 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[66]/C JFDCEXhzr> Jclock pessimismXhB%U>@ Jclock uncertaintyXh| .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[66]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh.)A; J arrival timeXh/ JXh4 JslackXhy@473SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu`@}A)Ah :7V&@h @A=А=@*U>V>W@R??Mb??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhW@d 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh&1?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]/C JFDCEXhzr> Jclock pessimismXh*U>@ Jclock uncertaintyXh{ .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[68]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh)A; J arrival timeXhl/ JXh4 JslackXh@473SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu`@}A)Ah :7V&@h @A=А=@*U>V>W@R??Mb??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhW@d 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh&1?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[70]/C JFDCEXhzr> Jclock pessimismXh*U>@ Jclock uncertaintyXh| .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[70]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh)A; J arrival timeXhl/ JXh4 JslackXh@473SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu~Z@}A)AEv+V&@E@A=А=l@ U>V>Q@R??Mb?rh?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhQ@d 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[76]/C JFDCEXhzr> Jclock pessimismXh U>@ Jclock uncertaintyXh{ .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[76]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh)A; J arrival timeXhj/ JXh4 JslackXhl@473SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsu~Z@}A)AEv+V&@E@A=А=l@ U>V>Q@R??Mb?rh?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhQ@d 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[78]/C JFDCEXhzr> Jclock pessimismXh U>@ Jclock uncertaintyXh| .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[78]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh)A; J arrival timeXhj/ JXh4 JslackXhl@473SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuG@}A4*Al V&@l@A=А=@zT>V>?5>@R??Mb?F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh?5>@d 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]/C JFDCEXhzr> Jclock pessimismXhzT>@ Jclock uncertaintyXh{ .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[44]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh4*A; J arrival timeXhQ/ JXh4 JslackXh@473SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[46]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0*X4Y92"RCLK_DSP_L_X75Y569/CLK_VDISTR_TOP0:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_14 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_14 rise@0.000nsuG@}A4*Al V&@l@A=А=@zT>V>?5>@R??Mb?F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_14 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_14!gtwiz_userclk_rx_srcclk_out[0]_14#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[23].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh?5>@d 2.SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[46]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y9 (CLOCK_ROOT)i 73SFP_GEN[23].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_14 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[23].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[46]/C JFDCEXhzr> Jclock pessimismXhzT>@ Jclock uncertaintyXh| .*SFP_GEN[23].ngCCM_gbt/RX_Word_rx40_reg[46]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh4*A; J arrival timeXhQ/ JXh4 JslackXh@4D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15!)y@1y @9Ay@Iy @eq@hq}n>d rise - rise rise - rise  d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsurh>}%(/=?/?n>oVD=K7>>2? >cX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhK7> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhc?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXhoV g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%(; J arrival timeXh2?/ JXh4 JslackXhn>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsurh>}%(/=?/?n>oVD=K7>>2? >cX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhK7> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhc?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXhoV g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%(; J arrival timeXh2?/ JXh4 JslackXhn>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsurh>}%(/=?/?n>oVD=K7>>2? >cX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhK7> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhc?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXhoV g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%(; J arrival timeXh2?/ JXh4 JslackXhn>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsurh>}%(/=?/?n>oVD=K7>>2? >cX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhK7> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhc?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXhoV g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%(; J arrival timeXh2?/ JXh4 JslackXhn>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsurh>}%(/=?/?n>oVD=K7>>2? >cX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhK7> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhc?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXhoV g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh%(; J arrival timeXh2?/ JXh4 JslackXhn>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu k>}jpĬ=?p?>SD=5^:>>2? >uX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh5^:> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXhS g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhj?/ JXh4 JslackXh>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu k>}jpĬ=?p?>SD=5^:>>2? >uX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh5^:> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXhS g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhj?/ JXh4 JslackXh>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu k>}jpĬ=?p?>SD=5^:>>2? >uX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh5^:> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXhS g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhj?/ JXh4 JslackXh>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu k>}jpĬ=?p?>SD=5^:>>2? >uX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh5^:> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXhS g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhj?/ JXh4 JslackXh>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu k>}jpĬ=?p?>SD=5^:>>2? >uX?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh5^:> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXhS g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhj?/ JXh4 JslackXh>Rg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuI@}A1A#)W=D4@#)@A=А=q@`>(>Vm@q=*?+??t?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh4@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)XhNb@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C JFDCEXhzr> Jclock pessimismXh`>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh\/ JXh4 JslackXhq@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuI@}A1A#)W=D4@#)@A=А=q@`>(>Vm@q=*?+??t?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh4@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)XhNb@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C JFDCEXhzr> Jclock pessimismXh`>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh\/ JXh4 JslackXhq@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuI@}A1A#)W=D4@#)@A=А=q@`>(>Vm@q=*?+??t?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh4@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)XhNb@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C JFDCEXhzr> Jclock pessimismXh`>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh\/ JXh4 JslackXhq@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu@}Au0A^)O=D4@^)@A=А=x@`>(>jl@q=*?+??23?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh4@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)XhA@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C JFDCEXhzr> Jclock pessimismXh`>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhu0A; J arrival timeXhr=/ JXh4 JslackXhx@ ;g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu{@}A0A)gS=D4@)@A=А=%Љ@`>(>Ah@q=*?+??S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh4@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)XhQ@X4Y7 (CLOCK_ROOT)y GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C JFDCEXhzr> Jclock pessimismXh`>@ Jclock uncertaintyXh EAg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh(/ JXh4 JslackXh%Љ@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu"{@}A\0A)L}K=D4@)@A=А=@`>(>g@q=*?+??o?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh4@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh'1@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C JFDCEXhzr> Jclock pessimismXh`>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh\0A; J arrival timeXh / JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu"{@}A\0A)L}K=D4@)@A=А=@`>(>g@q=*?+??o?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh4@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh'1@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C JFDCEXhzr> Jclock pessimismXh`>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh\0A; J arrival timeXh / JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu"{@}A\0A)L}K=D4@)@A=А=@`>(>g@q=*?+??o?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh4@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh'1@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C JFDCEXhzr> Jclock pessimismXh`>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]Recov_FFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh\0A; J arrival timeXh / JXh4 JslackXh@ 0g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsu"{@}A\0A)L}K=D4@)@A=А=@`>(>g@q=*?+??o?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh4@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh'1@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/C JFDCEXhzr> Jclock pessimismXh`>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh\0A; J arrival timeXh / JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR"#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1*X4Y72#RCLK_BRAM_L_X78Y509/CLK_VDISTR_BOT1:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_15 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_15 rise@0.000nsuOu@}A0AL7)O.=D4@L7)@A=А=@`>(>a@q=*?+??-?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_15 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_15!gtwiz_userclk_rx_srcclk_out[0]_15#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh4@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh$@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_15 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xhw@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C JFDCEXhzr> Jclock pessimismXh`>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]Recov_BFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16!)y@1y @9Ay@Iy @et@hq}^5>d rise - rise rise - rise  RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsugm>}*XNL=?X?^5>9H=Zd;>>sh1?X9>VN?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZd;> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhX9?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_regRemov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh*; J arrival timeXh?/ JXh4 JslackXh^5>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[66]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu>}ؘ(w=?(?G;>9H=bX>>sh1?X9>S?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhbX> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[66]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh> ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[66]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[66]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhؘ; J arrival timeXhA?/ JXh4 JslackXhG;>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[73]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu>}ؘ(w=?(?G;>9H=bX>>sh1?X9>S?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhbX> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[73]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh> ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[73]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[73]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhؘ; J arrival timeXhA?/ JXh4 JslackXhG;>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[74]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu>}ؘ(w=?(?G;>9H=bX>>sh1?X9>S?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhbX> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[74]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh> ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[74]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[74]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhؘ; J arrival timeXhA?/ JXh4 JslackXhG;>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[66]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu>}ؘ(w=?(?G;>9H=bX>>sh1?X9>S?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhbX> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[66]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh> ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[66]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[66]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhؘ; J arrival timeXhA?/ JXh4 JslackXhG;>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[73]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu>}ؘ(w=?(?G;>9H=bX>>sh1?X9>S?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhbX> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[73]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh> ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[73]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[73]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhؘ; J arrival timeXhA?/ JXh4 JslackXhG;>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[74]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu>}ؘ(w=?(?G;>9H=bX>>sh1?X9>S?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhbX> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[74]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh> ?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[74]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[74]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhؘ; J arrival timeXhA?/ JXh4 JslackXhG;>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[64]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu'1>};Dݙ=?D?T>>a9H=@5^>>sh1?X9>kT?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@5^> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[64]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[64]/C JFDCEXhzr> Jclock pessimismXha c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[64]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh;; J arrival timeXh%?/ JXh4 JslackXhT>>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[65]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu'1>};Dݙ=?D?T>>a9H=@5^>>sh1?X9>kT?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@5^> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[65]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[65]/C JFDCEXhzr> Jclock pessimismXha c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[65]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh;; J arrival timeXh%?/ JXh4 JslackXhT>>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[75]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu'1>};Dݙ=?D?T>>a9H=@5^>>sh1?X9>kT?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh@5^> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[75]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl?X4Y7 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[75]/C JFDCEXhzr> Jclock pessimismXha c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[75]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh;; J arrival timeXh%?/ JXh4 JslackXhT>>g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Czvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/PRE"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuFS@}A]0AL7)q=F3@L7)@A=А=t@W_d>V>J@.?33?v?A?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/AS[0] Jnet (fo=32, routed)XhJ@ zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/PRE JFDPEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw@X4Y7 (CLOCK_ROOT) xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]/C JFDPEXhzr> Jclock pessimismXhW_d>@ Jclock uncertaintyXh vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[0]Recov_AFF_SLICEM_C_PRE JFDPEXhv/ JXh< J required timeXh]0A; J arrival timeXhF/ JXh4 JslackXht@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Czvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[1]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuFS@}A]0AL7)q=F3@L7)@A=А=t@W_d>V>J@.?33?v?A?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/AS[0] Jnet (fo=32, routed)XhJ@ zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw@X4Y7 (CLOCK_ROOT) xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[1]/C JFDCEXhzr> Jclock pessimismXhW_d>@ Jclock uncertaintyXh vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[1]Recov_AFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh]0A; J arrival timeXhF/ JXh4 JslackXht@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Czvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuFS@}A]0AL7)q=F3@L7)@A=А=t@W_d>V>J@.?33?v?A?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/AS[0] Jnet (fo=32, routed)XhJ@ zvg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw@X4Y7 (CLOCK_ROOT) xtg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]/C JFDCEXhzr> Jclock pessimismXhW_d>@ Jclock uncertaintyXh vrg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/FSM_onehot_clkSlipProcess.state_reg[2]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh]0A; J arrival timeXhF/ JXh4 JslackXht@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C_[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsu/L@}A+1AM*[=F3@M*@A=А=E @W_d>V>C@.?33?v?n?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> UQg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/AS[0] Jnet (fo=32, routed)XhC@ _[g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> njg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X4Y7 (CLOCK_ROOT) ]Yg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_reg/C JFDCEXhzr> Jclock pessimismXhW_d>@ Jclock uncertaintyXh [Wg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].rxBitSlipControl/READY_o_regRecov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+1A; J arrival timeXhI/ JXh4 JslackXhE @ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuCD@}Aԣ0A'1(50=F3@'1(@A=А=&@W_d>>M2@.?33?v??5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)XhR@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C JFDCEXhzr> Jclock pessimismXhW_d>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhԣ0A; J arrival timeXh / JXh4 JslackXh&@ 4g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuCD@}Aԣ0A'1(50=F3@'1(@A=А=&@W_d>>M2@.?33?v??5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)XhR@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/C JFDCEXhzr> Jclock pessimismXhW_d>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhԣ0A; J arrival timeXh / JXh4 JslackXh&@ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuCD@}Aԣ0A'1(50=F3@'1(@A=А=&@W_d>>M2@.?33?v??5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)XhR@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzr> Jclock pessimismXhW_d>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhԣ0A; J arrival timeXh / JXh4 JslackXh&@ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuCD@}Aԣ0A'1(50=F3@'1(@A=А=&@W_d>>M2@.?33?v??5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhq=@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_0[0] Jnet (fo=674, routed)XhR@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C JFDCEXhzr> Jclock pessimismXhW_d>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhԣ0A; J arrival timeXh / JXh4 JslackXh&@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuX9D@}A0AX)y=F3@X)@A=А=N@W_d>>F+@.?33?v??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhB`@ fbg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__13/I0 JXhzr eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__13/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzf"y> WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhX? TPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh;@X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhW_d>@ Jclock uncertaintyXh PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhN@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X76Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_16 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_16 rise@0.000nsuX9D@}A0AX)y=F3@X)@A=А=N@W_d>>F+@.?33?v??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_16 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_16!gtwiz_userclk_rx_srcclk_out[0]_16#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhB`@ fbg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__13/I0 JXhzr eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__13/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzf"y> WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhX? YUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_16 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh;@X4Y7 (CLOCK_ROOT) WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhW_d>@ Jclock uncertaintyXh UQg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhN@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17!)y@1y @9Ay@Iy @e@hq} >d rise - rise rise - rise  73SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[15].ngCCM_gbt/pwr_good_pre_reg/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu&y>}C灿-=im?-? >MD=9H>>M?>]"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) 73SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[15].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh9H>` .*SFP_GEN[15].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh)\O?X4Y7 (CLOCK_ROOT)i 73SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[15].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhz?X4Y7 (CLOCK_ROOT)^ ,(SFP_GEN[15].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhMw *&SFP_GEN[15].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhC灿; J arrival timeXh?/ JXh4 JslackXh >4Hd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Ctpg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsun>}sဿ&߄=uJD=p=>>?> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xhp=> tpg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xhdx?X4Y7 (CLOCK_ROOT) rng_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXhuJ plg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhsဿ; J arrival timeXh•?/ JXh4 JslackXh'>Rmd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C}yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuq>}P#sh=GD=@>>?>&!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= jfg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xh@> }yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xhvx?X4Y7 (CLOCK_ROOT) {wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXhG yug_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhP#; J arrival timeXh$?/ JXh4 JslackXhp (>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu>}%ɂ=OD=@5^>>?>A ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXhO g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh#ۙ?/ JXh4 JslackXhH>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu>}%ɂ=OD=@5^>>?>A ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXhO g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh#ۙ?/ JXh4 JslackXhH>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu>}%ɂ=OD=@5^>>?>A ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXhO g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh#ۙ?/ JXh4 JslackXhH>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu>}%ɂ=OD=@5^>>?>A ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXhO g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh#ۙ?/ JXh4 JslackXhH>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu>}%ɂ=OD=@5^>>?>A ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh@5^> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXhO g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh#ۙ?/ JXh4 JslackXhH>R73SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuَ>}ހ&C=im?&?M>bD=Cl>>M?> ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) 73SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[15].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhCl>d 2.SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh)\O?X4Y7 (CLOCK_ROOT)i 73SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[15].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhdx?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30]/C JFDCEXhzr> Jclock pessimismXhb{ .*SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[30]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhހ; J arrival timeXh~?/ JXh4 JslackXhM>473SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuَ>}ހ&C=im?&?M>bD=Cl>>M?> ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17(DCD - SCD - CPR) 73SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[15].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhCl>d 2.SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh)\O?X4Y7 (CLOCK_ROOT)i 73SFP_GEN[15].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[15].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhdx?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXhb{ .*SFP_GEN[15].ngCCM_gbt/RX_Word_rx40_reg[32]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhހ; J arrival timeXh~?/ JXh4 JslackXhM>4g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu֣0@}Ab*AXk4@@A=А=@X[>>ff@)????z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhS? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C JFDCEXhzr> Jclock pessimismXhX[>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhb*A; J arrival timeXh!/ JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu֣0@}Ab*AXk4@@A=А=@X[>>ff@)????z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhS? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C JFDCEXhzr> Jclock pessimismXhX[>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhb*A; J arrival timeXh!/ JXh4 JslackXh@ 2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu֣0@}Ab*AXk4@@A=А=@X[>>ff@)????z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhS? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)XhQ?X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/C JFDCEXhzr> Jclock pessimismXhX[>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhb*A; J arrival timeXh!/ JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu.@}A+Ank4@n@A=А=bD@ԃ[>>k@)???/ݤ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhS? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C JFDCEXhzr> Jclock pessimismXhԃ[>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh"۱/ JXh4 JslackXhbD@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsu.@}A+Ank4@n@A=А=bD@ԃ[>>k@)???/ݤ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhS? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C JFDCEXhzr> Jclock pessimismXhԃ[>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh"۱/ JXh4 JslackXhbD@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuy.@}A +A6^q.k4@6^@A=А=wD@s[>>@)???k?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhS? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C JFDCEXhzr> Jclock pessimismXhs[>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh +A; J arrival timeXhұ/ JXh4 JslackXhwD@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuy.@}A +A6^q.k4@6^@A=А=wD@s[>>@)???k?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhS? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C JFDCEXhzr> Jclock pessimismXhs[>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh +A; J arrival timeXhұ/ JXh4 JslackXhwD@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuy.@}A +A6^q.k4@6^@A=А=wD@s[>>@)???k?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhS? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh?X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C JFDCEXhzr> Jclock pessimismXhs[>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh +A; J arrival timeXhұ/ JXh4 JslackXhwD@ =g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuv.@}A+Aq=1k4@q=@A=А=m@[>>X9@)???z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhS? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh8?X4Y7 (CLOCK_ROOT)y GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C JFDCEXhzr> Jclock pessimismXh[>@ Jclock uncertaintyXh EAg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhm@ 1g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR"#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT*X4Y72#RCLK_CLE_M_L_X75Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_17 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_17 rise@0.000nsuv.@}A+Aq=1k4@q=@A=А=m@[>>X9@)???z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_17 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_17!gtwiz_userclk_rx_srcclk_out[0]_17#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhS? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_17 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh8?X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/C JFDCEXhzr> Jclock pessimismXh[>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhm@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18!)y@1y @9Ay@Iy @e@hq} >d rise - rise rise - rise  d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuE5^>} r!=Ƌ?r? >IOD=W->̌>2?Ġ>EV?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhW-> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhS?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXhIO g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXhQ?/ JXh4 JslackXh >R73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu]B>}ٙv=V??H3>MED=rh>̌>5?Ġ>Z?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) 73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[16].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhrh>d 2.SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl{?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[72]/C JFDCEXhzr> Jclock pessimismXhME{ .*SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[72]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhٙ; J arrival timeXhB`?/ JXh4 JslackXhH3>473SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu]B>}ٙv=V??H3>MED=rh>̌>5?Ġ>Z?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) 73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[16].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhrh>d 2.SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl{?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[74]/C JFDCEXhzr> Jclock pessimismXhME| .*SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[74]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhٙ; J arrival timeXhB`?/ JXh4 JslackXhH3>473SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu]B>}ٙv=V??H3>MED=rh>̌>5?Ġ>Z?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) 73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[16].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhrh>d 2.SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl{?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[76]/C JFDCEXhzr> Jclock pessimismXhME{ .*SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[76]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhٙ; J arrival timeXhB`?/ JXh4 JslackXhH3>473SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu]B>}ٙv=V??H3>MED=rh>̌>5?Ġ>Z?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) 73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[16].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhrh>d 2.SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl{?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[78]/C JFDCEXhzr> Jclock pessimismXhME| .*SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[78]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhٙ; J arrival timeXhB`?/ JXh4 JslackXhH3>473SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu]B>}ٙv=V??H3>MED=rh>̌>5?Ġ>Z?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) 73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[16].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhrh>d 2.SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl{?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[81]/C JFDCEXhzr> Jclock pessimismXhME{ .*SFP_GEN[16].ngCCM_gbt/RX_Word_rx40_reg[81]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhٙ; J arrival timeXhB`?/ JXh4 JslackXhH3>4d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu>}6^(=Ƌ?6^?}&>'D== W>̌>2?Ġ>Z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh= W> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh~??X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh' g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh̬?/ JXh4 JslackXh}&>R73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[16].ngCCM_gbt/pwr_good_pre_reg/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuJs>} -=V??&>*D=\B>̌>5?Ġ>QW?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) 73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[16].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh\B>` .*SFP_GEN[16].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl{?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[16].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[16].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)^ ,(SFP_GEN[16].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh*w *&SFP_GEN[16].ngCCM_gbt/pwr_good_pre_regRemov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXh ?/ JXh4 JslackXh&>4d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu>}~35=Ƌ?~?*>'D=(\>̌>2?Ġ>6^Z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh(\> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhB`?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh' g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhp?/ JXh4 JslackXh*>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu>}~35=Ƌ?~?*>'D=(\>̌>2?Ġ>6^Z?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh(\> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhXy?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhB`?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh' g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhp?/ JXh4 JslackXh*>R3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu9x@}A0Aa(=e=/@a(@A=А=@a>5^>sha@I "?Nb?n?ˡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xha@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh:@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xhl@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhm/ JXh4 JslackXh@ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu9x@}A0Aa(=e=/@a(@A=А=@a>5^>sha@I "?Nb?n?ˡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xha@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh:@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xhl@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhm/ JXh4 JslackXh@ 4g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu9x@}A0Aa(=e=/@a(@A=А=@a>5^>sha@I "?Nb?n?ˡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xha@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh:@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xhl@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhm/ JXh4 JslackXh@ 4g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu9x@}A0Aa(=e=/@a(@A=А=@a>5^>sha@I "?Nb?n?ˡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xha@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh:@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xhl@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]Recov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhm/ JXh4 JslackXh@ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu9x@}A0Aa(=e=/@a(@A=А=@a>5^>sha@I "?Nb?n?ˡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xha@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh:@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xhl@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhm/ JXh4 JslackXh@ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsu9x@}A0Aa(=e=/@a(@A=А=@a>5^>sha@I "?Nb?n?ˡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xha@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh:@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xhl@X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]Recov_FFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhm/ JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuM7q@}A0A)E>/@)@A=А=z@a>5^>Y@I "?Nb?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xha@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh:@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh(/ JXh4 JslackXhz@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuM7q@}A0A)E>/@)@A=А=z@a>5^>Y@I "?Nb?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xha@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh:@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh(/ JXh4 JslackXhz@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsuM7q@}A0A)E>/@)@A=А=z@a>5^>Y@I "?Nb?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xha@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh:@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh(/ JXh4 JslackXhz@ ?g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT*X4Y82$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_BOT:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_18 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_18 rise@0.000nsup@}A0A(uq=/@(@A=А=@a>5^>xY@I "?Nb?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_18 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_18!gtwiz_userclk_rx_srcclk_out[0]_18#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xha@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh:@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_18 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh|@X4Y8 (CLOCK_ROOT)y GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh EAg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19!)y@1y @9Ay@Iy @eӶ@hq}C[>d rise - rise rise - rise  RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuI >}qDRZ =lg?D?C[>ZQ#9H=Q>̌>?w>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhQ> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhL7I?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXhZQ# c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_regRemov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhq; J arrival timeXhX9?/ JXh4 JslackXhC[>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuN>} sO&=lg?O?$>M#9H=|>̌>?w> ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh|> fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhL7I?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhNbp?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzr> Jclock pessimismXhM# b^g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh s; J arrival timeXh?/ JXh4 JslackXh$>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cuqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu>}sh~/=lg?h?ۣ>r#9H=>̌>?w>$!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhL7I?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh_p?X4Y8 (CLOCK_ROOT) sog_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C JFDCEXhzr> Jclock pessimismXhr# qmg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhs; J arrival timeXh?/ JXh4 JslackXhۣ>d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu ף>}=xm狿|=+g?m?ױ>c9H=>̌>]?w>.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhH?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhim?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXhc g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh=x; J arrival timeXhD?/ JXh4 JslackXhױ>RRNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[45]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu!>}0~َ=lg?َ?'>$9H=>̌>?w>#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[45]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhL7I?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhts?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[45]/C JFDCEXhzr> Jclock pessimismXh$ c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[45]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh0~; J arrival timeXhNb?/ JXh4 JslackXh'>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[13]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu!>}0~َ=lg?َ?'>$9H=>̌>?w>#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhL7I?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhts?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[13]/C JFDCEXhzr> Jclock pessimismXh$ c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[13]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh0~; J arrival timeXhNb?/ JXh4 JslackXh'>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[45]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu!>}0~َ=lg?َ?'>$9H=>̌>?w>#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[45]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhL7I?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhts?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[45]/C JFDCEXhzr> Jclock pessimismXh$ c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[45]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh0~; J arrival timeXhNb?/ JXh4 JslackXh'>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[53]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu!>}0~َ=lg?َ?'>$9H=>̌>?w>#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[53]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhL7I?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhts?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[53]/C JFDCEXhzr> Jclock pessimismXh$ c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[53]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh0~; J arrival timeXhNb?/ JXh4 JslackXh'>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[5]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu!>}0~َ=lg?َ?'>$9H=>̌>?w>#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhL7I?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhts?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[5]/C JFDCEXhzr> Jclock pessimismXh$ b^g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[5]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh0~; J arrival timeXhNb?/ JXh4 JslackXh'>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu23>}0~َ=lg?َ?>$9H=>̌>?w>#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhL7I?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhts?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]/C JFDCEXhzr> Jclock pessimismXh$ c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh0~; J arrival timeXh?/ JXh4 JslackXh>~73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuMb8@}A v*APB1<@P@A=А=Ӷ@ *c>V>|/@G!??-?o?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|/@d 2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhˡ@X4Y8 (CLOCK_ROOT)i 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[64]/C JFDCEXhzr> Jclock pessimismXh *c>@ Jclock uncertaintyXh{ .*SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[64]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh v*A; J arrival timeXh?5/ JXh4 JslackXhӶ@473SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuMb8@}A v*APB1<@P@A=А=Ӷ@ *c>V>|/@G!??-?o?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh|/@d 2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhˡ@X4Y8 (CLOCK_ROOT)i 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[66]/C JFDCEXhzr> Jclock pessimismXh *c>@ Jclock uncertaintyXh| .*SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[66]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh v*A; J arrival timeXh?5/ JXh4 JslackXhӶ@4~73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu61@}Ae*AKI1<@K@A=А=@4c>V>ף(@G!??-?[?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhף(@d 2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhˡ@X4Y8 (CLOCK_ROOT)i 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr> Jclock pessimismXh4c>@ Jclock uncertaintyXh{ .*SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[52]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhe*A; J arrival timeXhȶ/ JXh4 JslackXh@473SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu61@}Ae*AKI1<@K@A=А=@4c>V>ף(@G!??-?[?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhף(@d 2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhˡ@X4Y8 (CLOCK_ROOT)i 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[54]/C JFDCEXhzr> Jclock pessimismXh4c>@ Jclock uncertaintyXh| .*SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[54]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhe*A; J arrival timeXhȶ/ JXh4 JslackXh@4~73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuT%@}A*At%꾵1<@t@A=А=x@c>V>@G!??-??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhˡ@X4Y8 (CLOCK_ROOT)i 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[56]/C JFDCEXhzr> Jclock pessimismXhc>@ Jclock uncertaintyXh{ .*SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[56]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhx@473SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuT%@}A*At%꾵1<@t@A=А=x@c>V>@G!??-??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhˡ@X4Y8 (CLOCK_ROOT)i 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]/C JFDCEXhzr> Jclock pessimismXhc>@ Jclock uncertaintyXh| .*SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[58]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhx@4~73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuT%@}A*At%꾵1<@t@A=А=x@c>V>@G!??-??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhˡ@X4Y8 (CLOCK_ROOT)i 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[76]/C JFDCEXhzr> Jclock pessimismXhc>@ Jclock uncertaintyXh{ .*SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[76]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhx@473SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsuT%@}A*At%꾵1<@t@A=А=x@c>V>@G!??-??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@d 2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhˡ@X4Y8 (CLOCK_ROOT)i 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?5?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[78]/C JFDCEXhzr> Jclock pessimismXhc>@ Jclock uncertaintyXh| .*SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[78]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh*A; J arrival timeXh/ JXh4 JslackXhx@4~73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu}?%@}AϮ*Ard)뾵1<@r@A=А=ƹ@Sc>V>Z@G!??-?/ݤ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZ@d 2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhˡ@X4Y8 (CLOCK_ROOT)i 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]/C JFDCEXhzr> Jclock pessimismXhSc>@ Jclock uncertaintyXh{ .*SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[60]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhϮ*A; J arrival timeXhף/ JXh4 JslackXhƹ@473SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR"#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT*X4Y82#RCLK_CLE_M_L_X75Y569/CLK_VDISTR_BOT:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_19 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_19 rise@0.000nsu}?%@}AϮ*Ard)뾵1<@r@A=А=ƹ@Sc>V>Z@G!??-?/ݤ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_19 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_19!gtwiz_userclk_rx_srcclk_out[0]_19#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[17].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZ@d 2.SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhˡ@X4Y8 (CLOCK_ROOT)i 73SFP_GEN[17].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_19 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[17].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[62]/C JFDCEXhzr> Jclock pessimismXhSc>@ Jclock uncertaintyXh| .*SFP_GEN[17].ngCCM_gbt/RX_Word_rx40_reg[62]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhϮ*A; J arrival timeXhף/ JXh4 JslackXhƹ@4B **async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2!)y@1y @9Ay@Iy @e8f@hq}&>d rise - rise rise - rise  SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[43]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuأp>}($=zt?$?&>jD 9H=v>>̌>;?w>-2?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[43]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh%?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[43]/C JFDCEXhzr> Jclock pessimismXhjD  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[43]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh(; J arrival timeXhQ?/ JXh4 JslackXh&>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[46]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuأp>}($=zt?$?&>jD 9H=v>>̌>;?w>-2?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[46]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh%?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[46]/C JFDCEXhzr> Jclock pessimismXhjD  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[46]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh(; J arrival timeXhQ?/ JXh4 JslackXh&>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[50]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuأp>}($=zt?$?&>jD 9H=v>>̌>;?w>-2?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[50]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh%?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[50]/C JFDCEXhzr> Jclock pessimismXhjD  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[50]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh(; J arrival timeXhQ?/ JXh4 JslackXh&>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuأp>}($=zt?$?&>jD 9H=v>>̌>;?w>-2?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh%?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]/C JFDCEXhzr> Jclock pessimismXhjD  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[23]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh(; J arrival timeXhQ?/ JXh4 JslackXh&>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[26]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuأp>}($=zt?$?&>jD 9H=v>>̌>;?w>-2?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[26]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh%?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[26]/C JFDCEXhzr> Jclock pessimismXhjD  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[26]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh(; J arrival timeXhQ?/ JXh4 JslackXh&>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[46]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuأp>}($=zt?$?&>jD 9H=v>>̌>;?w>-2?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[46]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh%?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[46]/C JFDCEXhzr> Jclock pessimismXhjD  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[46]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh(; J arrival timeXhQ?/ JXh4 JslackXh&>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[50]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuأp>}($=zt?$?&>jD 9H=v>>̌>;?w>-2?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhv>> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[50]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh%?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[50]/C JFDCEXhzr> Jclock pessimismXhjD  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[50]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh(; J arrival timeXhQ?/ JXh4 JslackXh&>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuv>},T=zt?,?S>)? 9H=D>̌>;?w>2?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhD> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhsh?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]/C JFDCEXhzr> Jclock pessimismXh)?  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg0_reg[26]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhS>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuv>},T=zt?,?S>)? 9H=D>̌>;?w>2?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhD> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhsh?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]/C JFDCEXhzr> Jclock pessimismXh)?  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[27]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhS>SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[43]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZj]gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuv>},T=zt?,?S>)? 9H=D>̌>;?w>2?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2(DCD - SCD - CPR) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhD> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[43]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhEV?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhsh?X4Y3 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[43]/C JFDCEXhzr> Jclock pessimismXh)?  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/reg1_reg[43]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhS>g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@X> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhT%?r @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh6^@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C JFDCEXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*+A; J arrival timeXh/ JXh4 JslackXh8f@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@X> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhT%?r @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh6^@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C JFDCEXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*+A; J arrival timeXh/ JXh4 JslackXh8f@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@X> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhT%?r @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh6^@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh?X4Y3 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C JFDCEXhzr> Jclock pessimismXhC >@ Jclock uncertaintyXh <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh*+A; J arrival timeXh/ JXh4 JslackXh8f@ 2g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CKGg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsuff@}A$1,Aff A0@ff@A=А≠@W_d>X>v?G!??-?İ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xho#?} KGg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh6^@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh"?X4Y3 (CLOCK_ROOT){ IEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C JFDCEXhzr> Jclock pessimismXhW_d>@ Jclock uncertaintyXh GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh$1,A; J arrival timeXh/ JXh4 JslackXh̸@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@X>v?G!??-?İ?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xho#?r @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh6^@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)Xh"?X4Y3 (CLOCK_ROOT)p >:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C JFDCEXhzr> Jclock pessimismXhW_d>@ Jclock uncertaintyXh <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh$1,A; J arrival timeXh/ JXh4 JslackXh̸@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CUQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu@}A ,AJ0@@A=А=N@vd>t>?G!??-??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh㥛? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10/I0 JXhzr fbg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzfu> XTg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xhp= ? UQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh6^@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh9?X4Y3 (CLOCK_ROOT) SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhvd>@ Jclock uncertaintyXh QMg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh ,A; J arrival timeXhʙ/ JXh4 JslackXhN@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CZVg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsu@}A ,AJ0@@A=А=N@vd>t>?G!??-??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> jfg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh㥛? gcg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10/I0 JXhzr fbg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzfu> XTg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xhp= ? ZVg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh6^@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> NJg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh9?X4Y3 (CLOCK_ROOT) XTg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhvd>@ Jclock uncertaintyXh VRg_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_AFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh ,A; J arrival timeXhʙ/ JXh4 JslackXhN@ &g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsux@}A,A-L0@-@A=А=[@.|d>X>?G!??-?*\?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhQ>z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh6^@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)Xhr?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C JFDCEXhzr> Jclock pessimismXh.|d>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXh[@ 'g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsux@}A,A-L0@-@A=А=[@.|d>X>?G!??-?*\?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhQ>z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh6^@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)Xhr?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C JFDCEXhzr> Jclock pessimismXh.|d>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXh[@ &g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR"#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT*X4Y32#RCLK_CLE_M_L_X75Y269/CLK_VDISTR_BOT:X4Y3BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_2 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_2 rise@0.000nsux@}A,A-L0@-@A=А=[@.|d>X>?G!??-?*\?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_2 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_2 gtwiz_userclk_rx_srcclk_out[0]_2#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhQ>z HDg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh6^@X4Y3 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_2 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> *&g_gbt_bank[0].gbtbank/RX_WORDCLK_O[11] Jnet (fo=674, routed)Xhr?X4Y3 (CLOCK_ROOT)x FBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/C JFDCEXhzr> Jclock pessimismXh.|d>@ Jclock uncertaintyXh D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh,A; J arrival timeXh/ JXh4 JslackXh[@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20!)y@1y @9Ay@Iy @e@hq}3=d rise - rise rise - rise  RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuZ>}{- =Mb?-?3= v9H='>̌>[d>w>G!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh'> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhD?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh&q?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh v c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh{; J arrival timeXhj?/ JXh4 JslackXh3=73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[18].ngCCM_gbt/pwr_good_pre_reg/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsu+1>}`w-=Om??Ve>;u%D=e;_>̌>:?w>T%?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhe;_>` .*SFP_GEN[18].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhu?X4Y8 (CLOCK_ROOT)^ ,(SFP_GEN[18].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh;u%w *&SFP_GEN[18].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh`w; J arrival timeXh;?/ JXh4 JslackXhVe>4d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuʡ>}x(Lp=rh?(?<(>V9H=:>̌> ?w>?5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh:> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhq=J?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhzn?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXhV g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXh?/ JXh4 JslackXh<(>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuʡ>}x(Lp=rh?(?<(>V9H=:>̌> ?w>?5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh:> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhq=J?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhzn?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXhV g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXh?/ JXh4 JslackXh<(>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuʡ>}x(Lp=rh?(?<(>V9H=:>̌> ?w>?5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh:> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhq=J?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhzn?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXhV g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXh?/ JXh4 JslackXh<(>RRNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuη>}%zyD%=Mb?D?6v>F9H=S>̌>[d>w>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhD?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhn?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]/C JFDCEXhzr> Jclock pessimismXhF c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[27]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh%zy; J arrival timeXh?/ JXh4 JslackXh6v>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuη>}%zyD%=Mb?D?6v>F9H=S>̌>[d>w>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhD?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhn?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]/C JFDCEXhzr> Jclock pessimismXhF c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[32]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh%zy; J arrival timeXh?/ JXh4 JslackXh6v>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuη>}%zyD%=Mb?D?6v>F9H=S>̌>[d>w>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhD?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhn?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]/C JFDCEXhzr> Jclock pessimismXhF c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[33]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh%zy; J arrival timeXh?/ JXh4 JslackXh6v>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[41]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsun>}od~lw=Mb??_A>[9H=X>̌>[d>w> #?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhX> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[41]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhD?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhFs?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[41]/C JFDCEXhzr> Jclock pessimismXh[ c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[41]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhod~; J arrival timeXh¥?/ JXh4 JslackXh_A>RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsun>}od~lw=Mb??_A>[9H=X>̌>[d>w> #?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhX> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhD?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhFs?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]/C JFDCEXhzr> Jclock pessimismXh[ c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[44]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhod~; J arrival timeXh¥?/ JXh4 JslackXh_A>|73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsui\@}A%*A>@(@@A=А=@`Z>V> S@!?S? ?rh?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh S@d 2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)i 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr> Jclock pessimismXh`Z>@ Jclock uncertaintyXh{ .*SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[18]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh%*A; J arrival timeXh/ JXh4 JslackXh@4}73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsui\@}A%*A>@(@@A=А=@`Z>V> S@!?S? ?rh?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh S@d 2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)i 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[19]/C JFDCEXhzr> Jclock pessimismXh`Z>@ Jclock uncertaintyXh| .*SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[19]Recov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh%*A; J arrival timeXh/ JXh4 JslackXh@4|73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsui\@}A%*A>@(@@A=А=@`Z>V> S@!?S? ?rh?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh S@d 2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)i 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[20]/C JFDCEXhzr> Jclock pessimismXh`Z>@ Jclock uncertaintyXh{ .*SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[20]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh%*A; J arrival timeXh/ JXh4 JslackXh@4}73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsui\@}A%*A>@(@@A=А=@`Z>V> S@!?S? ?rh?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh S@d 2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)i 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzr> Jclock pessimismXh`Z>@ Jclock uncertaintyXh| .*SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[25]Recov_BFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh%*A; J arrival timeXh/ JXh4 JslackXh@4|73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuZ@}AZ*A'3(@@A=А=#@>Z>V>^Q@!?S? ?o?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh^Q@d 2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)i 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[64]/C JFDCEXhzr> Jclock pessimismXh>Z>@ Jclock uncertaintyXh{ .*SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[64]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhZ*A; J arrival timeXhh/ JXh4 JslackXh#@4}73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuZ@}AZ*A'3(@@A=А=#@>Z>V>^Q@!?S? ?o?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh^Q@d 2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)i 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[66]/C JFDCEXhzr> Jclock pessimismXh>Z>@ Jclock uncertaintyXh| .*SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[66]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhZ*A; J arrival timeXhh/ JXh4 JslackXh#@4|73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuZ@}AZ*A'3(@@A=А=#@>Z>V>^Q@!?S? ?o?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh^Q@d 2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)i 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[68]/C JFDCEXhzr> Jclock pessimismXh>Z>@ Jclock uncertaintyXh{ .*SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[68]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhZ*A; J arrival timeXhh/ JXh4 JslackXh#@4}73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuZ@}AZ*A'3(@@A=А=#@>Z>V>^Q@!?S? ?o?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh^Q@d 2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)i 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[70]/C JFDCEXhzr> Jclock pessimismXh>Z>@ Jclock uncertaintyXh| .*SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[70]Recov_GFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhZ*A; J arrival timeXhh/ JXh4 JslackXh#@4|73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuZ@}AZ*A'3(@@A=А=#@>Z>V>^Q@!?S? ?o?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh^Q@d 2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)i 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[72]/C JFDCEXhzr> Jclock pessimismXh>Z>@ Jclock uncertaintyXh{ .*SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[72]Recov_FFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhZ*A; J arrival timeXhh/ JXh4 JslackXh#@4}73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR""RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0*X4Y82"RCLK_DSP_L_X75Y569/CLK_VDISTR_BOT0:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_20 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_20 rise@0.000nsuZ@}AZ*A'3(@@A=А=#@>Z>V>^Q@!?S? ?o?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_20 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_20!gtwiz_userclk_rx_srcclk_out[0]_20#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>n *&SFP_GEN[18].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh^Q@d 2.SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> FBSFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh @X4Y8 (CLOCK_ROOT)i 73SFP_GEN[18].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_20 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84SFP_GEN[18].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[74]/C JFDCEXhzr> Jclock pessimismXh>Z>@ Jclock uncertaintyXh| .*SFP_GEN[18].ngCCM_gbt/RX_Word_rx40_reg[74]Recov_FFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhZ*A; J arrival timeXhh/ JXh4 JslackXh#@4D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21!)y@1y @9Ay@Iy @e@hq}K$>d rise - rise rise - rise  RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuw>}~=nr??K$>J)9H=ˡE>I>|?A>i-?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhˡE> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhY9T?X4Y8 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X4Y8 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXhJ) c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh~; J arrival timeXh'1?/ JXh4 JslackXhK$>73SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuƋ>}kG@=gff?G?V%>D=gff>I>I ?A>(1(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) 73SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[19].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhgff>d 2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQx?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[17]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[17]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhk; J arrival timeXh$?/ JXh4 JslackXhV%>473SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuƋ>}kG@=gff?G?V%>D=gff>I>I ?A>(1(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) 73SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[19].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhgff>d 2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQx?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhk; J arrival timeXh$?/ JXh4 JslackXhV%>473SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuƋ>}kG@=gff?G?V%>D=gff>I>I ?A>(1(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) 73SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[19].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhgff>d 2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQx?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[23]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhk; J arrival timeXh$?/ JXh4 JslackXhV%>473SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuƋ>}kG@=gff?G?V%>D=gff>I>I ?A>(1(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) 73SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[19].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhgff>d 2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQx?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[24]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[24]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhk; J arrival timeXh$?/ JXh4 JslackXhV%>473SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuƋ>}kG@=gff?G?V%>D=gff>I>I ?A>(1(?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) 73SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[19].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhgff>d 2.SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1H?X4Y8 (CLOCK_ROOT)i 73SFP_GEN[19].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[19].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhQx?X4Y8 (CLOCK_ROOT)b 0,SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[19].ngCCM_gbt/RX_Word_rx40_reg[28]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhk; J arrival timeXh$?/ JXh4 JslackXhV%>4d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu!Zd>}ΗX9y>=nr?X9?H/>D(9H=-2>I>|?A>{.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh-2> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhY9T?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5~?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXhD( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhΗ; J arrival timeXh•?/ JXh4 JslackXhH/>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuY>}z둿O<nr??m7>)9H=y&>I>|?A>x)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhy&> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhY9T?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhy?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhz; J arrival timeXhZ?/ JXh4 JslackXhm7>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu>}K!V=nr?!?l@>C9H== W>I>|?A> +?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh= W> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhY9T?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh"{?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXhC g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhK; J arrival timeXh6^?/ JXh4 JslackXhl@>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuI>}Z5=nr?Z?B>k!9H=fff>I>|?A>V.?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhfff> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhY9T?X4Y8 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhv~?X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXhk! g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhI?/ JXh4 JslackXhB>Rg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuA@}A+AB`".-@B`@A=А=@wb>rh>t3@!?.?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C JFDCEXhzr> Jclock pessimismXhwb>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh ׷/ JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuA@}A+AB`".-@B`@A=А=@wb>rh>t3@!?.?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/C JFDCEXhzr> Jclock pessimismXhwb>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh ׷/ JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuA@}A+AB`".-@B`@A=А=@wb>rh>t3@!?.?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C JFDCEXhzr> Jclock pessimismXhwb>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh ׷/ JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuA@}A+AB`".-@B`@A=А=@wb>rh>t3@!?.?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/C JFDCEXhzr> Jclock pessimismXhwb>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh ׷/ JXh4 JslackXh@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsuXA@}A+A~?$.-@~?@A=А=:@}b>rh>2@!?.?n?V?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhP?X4Y8 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/C JFDCEXhzr> Jclock pessimismXh}b>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXh:@ 1g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsue;7@}A+AB`".-@B`@A=А=1Y@wb>rh>:(@!?.?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzr> Jclock pessimismXhwb>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhv/ JXh4 JslackXh1Y@ 1g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsue;7@}A+AB`".-@B`@A=А=1Y@wb>rh>:(@!?.?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/C JFDCEXhzr> Jclock pessimismXhwb>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhv/ JXh4 JslackXh1Y@ =g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu!@}An,AUŠ.-@U@A=А=fR@bb>rh>C@!?.?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)y GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/C JFDCEXhzr> Jclock pessimismXhbb>@ Jclock uncertaintyXh EAg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhn,A; J arrival timeXhv/ JXh4 JslackXhfR@ 2g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu!@}An,AUŠ.-@U@A=А=fR@bb>rh>C@!?.?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C JFDCEXhzr> Jclock pessimismXhbb>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhn,A; J arrival timeXhv/ JXh4 JslackXhfR@ 1g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR"#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1*X4Y82#RCLK_BRAM_L_X78Y569/CLK_VDISTR_BOT1:X4Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_21 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_21 rise@0.000nsu!@}An,AUŠ.-@U@A=А=fR@bb>rh>C@!?.?n??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_21 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_21!gtwiz_userclk_rx_srcclk_out[0]_21#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhK@X4Y8 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_21 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh?X4Y8 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C JFDCEXhzr> Jclock pessimismXhbb>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhn,A; J arrival timeXhv/ JXh4 JslackXhfR@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22!)y@1y @9Ay@Iy @e)@hq}R>d rise - rise rise - rise  d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu>}^=q??R>(9H=/]>Ƌ> ?Ġ>)\/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh/]> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhFS?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhI?/ JXh4 JslackXhR>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu>}^=q??R>(9H=/]>Ƌ> ?Ġ>)\/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh/]> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhFS?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXh( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhI?/ JXh4 JslackXhR>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu>}^=q??R>(9H=/]>Ƌ> ?Ġ>)\/?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh/]> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhFS?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhw?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXh( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhI?/ JXh4 JslackXhR>RRNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu~>}q팿0-=yf??׏T>_{&9H=L>Ƌ>?Ġ>e;?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhL> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh:H?X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xho?X4Y9 (CLOCK_ROOT) eag_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh_{& c_g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhq; J arrival timeXhS?/ JXh4 JslackXh׏T>d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuَ>}X9W.E=q?X9?Gg>(9H=k>Ƌ> ?Ġ>-?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhk> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhFS?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5~?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXh( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh ?/ JXh4 JslackXhGg>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuَ>}X9W.E=q?X9?Gg>(9H=k>Ƌ> ?Ġ>-?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhk> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhFS?X4Y9 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh@5~?X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh( g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh ?/ JXh4 JslackXhGg>R73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu>};ztk=xi??Y}>d#0D=x>Ƌ>B`?Ġ>$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhx>d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhCK?X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr> Jclock pessimismXhd#0{ .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[18]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh;zt; J arrival timeXh?/ JXh4 JslackXhY}>473SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu>};ztk=xi??Y}>d#0D=x>Ƌ>B`?Ġ>$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhx>d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhCK?X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr> Jclock pessimismXhd#0| .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh;zt; J arrival timeXh?/ JXh4 JslackXhY}>473SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu>};ztk=xi??Y}>d#0D=x>Ƌ>B`?Ġ>$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhx>d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhCK?X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr> Jclock pessimismXhd#0{ .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[23]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh;zt; J arrival timeXh?/ JXh4 JslackXhY}>473SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu>};ztk=xi??Y}>d#0D=x>Ƌ>B`?Ġ>$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22(DCD - SCD - CPR) 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[20].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhx>d 2.SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhCK?X4Y9 (CLOCK_ROOT)i 73SFP_GEN[20].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[20].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X4Y9 (CLOCK_ROOT)b 0,SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]/C JFDCEXhzr> Jclock pessimismXhd#0| .*SFP_GEN[20].ngCCM_gbt/RX_Word_rx40_reg[24]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh;zt; J arrival timeXh?/ JXh4 JslackXhY}>43g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu--@}A)Ah sh1@h @A=А=)@(W>rh>+@ ?̡?rh?|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xh&1?X4Y9 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/C JFDCEXhzr> Jclock pessimismXh(W>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh)A; J arrival timeXhP/ JXh4 JslackXh)@ 4g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu--@}A)Ah sh1@h @A=А=)@(W>rh>+@ ?̡?rh?|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xh&1?X4Y9 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/C JFDCEXhzr> Jclock pessimismXh(W>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh)A; J arrival timeXhP/ JXh4 JslackXh)@ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu--@}A)Ah sh1@h @A=А=)@(W>rh>+@ ?̡?rh?|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xh&1?X4Y9 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C JFDCEXhzr> Jclock pessimismXh(W>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh)A; J arrival timeXhP/ JXh4 JslackXh)@ 3g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu--@}A)Ah sh1@h @A=А=)@(W>rh>+@ ?̡?rh?|?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xh&1?X4Y9 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/C JFDCEXhzr> Jclock pessimismXh(W>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh)A; J arrival timeXhP/ JXh4 JslackXh)@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuu'@}A)Aˡ lsh1@ˡ @A=А= @W>rh>L7@ ?̡?rh??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)XhQ?X4Y9 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/C JFDCEXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh)A; J arrival timeXht/ JXh4 JslackXh @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuu'@}A)Aˡ lsh1@ˡ @A=А= @W>rh>L7@ ?̡?rh??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)XhQ?X4Y9 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C JFDCEXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh)A; J arrival timeXht/ JXh4 JslackXh @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuu'@}A)Aˡ lsh1@ˡ @A=А= @W>rh>L7@ ?̡?rh??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)XhQ?X4Y9 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/C JFDCEXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh)A; J arrival timeXht/ JXh4 JslackXh @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsuu'@}A)Aˡ lsh1@ˡ @A=А= @W>rh>L7@ ?̡?rh??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT? g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3XhzfX9= @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)XhQ?X4Y9 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/C JFDCEXhzr> Jclock pessimismXhW>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh)A; J arrival timeXht/ JXh4 JslackXh @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu @}AW)AEeZsh1@E@A=А=˪@QxW>xi>q=@ ?̡?rh?`?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT? fbg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__19/I0 JXhzr eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__19/OProp_B6LUT_SLICEL_I0_O JLUT2XhzfE= WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh/? TPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhQxW>@ Jclock uncertaintyXh PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhW)A; J arrival timeXh/ JXh4 JslackXh˪@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP*X4Y92$RCLK_CLEL_R_L_X76Y569/CLK_VDISTR_TOP:X4Y9BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_22 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_22 rise@0.000nsu @}AW)AEeZsh1@E@A=А=˪@QxW>xi>q=@ ?̡?rh?`?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_22 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_22!gtwiz_userclk_rx_srcclk_out[0]_22#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhT? fbg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__19/I0 JXhzr eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__19/OProp_B6LUT_SLICEL_I0_O JLUT2XhzfE= WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh/? YUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X4Y9 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_22 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X4Y9 (CLOCK_ROOT) WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhQxW>@ Jclock uncertaintyXh UQg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhW)A; J arrival timeXh/ JXh4 JslackXh˪@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23!)y@1y @9Ay@Iy @eQp@hq}>d rise - rise rise - rise  d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsulg>}*:ʿS㿭O@=Mb?S?>-M9H=}?5>-?NbP?S#?y?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh}?5> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?5?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh-M g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh*:ʿ; J arrival timeXhO?/ JXh4 JslackXh>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsulg>}*:ʿS㿭O@=Mb?S?>-M9H=}?5>-?NbP?S#?y?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh}?5> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?5?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh-M g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh*:ʿ; J arrival timeXhO?/ JXh4 JslackXh>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu$>}sɿ\⿭)׆=Mb?\?iC>M9H=Z>-?NbP?S#?Pw?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZ> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXhM g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhsɿ; J arrival timeXh?/ JXh4 JslackXhiC>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu$>}sɿ\⿭)׆=Mb?\?iC>M9H=Z>-?NbP?S#?Pw?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZ> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXhM g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhsɿ; J arrival timeXh?/ JXh4 JslackXhiC>Rd`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu$>}sɿ\⿭)׆=Mb?\?iC>M9H=Z>-?NbP?S#?Pw?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZ> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X4Y7 (CLOCK_ROOT) d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhp?X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXhM g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhsɿ; J arrival timeXh?/ JXh4 JslackXhiC>R73SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu`>}ɿ⿭.yu=sh??P>JMD=Mb>-?nR?S#?bx?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) 73SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[21].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhMb>d 2.SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X4Y7 (CLOCK_ROOT)i 73SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[20]/C JFDCEXhzr> Jclock pessimismXhJM{ .*SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[20]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhɿ; J arrival timeXh ?/ JXh4 JslackXhP>473SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu`>}ɿ⿭.yu=sh??P>JMD=Mb>-?nR?S#?bx?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) 73SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[21].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhMb>d 2.SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X4Y7 (CLOCK_ROOT)i 73SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzr> Jclock pessimismXhJM| .*SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[25]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhɿ; J arrival timeXh ?/ JXh4 JslackXhP>473SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu`>}ɿ⿭.yu=sh??P>JMD=Mb>-?nR?S#?bx?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) 73SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[21].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhMb>d 2.SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X4Y7 (CLOCK_ROOT)i 73SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[26]/C JFDCEXhzr> Jclock pessimismXhJM{ .*SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[26]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhɿ; J arrival timeXh ?/ JXh4 JslackXhP>473SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu`>}ɿ⿭.yu=sh??P>JMD=Mb>-?nR?S#?bx?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) 73SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[21].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhMb>d 2.SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X4Y7 (CLOCK_ROOT)i 73SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzr> Jclock pessimismXhJM| .*SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[27]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhɿ; J arrival timeXh ?/ JXh4 JslackXhP>473SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu`>}ɿ⿭.yu=sh??P>JMD=Mb>-?nR?S#?bx?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23(DCD - SCD - CPR) 73SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[21].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhMb>d 2.SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhM?X4Y7 (CLOCK_ROOT)i 73SFP_GEN[21].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[21].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X4Y7 (CLOCK_ROOT)b 0,SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXhJM{ .*SFP_GEN[21].ngCCM_gbt/RX_Word_rx40_reg[28]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhɿ; J arrival timeXh ?/ JXh4 JslackXhP>4&RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu(t@}Aa:A"Sv@"S@A=А=Qp@F>)\>33k@h?@?i?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh33k@ hdg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhh@X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> uqg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh9@X4Y7 (CLOCK_ROOT) fbg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]/C JFDCEXhzr> Jclock pessimismXhF>@ Jclock uncertaintyXh d`g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/reg1_reg[112]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXha:A; J arrival timeXh/ JXh4 JslackXhQp@g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsupu@}A?AeS+@e@A=А= @F>$>O]@h? @?x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/@ fbg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__20/I0 JXhzr eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__20/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf!r> WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh+6? TPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh1L@X4Y7 (CLOCK_ROOT) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhF>@ Jclock uncertaintyXh PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh?A; J arrival timeXhM/ JXh4 JslackXh @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsupu@}A?AeS+@e@A=А= @F>$>O]@h? @?x?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> ieg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh/@ fbg_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__20/I0 JXhzr eag_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__20/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf!r> WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh+6? YUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh1L@X4Y7 (CLOCK_ROOT) WSg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhF>@ Jclock uncertaintyXh UQg_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh?A; J arrival timeXhM/ JXh4 JslackXh @ 0g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuzt@}A?AfK+@f@A=А=rp@F>>z\@h? @?~?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh0@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)XhCL@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzr> Jclock pessimismXhF>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh?A; J arrival timeXh/ JXh4 JslackXhrp@ 0g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuzt@}A?AfK+@f@A=А=rp@F>>z\@h? @?~?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh0@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)XhCL@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/C JFDCEXhzr> Jclock pessimismXhF>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh?A; J arrival timeXh/ JXh4 JslackXhrp@ 1g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuzt@}A?AfK+@f@A=А=rp@F>>z\@h? @?~?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh0@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)XhCL@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/C JFDCEXhzr> Jclock pessimismXhF>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh?A; J arrival timeXh/ JXh4 JslackXhrp@ <g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsus@}A[h?AeZ+@e@A=А=x@F>>[@h? @?9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh0@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)XhK@X4Y7 (CLOCK_ROOT)y GCg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/C JFDCEXhzr> Jclock pessimismXhF>@ Jclock uncertaintyXh EAg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh[h?A; J arrival timeXhX/ JXh4 JslackXhx@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsus@}A[h?AeZ+@e@A=А=x@F>>[@h? @?9?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh0@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)XhK@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C JFDCEXhzr> Jclock pessimismXhF>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh[h?A; J arrival timeXhX/ JXh4 JslackXhx@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsu%q@}A?A$fkI+@$f@A=А=4;@F>>%Y@h? @??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh0@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @:g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)Xhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)XhL@X4Y7 (CLOCK_ROOT)n <8g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C JFDCEXhzr> Jclock pessimismXhF>@ Jclock uncertaintyXh :6g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh?A; J arrival timeXh/ JXh4 JslackXh4;@ 0g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR"$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT*X4Y72$RCLK_CLEL_R_L_X64Y509/CLK_VDISTR_BOT:X4Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_23 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_23 rise@0.000nsuNbp@}A?AfK+@f@A=А=|@F>>NbX@h? @?~?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_23 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_23!gtwiz_userclk_rx_srcclk_out[0]_23#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh0@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/I0 JXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh`@X4Y7 (CLOCK_ROOT) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_23 rise edge)XhzrA g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[1].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)XhCL@X4Y7 (CLOCK_ROOT)v D@g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/C JFDCEXhzr> Jclock pessimismXhF>@ Jclock uncertaintyXh B>g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh?A; J arrival timeXh/ JXh4 JslackXh|@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24!)y@1y @9Ay@Iy @eX@hq}#,>d rise - rise rise - rise  RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[91]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@>}(=ף??#,>M9H=V>%>o#?>{F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[91]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh(?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[91]/C JFDCEXhzr> Jclock pessimismXhM c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[91]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh:?/ JXh4 JslackXh#,>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[96]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@>}(=ף??#,>M9H=V>%>o#?>{F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[96]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh(?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[96]/C JFDCEXhzr> Jclock pessimismXhM c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[96]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh:?/ JXh4 JslackXh#,>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[98]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@>}(=ף??#,>M9H=V>%>o#?>{F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[98]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh(?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[98]/C JFDCEXhzr> Jclock pessimismXhM c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[98]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh:?/ JXh4 JslackXh#,>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[56]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@>}(=ף??#,>M9H=V>%>o#?>{F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[56]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh(?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[56]/C JFDCEXhzr> Jclock pessimismXhM c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[56]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh:?/ JXh4 JslackXh#,>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[91]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@>}(=ף??#,>M9H=V>%>o#?>{F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[91]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh(?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[91]/C JFDCEXhzr> Jclock pessimismXhM c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[91]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh:?/ JXh4 JslackXh#,>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[96]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@>}(=ף??#,>M9H=V>%>o#?>{F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[96]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh(?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[96]/C JFDCEXhzr> Jclock pessimismXhM c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[96]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh:?/ JXh4 JslackXh#,>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[98]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu@>}(=ף??#,>M9H=V>%>o#?>{F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[98]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh(?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[98]/C JFDCEXhzr> Jclock pessimismXhM c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg1_reg[98]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh:?/ JXh4 JslackXh#,>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[51]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuC>}:і<߯s11=ף?<߯?k*>ɎM9H=rh>%>o#?>lG?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhrh> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[51]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhj?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[51]/C JFDCEXhzr> Jclock pessimismXhɎM c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[51]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh:і; J arrival timeXh?/ JXh4 JslackXhk*>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[56]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuC>}:і<߯s11=ף?<߯?k*>ɎM9H=rh>%>o#?>lG?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhrh> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[56]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhj?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[56]/C JFDCEXhzr> Jclock pessimismXhɎM c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[56]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh:і; J arrival timeXh?/ JXh4 JslackXhk*>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[58]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuC>}:і<߯s11=ף?<߯?k*>ɎM9H=rh>%>o#?>lG?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhrh> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[58]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhʁ?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhj?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[58]/C JFDCEXhzr> Jclock pessimismXhɎM c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[0].gbt_rxgearbox_inst/reg0_reg[58]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh:і; J arrival timeXh?/ JXh4 JslackXhk*>g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuʙ@}A1An*8@n*@A=А=X@X>(>1@CK??5?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh9h@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhX@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuʙ@}A1An*8@n*@A=А=X@X>(>1@CK??5?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh9h@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhX@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsuʙ@}A1An*8@n*@A=А=X@X>(>1@CK??5?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh9h@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh5^@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhX@ 3g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsux@}Ax*1A +?<8@ +@A=А=7a@X>(>F@CK??5? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh9h@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhx*1A; J arrival timeXhx/ JXh4 JslackXh7a@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsux@}Ax*1A +?<8@ +@A=А=7a@X>(>F@CK??5? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh9h@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhx*1A; J arrival timeXhx/ JXh4 JslackXh7a@ 'g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsux@}Ax*1A +?<8@ +@A=А=7a@X>(>F@CK??5? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh9h@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhx*1A; J arrival timeXhx/ JXh4 JslackXh7a@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu}?@}AF"1AG*;8@G*@A=А=! b@X>(>|@CK??5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh9h@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhF"1A; J arrival timeXh|?/ JXh4 JslackXh! b@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu}?@}AF"1AG*;8@G*@A=А=! b@X>(>|@CK??5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh9h@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhF"1A; J arrival timeXh|?/ JXh4 JslackXh! b@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu}?@}AF"1AG*;8@G*@A=А=! b@X>(>|@CK??5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh9h@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]Recov_FFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhF"1A; J arrival timeXh|?/ JXh4 JslackXh! b@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR"$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT*X1Y22$RCLK_CLEL_R_L_X29Y209/CLK_VDISTR_BOT:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_24 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_24 rise@0.000nsu}?@}AF"1AG*;8@G*@A=А=! b@X>(>|@CK??5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_24 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_24!gtwiz_userclk_rx_srcclk_out[0]_24#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh9h@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_24 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[2].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhF"1A; J arrival timeXh|?/ JXh4 JslackXh! b@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25!)y@1y @9Ay@Iy @eB3@hq}g>d rise - rise rise - rise  Weag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cuqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsui;_>}ML7^=/}?L7?g>9H=W->5^>M?>A5?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= kgg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhW-> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh|_?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ieg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xh…?X1Y4 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXh qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhM; J arrival timeXh~?/ JXh4 JslackXhg>R73SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu$>}NHᚿ?K= |?H?k4>zD="[>5^>?>8!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) 73SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[34].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh"[>d 2.SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[34].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXhz{ .*SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[32]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhN; J arrival timeXh<ߟ?/ JXh4 JslackXhk4>473SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu$>}NHᚿ?K= |?H?k4>zD="[>5^>?>8!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) 73SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[34].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh"[>d 2.SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[34].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXhz| .*SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[34]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhN; J arrival timeXh<ߟ?/ JXh4 JslackXhk4>473SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu$>}NHᚿ?K= |?H?k4>zD="[>5^>?>8!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) 73SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[34].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh"[>d 2.SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[34].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXhz{ .*SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[36]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhN; J arrival timeXh<ߟ?/ JXh4 JslackXhk4>473SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu$>}NHᚿ?K= |?H?k4>zD="[>5^>?>8!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) 73SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[34].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh"[>d 2.SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[34].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[34].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhl?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr> Jclock pessimismXhz| .*SFP_GEN[34].ngCCM_gbt/RX_Word_rx40_reg[38]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhN; J arrival timeXh<ߟ?/ JXh4 JslackXhk4>4eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu~>}~ㇿx=/}?x?X4>n9H=L>5^>M?>S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhL> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh|_?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXhn g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh~ㇿ; J arrival timeXhv?/ JXh4 JslackXhX4>Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu~>}~ㇿx=/}?x?X4>n9H=L>5^>M?>S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhL> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh|_?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXhn g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh~ㇿ; J arrival timeXhv?/ JXh4 JslackXhX4>Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu~>}~ㇿx=/}?x?X4>n9H=L>5^>M?>S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhL> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh|_?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXhn g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh~ㇿ; J arrival timeXhv?/ JXh4 JslackXhX4>Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu~>}~ㇿx=/}?x?X4>n9H=L>5^>M?>S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhL> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh|_?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXhn g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh~ㇿ; J arrival timeXhv?/ JXh4 JslackXhX4>Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu~>}~ㇿx=/}?x?X4>n9H=L>5^>M?>S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhL> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh|_?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXhn g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh~ㇿ; J arrival timeXhv?/ JXh4 JslackXhX4>R*g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@n>@MB?M?{.? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh> ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhgff?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 Jnet (fo=674, routed)Xh+?X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/C JFDCEXhzr> Jclock pessimismXh(P>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh)0+A; J arrival timeXh-/ JXh4 JslackXhB3@ )g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@n>@MB?M?{.? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh> ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhgff?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 Jnet (fo=674, routed)Xh+?X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C JFDCEXhzr> Jclock pessimismXh(P>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh)0+A; J arrival timeXh-/ JXh4 JslackXhB3@ )g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@n>@MB?M?{.? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh> ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhgff?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 Jnet (fo=674, routed)Xh+?X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C JFDCEXhzr> Jclock pessimismXh(P>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh)0+A; J arrival timeXh-/ JXh4 JslackXhB3@ )g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@n>@MB?M?{.?<ߟ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh> ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhd?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 Jnet (fo=674, routed)Xhy?X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C JFDCEXhzr> Jclock pessimismXh-P>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh (+A; J arrival timeXh/ JXh4 JslackXha\@ )g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@n>@MB?M?{.?<ߟ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh> ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhd?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 Jnet (fo=674, routed)Xhy?X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/C JFDCEXhzr> Jclock pessimismXh-P>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh (+A; J arrival timeXh/ JXh4 JslackXha\@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CUQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu@}A+AZd*04@Zd@A=А=>@3P>H>A@MB?M?{.??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__33/I0 JXhzr fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__33/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzfgff> XTg_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhB? UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh3P>@ Jclock uncertaintyXh QMg_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhE/ JXh4 JslackXh>@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CZVg_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu@}A+AZd*04@Zd@A=А=>@3P>H>A@MB?M?{.??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__33/I0 JXhzr fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__33/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzfgff> XTg_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhB? ZVg_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT) XTg_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh3P>@ Jclock uncertaintyXh VRg_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhE/ JXh4 JslackXh>@ )g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@n> @MB?M?{.?A?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh> ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh$?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 Jnet (fo=674, routed)XhK?X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C JFDCEXhzr> Jclock pessimismXh&P>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh74+A; J arrival timeXh/ JXh4 JslackXht@ Ug_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CKGg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT0:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_25 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_25 rise@0.000nsu<@}AC+A4@@A=А=@2O>n>h @MB?M?{.?!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh> ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh'1(?} KGg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 Jnet (fo=674, routed)Xh^?X1Y4 (CLOCK_ROOT){ IEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C JFDCEXhzr> Jclock pessimismXh2O>@ Jclock uncertaintyXh GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhC+A; J arrival timeXhff/ JXh4 JslackXh@ )g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@n>X9 @MB?M?{.??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_25 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_25!gtwiz_userclk_rx_srcclk_out[0]_25#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh> ? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1/OProp_C6LUT_SLICEM_I0_O JLUT3Xhzf> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh"?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_25 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7 Jnet (fo=674, routed)Xh= ?X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/C JFDCEXhzr> Jclock pessimismXhC+P>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh,+A; J arrival timeXh_/ JXh4 JslackXh՝@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26!)y@1y @9Ay@Iy @e%@hq} >d rise - rise rise - rise  eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuCl>}K7İ=?İ? >7!D=Zd;>>$&?A>~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZd;> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhЂ?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzr> Jclock pessimismXh7! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhK7; J arrival timeXhe;?/ JXh4 JslackXh >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuCl>}K7İ=?İ? >7!D=Zd;>>$&?A>~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZd;> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhЂ?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXh7! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhK7; J arrival timeXhe;?/ JXh4 JslackXh >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuCl>}K7İ=?İ? >7!D=Zd;>>$&?A>~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZd;> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhЂ?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXh7! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhK7; J arrival timeXhe;?/ JXh4 JslackXh >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuCl>}K7İ=?İ? >7!D=Zd;>>$&?A>~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZd;> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhЂ?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXh7! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhK7; J arrival timeXhe;?/ JXh4 JslackXh >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuCl>}K7İ=?İ? >7!D=Zd;>>$&?A>~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZd;> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhЂ?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXh7! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhK7; J arrival timeXhe;?/ JXh4 JslackXh >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuCl>}K7İ=?İ? >7!D=Zd;>>$&?A>~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZd;> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhЂ?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXh7! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhK7; J arrival timeXhe;?/ JXh4 JslackXh >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuCl>}K7İ=?İ? >7!D=Zd;>>$&?A>~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZd;> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhЂ?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh7! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhK7; J arrival timeXhe;?/ JXh4 JslackXh >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuCl>}K7İ=?İ? >7!D=Zd;>>$&?A>~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZd;> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhЂ?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh7! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhK7; J arrival timeXhe;?/ JXh4 JslackXh >Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuX9>}肖=??>MD='1>>$&?A>)1H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh'1> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhЂ?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh(?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXhM g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh肖; J arrival timeXhԨ?/ JXh4 JslackXh>Reag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsu!Zd>}&RL=?R?Fy>!D=433>>$&?A>gfF?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26(DCD - SCD - CPR) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh433> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= vrg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhЂ?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhC?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXh! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh&; J arrival timeXh@5?/ JXh4 JslackXhFy>Rg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CUQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuQx@}A0Aa(u8@a(@A=А=%@GZ>>zf@G??n2?r?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh6@ gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__34/I0 JXhzr fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__34/OProp_C6LUT_SLICEM_I0_O JLUT2Xhzf> XTg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB`@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhGZ>@ Jclock uncertaintyXh QMg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhr/ JXh4 JslackXh%@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CZVg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuQx@}A0Aa(u8@a(@A=А=%@GZ>>zf@G??n2?r?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> jfg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh6@ gcg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__34/I0 JXhzr fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__34/OProp_C6LUT_SLICEM_I0_O JLUT2Xhzf> XTg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB`@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) XTg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhGZ>@ Jclock uncertaintyXh VRg_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhr/ JXh4 JslackXh%@ 0g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>]@G??n2?I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh6@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh"?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB`@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C JFDCEXhzr> Jclock pessimismXhGZ>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh%1A; J arrival timeXhMb/ JXh4 JslackXhJ@ 0g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>]@G??n2?I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh6@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh"?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB`@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C JFDCEXhzr> Jclock pessimismXhGZ>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh%1A; J arrival timeXhMb/ JXh4 JslackXhJ@ 0g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>]@G??n2?I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh6@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh"?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB`@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C JFDCEXhzr> Jclock pessimismXhGZ>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh%1A; J arrival timeXhMb/ JXh4 JslackXhJ@ 1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>]@G??n2?~j?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh6@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhZd?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB`@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/C JFDCEXhzr> Jclock pessimismXhGZ>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh)1A; J arrival timeXh~j/ JXh4 JslackXhK@ 0g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@t>]@G??n2?~j?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh6@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhZd?r @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB`@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C JFDCEXhzr> Jclock pessimismXhGZ>@ Jclock uncertaintyXh <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh)1A; J arrival timeXh~j/ JXh4 JslackXhK@ \g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CKGg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuuo@}A1A!*gUu8@!*@A=А=@@GZ>t>O]@G??n2?2?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh6@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhX?} KGg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB`@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT){ IEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/C JFDCEXhzr> Jclock pessimismXhGZ>@ Jclock uncertaintyXh GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh(/ JXh4 JslackXh@@ Pg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuOm@}A0A)ziu8@)@A=А=n@GZ>t>GZ@G??n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh6@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh?z HDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB`@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)x FBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C JFDCEXhzr> Jclock pessimismXhGZ>@ Jclock uncertaintyXh D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhn@ Qg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR"$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT*X1Y42$RCLK_CLEL_R_L_X29Y329/CLK_VDISTR_BOT:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_26 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_26 rise@0.000nsuOm@}A0A)ziu8@)@A=А=n@GZ>t>GZ@G??n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_26 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_26!gtwiz_userclk_rx_srcclk_out[0]_26#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh6@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh?z HDg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhB`@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_26 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)x FBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C JFDCEXhzr> Jclock pessimismXhGZ>@ Jclock uncertaintyXh D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhn@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27!)y@1y @9Ay@Iy @e-@hq}>d rise - rise rise - rise  d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsumt>}㝿shE=\?sh?>E!D=C>>+'?G>CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhC> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXhE! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㝿; J arrival timeXh&?/ JXh4 JslackXh>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsumt>}㝿shE=\?sh?>E!D=C>>+'?G>CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhC> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzr> Jclock pessimismXhE! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㝿; J arrival timeXh&?/ JXh4 JslackXh>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsumt>}㝿shE=\?sh?>E!D=C>>+'?G>CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhC> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXhE! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㝿; J arrival timeXh&?/ JXh4 JslackXh>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsumt>}㝿shE=\?sh?>E!D=C>>+'?G>CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhC> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXhE! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㝿; J arrival timeXh&?/ JXh4 JslackXh>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsumt>}㝿shE=\?sh?>E!D=C>>+'?G>CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhC> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXhE! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㝿; J arrival timeXh&?/ JXh4 JslackXh>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsumt>}㝿shE=\?sh?>E!D=C>>+'?G>CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhC> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXhE! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㝿; J arrival timeXh&?/ JXh4 JslackXh>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsumt>}㝿shE=\?sh?>E!D=C>>+'?G>CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhC> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXhE! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㝿; J arrival timeXh&?/ JXh4 JslackXh>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsumt>}㝿shE=\?sh?>E!D=C>>+'?G>CK?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhC> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhF?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXhE! g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh㝿; J arrival timeXh&?/ JXh4 JslackXh>RRNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu">}e뱿=8??oaO>L!9H=I >>%?G>IL?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhI > gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh!?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]/C JFDCEXhzr> Jclock pessimismXhL! c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhe; J arrival timeXhQ?/ JXh4 JslackXhoaO>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu">}e뱿=8??oaO>L!9H=I >>%?G>IL?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhI > gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh!?X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/C JFDCEXhzr> Jclock pessimismXhL! c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhe; J arrival timeXhQ?/ JXh4 JslackXhoaO>g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuPw@}A1A~* >?5.@~*@A=А=-@aqX>/>lc@I?$?}?5?q=?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ,@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24/OProp_C6LUT_SLICEM_I0_O JLUT2Xhzf +> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh@5^? TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhn@X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhaqX>@ Jclock uncertaintyXh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhH/ JXh4 JslackXh-@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuPw@}A1A~* >?5.@~*@A=А=-@aqX>/>lc@I?$?}?5?q=?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZ,@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24/OProp_C6LUT_SLICEM_I0_O JLUT2Xhzf +> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh@5^? YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhn@X1Y2 (CLOCK_ROOT) WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhaqX>@ Jclock uncertaintyXh UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhH/ JXh4 JslackXh-@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuj@}AV(1A +->%>?5.@ +@A=А=-@aqX>d;>QV@I?$?}?5?C?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh,@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf/> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C JFDCEXhzr> Jclock pessimismXhaqX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhV(1A; J arrival timeXhj/ JXh4 JslackXh-@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuj@}AV(1A +->%>?5.@ +@A=А=-@aqX>d;>QV@I?$?}?5?C?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh,@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf/> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C JFDCEXhzr> Jclock pessimismXhaqX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhV(1A; J arrival timeXhj/ JXh4 JslackXh-@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuj@}AV(1A +->%>?5.@ +@A=А=-@aqX>d;>QV@I?$?}?5?C?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh,@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf/> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C JFDCEXhzr> Jclock pessimismXhaqX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhV(1A; J arrival timeXhj/ JXh4 JslackXh-@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsui@}A$ 1AG*1#>?5.@G*@A=А='@aqX>d;>{V@I?$?}?5? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh,@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf/> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C JFDCEXhzr> Jclock pessimismXhaqX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh$ 1A; J arrival timeXh/ JXh4 JslackXh'@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu[dc@}A]1A +2>?5.@ +@A=А=\@aqX>d;>|O@I?$?}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh,@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf/> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C JFDCEXhzr> Jclock pessimismXhaqX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh]1A; J arrival timeXh/ JXh4 JslackXh\@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu[dc@}A]1A +2>?5.@ +@A=А=\@aqX>d;>|O@I?$?}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh,@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf/> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C JFDCEXhzr> Jclock pessimismXhaqX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh]1A; J arrival timeXh/ JXh4 JslackXh\@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsu[dc@}A]1A +2>?5.@ +@A=А=\@aqX>d;>|O@I?$?}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh,@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf/> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C JFDCEXhzr> Jclock pessimismXhaqX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh]1A; J arrival timeXh/ JXh4 JslackXh\@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR"#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1*X1Y22#RCLK_BRAM_L_X30Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_27 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_27 rise@0.000nsuIb@}AKQ1A+{/>?5.@+@A=А=Q@aqX>d;>N@I?$?}?5?D?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_27 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_27!gtwiz_userclk_rx_srcclk_out[0]_27#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_AFF_SLICEL_C_Q JFDCEXhzr)\> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh,@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf/> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh @X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_27 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/C JFDCEXhzr> Jclock pessimismXhaqX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhKQ1A; J arrival timeXhD/ JXh4 JslackXhQ@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28!)y@1y @9Ay@Iy @e@hq}_>d rise - rise rise - rise  d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuD`e>}኿ß=A??_>r9H=433>j>?/> #?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh433> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh኿; J arrival timeXh?/ JXh4 JslackXh_>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuD`e>}኿ß=A??_>r9H=433>j>?/> #?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh433> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh኿; J arrival timeXh?/ JXh4 JslackXh_>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuD`e>}኿ß=A??_>r9H=433>j>?/> #?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh433> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh኿; J arrival timeXh?/ JXh4 JslackXh_>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuD`e>}኿ß=A??_>r9H=433>j>?/> #?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh433> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh኿; J arrival timeXh?/ JXh4 JslackXh_>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuD`e>}኿ß=A??_>r9H=433>j>?/> #?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh433> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh኿; J arrival timeXh?/ JXh4 JslackXh_>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuD`e>}኿ß=A??_>r9H=433>j>?/> #?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh433> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh኿; J arrival timeXh?/ JXh4 JslackXh_>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuD`e>}኿ß=A??_>r9H=433>j>?/> #?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh433> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhL7?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXhr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh኿; J arrival timeXh?/ JXh4 JslackXh_>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu k>}DV=A?V?l>l9H=X9>j>?/>$?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhX9> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXhl g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhD; J arrival timeXh.?/ JXh4 JslackXhl>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu>}M{=A?{?1'>FU9H=V>j>?/>&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhV> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXhFU g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhM; J arrival timeXhG?/ JXh4 JslackXh1'>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsuˡ>}VS=A?V?(>R9H=Y>j>?/>+'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhY> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhb?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhH?X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXhR g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh(>RRNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[13]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsum?}AQ+AV (,@V@A=А=@0P>V>G?ʡE??sh1? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhG? gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhC?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[13]/C JFDCEXhzr> Jclock pessimismXh0P>@ Jclock uncertaintyXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[13]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhQ+A; J arrival timeXhَ/ JXh4 JslackXh@RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[14]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsum?}AQ+AV (,@V@A=А=@0P>V>G?ʡE??sh1? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhG? gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhC?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[14]/C JFDCEXhzr> Jclock pessimismXh0P>@ Jclock uncertaintyXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[14]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhQ+A; J arrival timeXhَ/ JXh4 JslackXh@RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsum?}AQ+AV (,@V@A=А=@0P>V>G?ʡE??sh1? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhG? fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhC?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/C JFDCEXhzr> Jclock pessimismXh0P>@ Jclock uncertaintyXh b^g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhQ+A; J arrival timeXhَ/ JXh4 JslackXh@RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsum?}AQ+AV (,@V@A=А=@0P>V>G?ʡE??sh1? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhG? fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhC?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/C JFDCEXhzr> Jclock pessimismXh0P>@ Jclock uncertaintyXh b^g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhQ+A; J arrival timeXhَ/ JXh4 JslackXh@RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[13]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsum?}AQ+AV (,@V@A=А=@0P>V>G?ʡE??sh1? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhG? gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhC?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[13]/C JFDCEXhzr> Jclock pessimismXh0P>@ Jclock uncertaintyXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[13]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhQ+A; J arrival timeXhَ/ JXh4 JslackXh@RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[14]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsum?}AQ+AV (,@V@A=А=@0P>V>G?ʡE??sh1? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhG? gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhC?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[14]/C JFDCEXhzr> Jclock pessimismXh0P>@ Jclock uncertaintyXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[14]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhQ+A; J arrival timeXhَ/ JXh4 JslackXh@RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsum?}AQ+AV (,@V@A=А=@0P>V>G?ʡE??sh1? ף?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhG? fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhC?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]/C JFDCEXhzr> Jclock pessimismXh0P>@ Jclock uncertaintyXh b^g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]Recov_BFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhQ+A; J arrival timeXhَ/ JXh4 JslackXh@RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[86]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu?}A4+A?5(,@?5@A=А==!@5P>V>?ʡE??sh1??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh? gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[86]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhI?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[86]/C JFDCEXhzr> Jclock pessimismXh5P>@ Jclock uncertaintyXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[86]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh4+A; J arrival timeXh+/ JXh4 JslackXh=!@RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu?}A4+A?5(,@?5@A=А==!@5P>V>?ʡE??sh1??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh? gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhI?X1Y2 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]/C JFDCEXhzr> Jclock pessimismXh5P>@ Jclock uncertaintyXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh4+A; J arrival timeXh+/ JXh4 JslackXh=!@RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cfbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT0:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_28 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_28 rise@0.000nsu?}A4+A?5(,@?5@A=А==!@5P>V>?ʡE??sh1??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_28 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_28!gtwiz_userclk_rx_srcclk_out[0]_28#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh? fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_28 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhI?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]/C JFDCEXhzr> Jclock pessimismXh5P>@ Jclock uncertaintyXh b^g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh4+A; J arrival timeXh+/ JXh4 JslackXh=!@D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29!)y@1y @9Ay@Iy @e^@hq}\'>d rise - rise rise - rise  +d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Ctpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsur>}shR=-?sh?\'>1 D=T>>(1(? >hM?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhT> tpg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhS?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT) rng_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXh1  plg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh\'>RPd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C}yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu$>}iʱ=-?ʱ?j*>, D="[>>(1(? >VN?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= jfg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xh"[> }yg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhS?X1Y2 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)XhV?X1Y2 (CLOCK_ROOT) {wg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXh,  yug_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXhG?/ JXh4 JslackXhj*>R73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[48]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuK >}mŚ?5 = ??5?M.>I D=R>>$? >+G?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[48]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[48]/C JFDCEXhzr> Jclock pessimismXhI { .*SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[48]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhmŚ; J arrival timeXhף?/ JXh4 JslackXhM.>473SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuK >}mŚ?5 = ??5?M.>I D=R>>$? >+G?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[50]/C JFDCEXhzr> Jclock pessimismXhI | .*SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[50]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhmŚ; J arrival timeXhף?/ JXh4 JslackXhM.>473SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu<>}= ??5> D=A`>>$? >H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhA`>d 2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh䥛?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[72]/C JFDCEXhzr> Jclock pessimismXh { .*SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[72]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhM?/ JXh4 JslackXh5>473SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu<>}= ??5> D=A`>>$? >H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhA`>d 2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh䥛?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[74]/C JFDCEXhzr> Jclock pessimismXh | .*SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[74]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhM?/ JXh4 JslackXh5>473SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuMb>}2暿Vf= ?V?.J>I D=o>>$? >lG?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xho>d 2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhH?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[56]/C JFDCEXhzr> Jclock pessimismXhI { .*SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[56]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh2暿; J arrival timeXhX9?/ JXh4 JslackXh.J>473SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuMb>}2暿Vf= ?V?.J>I D=o>>$? >lG?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xho>d 2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhH?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[58]/C JFDCEXhzr> Jclock pessimismXhI | .*SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[58]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh2暿; J arrival timeXhX9?/ JXh4 JslackXh.J>473SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuMb>}2暿Vf= ?V?.J>I D=o>>$? >lG?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xho>d 2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhH?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[81]/C JFDCEXhzr> Jclock pessimismXhI { .*SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[81]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh2暿; J arrival timeXhX9?/ JXh4 JslackXh.J>473SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZj_gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuMb>}2暿Vf= ?V?.J>I D=o>>$? >lG?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29(DCD - SCD - CPR) 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[27].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xho>d 2.SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhG?X1Y2 (CLOCK_ROOT)i 73SFP_GEN[27].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[27].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhH?X1Y2 (CLOCK_ROOT)b 0,SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[83]/C JFDCEXhzr> Jclock pessimismXhI | .*SFP_GEN[27].ngCCM_gbt/RX_Word_rx40_reg[83]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh2暿; J arrival timeXhX9?/ JXh4 JslackXh.J>4;g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu0@}A0AL7)18=z4@L7)@A=А=^@\GU>n>H@ffF?)\?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhlo@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh&@X1Y2 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C JFDCEXhzr> Jclock pessimismXh\GU>@ Jclock uncertaintyXh EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhE/ JXh4 JslackXh^@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu0@}A0AL7)18=z4@L7)@A=А=^@\GU>n>H@ffF?)\?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhlo@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh&@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C JFDCEXhzr> Jclock pessimismXh\GU>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhE/ JXh4 JslackXh^@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuv@}A0A#)--=z4@#)@A=А=\a@\GU>n>O@ffF?)\?n2?5^?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhlo@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C JFDCEXhzr> Jclock pessimismXh\GU>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh9/ JXh4 JslackXh\a@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuv@}A0A#)--=z4@#)@A=А=\a@\GU>n>O@ffF?)\?n2?5^?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhlo@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C JFDCEXhzr> Jclock pessimismXh\GU>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh9/ JXh4 JslackXh\a@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuv@}A0A#)--=z4@#)@A=А=\a@\GU>n>O@ffF?)\?n2?5^?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhlo@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C JFDCEXhzr> Jclock pessimismXh\GU>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh9/ JXh4 JslackXh\a@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsuv@}A0A#)--=z4@#)@A=А=\a@\GU>n>O@ffF?)\?n2?5^?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhlo@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C JFDCEXhzr> Jclock pessimismXh\GU>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh9/ JXh4 JslackXh\a@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu$@}A0A^)$=z4@^)@A=А=nbb@\GU>n>@ffF?)\?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhlo@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C JFDCEXhzr> Jclock pessimismXh\GU>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhNb/ JXh4 JslackXhnbb@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu$@}A0A^)$=z4@^)@A=А=nbb@\GU>n>@ffF?)\?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhlo@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C JFDCEXhzr> Jclock pessimismXh\GU>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]Recov_GFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhNb/ JXh4 JslackXhnbb@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu$@}A0A^)$=z4@^)@A=А=nbb@\GU>n>@ffF?)\?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhlo@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf+> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C JFDCEXhzr> Jclock pessimismXh\GU>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]Recov_FFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhNb/ JXh4 JslackXhnbb@ 0g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR""RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1*X1Y22"RCLK_DSP_L_X27Y209/CLK_VDISTR_BOT1:X1Y2BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_29 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_29 rise@0.000nsu@}A|1AG*̶n=z4@G*@A=А=rg@\GU>n>Њ@ffF?)\?n2?~j?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_29 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_29!gtwiz_userclk_rx_srcclk_out[0]_29#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhlo@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1/OProp_B6LUT_SLICEL_I0_O JLUT3Xhzf+> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhG@X1Y2 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_29 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y2 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/C JFDCEXhzr> Jclock pessimismXh\GU>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]Recov_AFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh|1A; J arrival timeXh@5/ JXh4 JslackXhrg@ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3!)y@1y @9Ay@Iy @eN@hq}>d rise - rise rise - rise  #d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Ctpg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuxi>} 0Ŀ=t?0?>++9H=K7>(?D ?/?=/?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= jfg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhK7> tpg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhZ?X3Y0 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xhw?X3Y0 (CLOCK_ROOT) rng_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXh++ plg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXhأ?/ JXh4 JslackXh>RRNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuD`e>}yu)\=rh?)\?>9T,9H=433>(?r?/?/$?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh433> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhM?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhq=?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh9T, c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhyu; J arrival timeXh{?/ JXh4 JslackXh>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu>}_Y9Ŀ/-=rh?Y9?R:8>+9H=u>(?r?/?.?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhu> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhM?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/C JFDCEXhzr> Jclock pessimismXh+ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh_; J arrival timeXhgf?/ JXh4 JslackXhR:8>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu>}_Y9Ŀ/-=rh?Y9?R:8>+9H=u>(?r?/?.?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhu> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhM?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]/C JFDCEXhzr> Jclock pessimismXh+ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[30]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh_; J arrival timeXhgf?/ JXh4 JslackXhR:8>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[36]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu>}_Y9Ŀ/-=rh?Y9?R:8>+9H=u>(?r?/?.?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhu> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[36]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhM?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[36]/C JFDCEXhzr> Jclock pessimismXh+ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[36]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh_; J arrival timeXhgf?/ JXh4 JslackXhR:8>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[28]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu>}_Y9Ŀ/-=rh?Y9?R:8>+9H=u>(?r?/?.?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhu> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[28]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhM?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[28]/C JFDCEXhzr> Jclock pessimismXh+ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[28]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh_; J arrival timeXhgf?/ JXh4 JslackXhR:8>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu>}_Y9Ŀ/-=rh?Y9?R:8>+9H=u>(?r?/?.?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhu> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhM?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]/C JFDCEXhzr> Jclock pessimismXh+ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[30]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh_; J arrival timeXhgf?/ JXh4 JslackXhR:8>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[36]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu>}_Y9Ŀ/-=rh?Y9?R:8>+9H=u>(?r?/?.?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhu> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[36]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhM?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[36]/C JFDCEXhzr> Jclock pessimismXh+ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[36]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh_; J arrival timeXhgf?/ JXh4 JslackXhR:8>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu>}zĿJ=rh?z?=9>+9H=x>(?r?/?/?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhx> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhM?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh)\?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]/C JFDCEXhzr> Jclock pessimismXh+ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh=9>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsu>}zĿJ=rh?z?=9>+9H=x>(?r?/?/?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhx> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhM?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh)\?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]/C JFDCEXhzr> Jclock pessimismXh+ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh=9>g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuz@}A_7A@m2b@@@A=А=N@5|>>v~@?Z@~?z?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh]@ eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__0/I0 JXhzr d`g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__0/OProp_B6LUT_SLICEM_I0_O JLUT2Xhzf> WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhB`? TPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh|'@X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh5|>@ Jclock uncertaintyXh PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh_7A; J arrival timeXhE/ JXh4 JslackXhN@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuz@}A_7A@m2b@@@A=А=N@5|>>v~@?Z@~?z?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh]@ eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__0/I0 JXhzr d`g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__0/OProp_B6LUT_SLICEM_I0_O JLUT2Xhzf> WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhB`? YUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh|'@X3Y0 (CLOCK_ROOT) WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh5|>@ Jclock uncertaintyXh UQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh_7A; J arrival timeXhE/ JXh4 JslackXhN@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsue@}A7AXA0b@XA@A=А= z@Vt>d;>Q@?Z@~?~??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh% @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzf 0> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh<'@X3Y0 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C JFDCEXhzr> Jclock pessimismXhVt>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXh z@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsue@}A7AXA0b@XA@A=А= z@Vt>d;>Q@?Z@~?~??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh% @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzf 0> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xh<'@X3Y0 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C JFDCEXhzr> Jclock pessimismXhVt>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXh z@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuB`e@}A7AL7Akj1b@L7A@A=А=X]z@v>d;>xQ@?Z@~??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh% @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzf 0> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xhv'@X3Y0 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C JFDCEXhzr> Jclock pessimismXhv>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXhX]z@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuB`e@}A7AL7Akj1b@L7A@A=А=X]z@v>d;>xQ@?Z@~??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh% @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzf 0> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)Xhv'@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/C JFDCEXhzr> Jclock pessimismXhv>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh7A; J arrival timeXh/ JXh4 JslackXhX]z@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuK7a@}A% 8A#A.b@#A@A=А=(@i>d;>OM@?Z@~?E?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh% @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzf 0> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)XhMb(@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/C JFDCEXhzr> Jclock pessimismXhi>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh% 8A; J arrival timeXh/ JXh4 JslackXh(@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuK7a@}A% 8A#A.b@#A@A=А=(@i>d;>OM@?Z@~?E?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh% @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzf 0> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)XhMb(@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/C JFDCEXhzr> Jclock pessimismXhi>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh% 8A; J arrival timeXh/ JXh4 JslackXh(@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsuK7a@}A% 8A#A.b@#A@A=А=(@i>d;>OM@?Z@~?E?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh% @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzf 0> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)XhMb(@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/C JFDCEXhzr> Jclock pessimismXhi>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh% 8A; J arrival timeXh/ JXh4 JslackXh(@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR""RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1*X3Y02"RCLK_BRAM_L_X62Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_3 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_3 rise@0.000nsut`@}A8A^A^c/b@^A@A=А=@zl>d;> L@?Z@~??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_3 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_3 gtwiz_userclk_rx_srcclk_out[0]_3#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh% @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzf 0> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh^a@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_3 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[1] Jnet (fo=674, routed)XhA(@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C JFDCEXhzr> Jclock pessimismXhzl>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh8A; J arrival timeXhZ/ JXh4 JslackXh@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30!)y@1y @9Ay@Iy @eV^@hq}37=d rise - rise rise - rise  RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[72]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuG>}"=?"?37==6"9H=>>l?G>S>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[72]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh(|?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[72]/C JFDCEXhzr> Jclock pessimismXh=6" c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[72]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhT?/ JXh4 JslackXh37=RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[75]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuG>}"=?"?37==6"9H=>>l?G>S>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[75]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh(|?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[75]/C JFDCEXhzr> Jclock pessimismXh=6" c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[75]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhT?/ JXh4 JslackXh37=RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[72]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuG>}"=?"?37==6"9H=>>l?G>S>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[72]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh(|?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[72]/C JFDCEXhzr> Jclock pessimismXh=6" c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[72]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhT?/ JXh4 JslackXh37=RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[75]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuG>}"=?"?37==6"9H=>>l?G>S>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[75]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh(|?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[75]/C JFDCEXhzr> Jclock pessimismXh=6" c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[75]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhT?/ JXh4 JslackXh37=RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuM>}◿=??Q=0"9H=>>l?G>|??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh(|?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]/C JFDCEXhzr> Jclock pessimismXh0" c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[43]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh◿; J arrival timeXh罹?/ JXh4 JslackXhQ=RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuM>}◿=??Q=0"9H=>>l?G>|??z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh(|?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]/C JFDCEXhzr> Jclock pessimismXh0" c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh◿; J arrival timeXh罹?/ JXh4 JslackXhQ=RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu>}i/=?/?#1(>I "9H="[>>l?G>B?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh"[> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh(|?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh_?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]/C JFDCEXhzr> Jclock pessimismXhI " c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[81]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXh?/ JXh4 JslackXh#1(>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[88]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu>}i/=?/?#1(>I "9H="[>>l?G>B?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh"[> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[88]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh(|?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh_?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[88]/C JFDCEXhzr> Jclock pessimismXhI " c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[88]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXh?/ JXh4 JslackXh#1(>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu>}i/=?/?#1(>I "9H="[>>l?G>B?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh"[> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh(|?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh_?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/C JFDCEXhzr> Jclock pessimismXhI " c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXh?/ JXh4 JslackXh#1(>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[98]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsu>}i/=?/?#1(>I "9H="[>>l?G>B?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh"[> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[98]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh(|?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh_?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[98]/C JFDCEXhzr> Jclock pessimismXhI " c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[98]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXh?/ JXh4 JslackXh#1(>1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuz@}AΊ0A֣(|7@֣(@A=А=V^@V>%>@I??}?5?*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhXi@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_H6LUT_SLICEL_I0_O JLUT3XhzfFs> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xht@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhΊ0A; J arrival timeXh/ JXh4 JslackXhV^@ 2g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuz@}AΊ0A֣(|7@֣(@A=А=V^@V>%>@I??}?5?*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhXi@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_H6LUT_SLICEL_I0_O JLUT3XhzfFs> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xht@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhΊ0A; J arrival timeXh/ JXh4 JslackXhV^@ 1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuz@}AΊ0A֣(|7@֣(@A=А=V^@V>%>@I??}?5?*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhXi@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_H6LUT_SLICEL_I0_O JLUT3XhzfFs> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xht@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhΊ0A; J arrival timeXh/ JXh4 JslackXhV^@ 1g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuz@}AΊ0A֣(|7@֣(@A=А=V^@V>%>@I??}?5?*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhXi@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_H6LUT_SLICEL_I0_O JLUT3XhzfFs> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xht@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhΊ0A; J arrival timeXh/ JXh4 JslackXhV^@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuef@}Aa0A$)σ|7@$)@A=А=Cn@V>%>V@I??}?5?K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhXi@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_H6LUT_SLICEL_I0_O JLUT3XhzfFs> @p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXha0A; J arrival timeXh$/ JXh4 JslackXhCn@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuef@}Aa0A$)σ|7@$)@A=А=Cn@V>%>V@I??}?5?K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhXi@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_H6LUT_SLICEL_I0_O JLUT3XhzfFs> @p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXha0A; J arrival timeXh$/ JXh4 JslackXhCn@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuef@}Aa0A$)σ|7@$)@A=А=Cn@V>%>V@I??}?5?K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhXi@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_H6LUT_SLICEL_I0_O JLUT3XhzfFs> @p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXha0A; J arrival timeXh$/ JXh4 JslackXhCn@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuef@}Aa0A$)σ|7@$)@A=А=Cn@V>%>V@I??}?5?K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhXi@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_H6LUT_SLICEL_I0_O JLUT3XhzfFs> @p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXha0A; J arrival timeXh$/ JXh4 JslackXhCn@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuz@}A00Aa(1|7@a(@A=А=n@V>%>@I??}?5?> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhXi@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_H6LUT_SLICEL_I0_O JLUT3XhzfFs> @p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh00A; J arrival timeXh/ JXh4 JslackXhn@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR"#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1*X1Y32#RCLK_BRAM_L_X30Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_30 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_30 rise@0.000nsuz@}A00Aa(1|7@a(@A=А=n@V>%>@I??}?5?> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_30 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_30!gtwiz_userclk_rx_srcclk_out[0]_30#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhXi@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1/OProp_H6LUT_SLICEL_I0_O JLUT3XhzfFs> @p >:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhI@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_30 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C JFDCEXhzr> Jclock pessimismXhV>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh00A; J arrival timeXh/ JXh4 JslackXhn@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31!)y@1y @9Ay@Iy @e(@hq}v">d rise - rise rise - rise  RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[37]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu~j>}je;=n?e;?v">#9H=Q8>%>&?>$F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhQ8> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[37]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƛ?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[37]/C JFDCEXhzr> Jclock pessimismXh# c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[37]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhw?/ JXh4 JslackXhv">RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[38]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu~j>}je;=n?e;?v">#9H=Q8>%>&?>$F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhQ8> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[38]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƛ?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[38]/C JFDCEXhzr> Jclock pessimismXh# c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[38]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhw?/ JXh4 JslackXhv">RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[39]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu~j>}je;=n?e;?v">#9H=Q8>%>&?>$F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhQ8> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[39]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƛ?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[39]/C JFDCEXhzr> Jclock pessimismXh# c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[39]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhj; J arrival timeXhw?/ JXh4 JslackXhv">RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cuqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsugm>}Ŭ|f=n?|?#>#9H=Zd;>%>&?>F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZd;> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1?X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]/C JFDCEXhzr> Jclock pessimismXh# qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[0]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhŬ; J arrival timeXh ?/ JXh4 JslackXh#>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cuqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsugm>}Ŭ|f=n?|?#>#9H=Zd;>%>&?>F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZd;> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1?X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]/C JFDCEXhzr> Jclock pessimismXh# qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[1]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhŬ; J arrival timeXh ?/ JXh4 JslackXh#>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cuqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsugm>}Ŭ|f=n?|?#>#9H=Zd;>%>&?>F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZd;> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1?X1Y3 (CLOCK_ROOT) sog_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]/C JFDCEXhzr> Jclock pessimismXh# qmg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbRegMan_proc.cnter_reg[2]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhŬ; J arrival timeXh ?/ JXh4 JslackXh#>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsugm>}Ŭ|f=n?|?#>#9H=Zd;>%>&?>F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZd;> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh1?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]/C JFDCEXhzr> Jclock pessimismXh# c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[31]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhŬ; J arrival timeXh ?/ JXh4 JslackXh#>d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu>}7|>=w?|?.>j#D=(\>%>G!?>F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh(\> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh1?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXhj# g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh7; J arrival timeXhsh?/ JXh4 JslackXh.>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu>}7|>=w?|?.>j#D=(\>%>G!?>F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh(\> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh1?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXhj# g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh7; J arrival timeXhsh?/ JXh4 JslackXh.>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu>}7|>=w?|?.>j#D=(\>%>G!?>F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEL_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh(\> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh1?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXhj# g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh7; J arrival timeXhsh?/ JXh4 JslackXh.>Rg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu"ۅ@}A0A8) Q8@8)@A=А=(@X>k>|@CK??5?b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf5^= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)Xhx@X1Y3 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh(@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuˡ@}A0Ax)a&Q8@x)@A=А=U@X>k>C|@CK??5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf5^= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)Xhrh@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhU@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuˡ@}A0Ax)a&Q8@x)@A=А=U@X>k>C|@CK??5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf5^= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)Xhrh@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhU@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuƃ@}A0AJ *d6Q8@J *@A=А=@X>k>x@CK??5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf5^= @?x FBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuأ@}A0A*u&Q8@*@A=А= @X>K>5^j@CK??5?K7?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh}?=@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28/OProp_B6LUT_SLICEL_I0_O JLUT2XhzfA`> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xhz4? TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhI @X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsuأ@}A0A*u&Q8@*@A=А= @X>K>5^j@CK??5?K7?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh}?=@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28/OProp_B6LUT_SLICEL_I0_O JLUT2XhzfA`> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xhz4? YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhI @X1Y3 (CLOCK_ROOT) WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh @  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu |@}Ae1An*aQ8@n*@A=А=ы@X>k>m@CK??5?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf5^= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)Xh5^@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhe1A; J arrival timeXh~/ JXh4 JslackXhы@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu |@}Ae1An*aQ8@n*@A=А=ы@X>k>m@CK??5?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf5^= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)Xh5^@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhe1A; J arrival timeXh~/ JXh4 JslackXhы@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu |@}Ae1An*aQ8@n*@A=А=ы@X>k>m@CK??5?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf5^= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)Xh5^@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhe1A; J arrival timeXh~/ JXh4 JslackXhы@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR"$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT*X1Y32$RCLK_CLEL_R_L_X29Y269/CLK_VDISTR_BOT:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_31 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_31 rise@0.000nsu |@}Ae1An*aQ8@n*@A=А=ы@X>k>m@CK??5?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_31 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_31!gtwiz_userclk_rx_srcclk_out[0]_31#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhI@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzf5^= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_31 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[2].gbtbank/CLK Jnet (fo=674, routed)Xh5^@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C JFDCEXhzr> Jclock pessimismXhX>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhe1A; J arrival timeXh~/ JXh4 JslackXhы@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32!)y@1y @9Ay@Iy @eʥ@hq}.=d rise - rise rise - rise  73SFP_GEN[30].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu]B>}H=.}??.=cD=rh>j>?/>S?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) 73SFP_GEN[30].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[30].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhrh>c 1-SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[30].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh`?X1Y3 (CLOCK_ROOT)i 73SFP_GEN[30].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[30].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)a /+SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXhcz -)SFP_GEN[30].ngCCM_gbt/RX_Word_rx40_reg[2]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhH; J arrival timeXh+?/ JXh4 JslackXh.=4d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuD`e>}iq==@5~?q=?>9H=433>j>M?/>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh433> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh`?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhȆ?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXhƛ?/ JXh4 JslackXh>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuD`e>}iq==@5~?q=?>9H=433>j>M?/>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh433> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh`?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhȆ?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXhƛ?/ JXh4 JslackXh>RRNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsǔ>}+jq==v~?q=?i#P>9H=lg>j>\?/>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhlg> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh`?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhȆ?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh+j; J arrival timeXhn?/ JXh4 JslackXhi#P>d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu>}rCGB=@5~?C?Xs`>9H=>j>M?/>&!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh`?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh·?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhr; J arrival timeXh?/ JXh4 JslackXhXs`>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu>}rCGB=@5~?C?Xs`>9H=>j>M?/>&!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh`?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh·?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhr; J arrival timeXh?/ JXh4 JslackXhXs`>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu>}rCGB=@5~?C?Xs`>9H=>j>M?/>&!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh`?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh·?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhr; J arrival timeXh?/ JXh4 JslackXhXs`>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu>}i0 )=@5~? ?~a>̫9H=>j>M?/> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh`?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhP?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh̫ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi0; J arrival timeXhB`?/ JXh4 JslackXh~a>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu>}i0 )=@5~? ?~a>̫9H=>j>M?/> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh`?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhP?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh̫ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi0; J arrival timeXhB`?/ JXh4 JslackXh~a>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu>}i0 )=@5~? ?~a>̫9H=>j>M?/> ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh`?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhP?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh̫ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi0; J arrival timeXhB`?/ JXh4 JslackXh~a>R/g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu1,@}A|+AޣV6@@A=А=ʥ@cN>~j>B`@ʡE?t?sh1?%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh^?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/C JFDCEXhzr> Jclock pessimismXhcN>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh|+A; J arrival timeXh// JXh4 JslackXhʥ@ 0g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu1,@}A|+AޣV6@@A=А=ʥ@cN>~j>B`@ʡE?t?sh1?%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh^?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/C JFDCEXhzr> Jclock pessimismXhcN>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh|+A; J arrival timeXh// JXh4 JslackXhʥ@ /g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu1,@}A|+AޣV6@@A=А=ʥ@cN>~j>B`@ʡE?t?sh1?%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh^?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr> Jclock pessimismXhcN>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh|+A; J arrival timeXh// JXh4 JslackXhʥ@ /g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu1,@}A|+AޣV6@@A=А=ʥ@cN>~j>B`@ʡE?t?sh1?%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh^?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/C JFDCEXhzr> Jclock pessimismXhcN>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh|+A; J arrival timeXh// JXh4 JslackXhʥ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuC+@}Aސ+A}?VV6@}?@A=А=T@CN>~j>@ʡE?t?sh1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh5^?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/C JFDCEXhzr> Jclock pessimismXhCN>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhސ+A; J arrival timeXh̰/ JXh4 JslackXhT@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuC+@}Aސ+A}?VV6@}?@A=А=T@CN>~j>@ʡE?t?sh1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh5^?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/C JFDCEXhzr> Jclock pessimismXhCN>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhސ+A; J arrival timeXh̰/ JXh4 JslackXhT@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuC+@}Aސ+A}?VV6@}?@A=А=T@CN>~j>@ʡE?t?sh1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh5^?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/C JFDCEXhzr> Jclock pessimismXhCN>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhސ+A; J arrival timeXh̰/ JXh4 JslackXhT@ 0g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsuC+@}Aސ+A}?VV6@}?@A=А=T@CN>~j>@ʡE?t?sh1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh5^?X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/C JFDCEXhzr> Jclock pessimismXhCN>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhސ+A; J arrival timeXh̰/ JXh4 JslackXhT@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu|'@}Aj+ATDV6@T@A=А=Z@ N>~j>@ʡE?t?sh1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/C JFDCEXhzr> Jclock pessimismXh N>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhj+A; J arrival timeXhy/ JXh4 JslackXhZ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT0:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_32 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_32 rise@0.000nsu|'@}Aj+ATDV6@T@A=А=Z@ N>~j>@ʡE?t?sh1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_32 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_32!gtwiz_userclk_rx_srcclk_out[0]_32#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfQ= @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_32 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C JFDCEXhzr> Jclock pessimismXh N>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhj+A; J arrival timeXhy/ JXh4 JslackXhZ@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33!)y@1y @9Ay@Iy @ek@hq}>d rise - rise rise - rise  RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[102]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuQ8>}kٖwM)=I ?w?>GL9H=$>>'? >r=J?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh$> hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[102]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh33?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhI?X1Y3 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[102]/C JFDCEXhzr> Jclock pessimismXhGL d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[102]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhkٖ; J arrival timeXh?/ JXh4 JslackXh>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[111]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuZ>}DİxDL=I ?İ?!>sB9H='>>'? >IL?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh'> hdg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[111]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh33?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhO?X1Y3 (CLOCK_ROOT) fbg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[111]/C JFDCEXhzr> Jclock pessimismXhsB d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[111]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhD; J arrival timeXhO?/ JXh4 JslackXh!>d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuˡ>}Vy~=n??9>L D=Z>>:(? >J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhD?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXhL  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhV; J arrival timeXh ׳?/ JXh4 JslackXh9>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuˡ>}Vy~=n??9>L D=Z>>:(? >J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhD?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXhL  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhV; J arrival timeXh ׳?/ JXh4 JslackXh9>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuˡ>}Vy~=n??9>L D=Z>>:(? >J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y3 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhD?X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXhL  g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhV; J arrival timeXh ׳?/ JXh4 JslackXh9>RRNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[60]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuo>}NR=I ?R?\<>yk 9H=S>>'? >'1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[60]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh33?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[60]/C JFDCEXhzr> Jclock pessimismXhyk  c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[60]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhN; J arrival timeXhв?/ JXh4 JslackXh\<>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[63]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuo>}NR=I ?R?\<>yk 9H=S>>'? >'1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[63]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh33?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[63]/C JFDCEXhzr> Jclock pessimismXhyk  c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[63]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhN; J arrival timeXhв?/ JXh4 JslackXh\<>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[68]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuo>}NR=I ?R?\<>yk 9H=S>>'? >'1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[68]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh33?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[68]/C JFDCEXhzr> Jclock pessimismXhyk  c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[68]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhN; J arrival timeXhв?/ JXh4 JslackXh\<>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[72]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuo>}NR=I ?R?\<>yk 9H=S>>'? >'1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[72]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh33?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[72]/C JFDCEXhzr> Jclock pessimismXhyk  c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg0_reg[72]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhN; J arrival timeXhв?/ JXh4 JslackXh\<>RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[60]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZj_gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuo>}NR=I ?R?\<>yk 9H=S>>'? >'1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[60]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh33?X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X1Y3 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[60]/C JFDCEXhzr> Jclock pessimismXhyk  c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/reg1_reg[60]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhN; J arrival timeXhв?/ JXh4 JslackXh\<>g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu p@}A(0An*=5@n*@A=А=k@lU>Cl>Xa@ffF?th?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1<@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__30/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__30/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzfj= WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh~?? TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh5^@X1Y3 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhlU>@ Jclock uncertaintyXh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh(0A; J arrival timeXh/ JXh4 JslackXhk@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu p@}A(0An*=5@n*@A=А=k@lU>Cl>Xa@ffF?th?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh1<@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__30/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__30/OProp_D6LUT_SLICEM_I0_O JLUT2Xhzfj= WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh~?? YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh5^@X1Y3 (CLOCK_ROOT) WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhlU>@ Jclock uncertaintyXh UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh(0A; J arrival timeXh/ JXh4 JslackXhk@ ,g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu`@}A0A5^*O =5@5^*@A=А=N@lU>X>I@ffF?th?n2?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhm#@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C JFDCEXhzr> Jclock pessimismXhlU>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh"/ JXh4 JslackXhN@ -g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu`@}A0A5^*O =5@5^*@A=А=N@lU>X>I@ffF?th?n2?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhm#@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/C JFDCEXhzr> Jclock pessimismXhlU>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh"/ JXh4 JslackXhN@ ,g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu`@}A0A5^*O =5@5^*@A=А=N@lU>X>I@ffF?th?n2?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhm#@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/C JFDCEXhzr> Jclock pessimismXhlU>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh"/ JXh4 JslackXhN@ ,g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsu`@}A0A5^*O =5@5^*@A=А=N@lU>X>I@ffF?th?n2?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhm#@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/C JFDCEXhzr> Jclock pessimismXhlU>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh"/ JXh4 JslackXhN@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsux^@}A(0An*=5@n*@A=А=@lU>X>wG@ffF?th?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhm#@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 Jnet (fo=674, routed)Xh5^@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/C JFDCEXhzr> Jclock pessimismXhlU>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh(0A; J arrival timeXh?5/ JXh4 JslackXh@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsux^@}A(0An*=5@n*@A=А=@lU>X>wG@ffF?th?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhm#@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 Jnet (fo=674, routed)Xh5^@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C JFDCEXhzr> Jclock pessimismXhlU>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh(0A; J arrival timeXh?5/ JXh4 JslackXh@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsux^@}A(0An*=5@n*@A=А=@lU>X>wG@ffF?th?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhm#@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 Jnet (fo=674, routed)Xh5^@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/C JFDCEXhzr> Jclock pessimismXhlU>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh(0A; J arrival timeXh?5/ JXh4 JslackXh@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR""RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1*X1Y32"RCLK_DSP_L_X27Y269/CLK_VDISTR_BOT1:X1Y3BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_33 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_33 rise@0.000nsuE^@}A0AM*=5@M*@A=А=@lU>X>G@ffF?th?n2?C?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_33 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_33!gtwiz_userclk_rx_srcclk_out[0]_33#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhm#@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhM@X1Y3 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_33 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4 Jnet (fo=674, routed)Xhq=@X1Y3 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C JFDCEXhzr> Jclock pessimismXhlU>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhT/ JXh4 JslackXh@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34!)y@1y @9Ay@Iy @e@hq}=d rise - rise rise - rise  73SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsudI>}9As=|??={D=u>H>Z?>o#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) 73SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[32].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhu>d 2.SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhb?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXh{{ .*SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[36]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh9; J arrival timeXh?/ JXh4 JslackXh=473SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsudI>}9As=|??={D=u>H>Z?>o#?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) 73SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[32].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhu>d 2.SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhb?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr> Jclock pessimismXh{| .*SFP_GEN[32].ngCCM_gbt/RX_Word_rx40_reg[38]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh9; J arrival timeXh?/ JXh4 JslackXh=473SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[32].ngCCM_gbt/pwr_good_pre_reg/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu>}0~ =|?~?C>D=@5^>H>Z?>&!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) 73SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[32].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@5^>` .*SFP_GEN[32].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[32].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[32].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh> ?X1Y4 (CLOCK_ROOT)^ ,(SFP_GEN[32].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhw *&SFP_GEN[32].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh0; J arrival timeXh?/ JXh4 JslackXhC>4RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsǔ>}O)=.}??E>P9H=lg>H>]?>G!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xhlg> gcg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh`?X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh+?X1Y4 (CLOCK_ROOT) eag_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXhP c_g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhO; J arrival timeXhJ ?/ JXh4 JslackXhE>d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu>}5~X=ʁ?~?N>f9H=bX>H>r?>&!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhbX> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhTe?X1Y4 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh> ?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXhf g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh5; J arrival timeXho?/ JXh4 JslackXhN>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu>}5~X=ʁ?~?N>f9H=bX>H>r?>&!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhbX> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhTe?X1Y4 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh> ?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXhf g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh5; J arrival timeXho?/ JXh4 JslackXhN>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu>}5~X=ʁ?~?N>f9H=bX>H>r?>&!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhbX> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhTe?X1Y4 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh> ?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXhf g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh5; J arrival timeXho?/ JXh4 JslackXhN>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu>}5~X=ʁ?~?N>f9H=bX>H>r?>&!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhbX> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhTe?X1Y4 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh> ?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXhf g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh5; J arrival timeXho?/ JXh4 JslackXhN>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu>}5~X=ʁ?~?N>f9H=bX>H>r?>&!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhbX> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhTe?X1Y4 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh> ?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXhf g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh5; J arrival timeXho?/ JXh4 JslackXhN>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu>}5~X=ʁ?~?N>f9H=bX>H>r?>&!?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhbX> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhTe?X1Y4 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh> ?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXhf g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh5; J arrival timeXho?/ JXh4 JslackXhN>R g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuD<@}A+A}?*w7@}?@A=А=@W}N>>M*@oC?P?/?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhV? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh5^?X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/C JFDCEXhzr> Jclock pessimismXhW}N>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh$/ JXh4 JslackXh@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsuD<@}A+A}?*w7@}?@A=А=@W}N>>M*@oC?P?/?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhV? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh5^?X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/C JFDCEXhzr> Jclock pessimismXhW}N>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh$/ JXh4 JslackXh@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsum;@}AƇ+Aw7@@A=А=<@N>>)@oC?P?/?[?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhV? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhƇ+A; J arrival timeXhҹ/ JXh4 JslackXh<@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsum;@}AƇ+Aw7@@A=А=<@N>>)@oC?P?/?[?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhV? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhƇ+A; J arrival timeXhҹ/ JXh4 JslackXh<@ 8g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu3@}A+A}?*w7@}?@A=А=m@W}N>>rh!@oC?P?/?Т?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhV? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh5^?X1Y4 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/C JFDCEXhzr> Jclock pessimismXhW}N>@ Jclock uncertaintyXh EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh./ JXh4 JslackXhm@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu333@}AƇ+Aw7@@A=А=@N>> @oC?P?/?[?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhV? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhƇ+A; J arrival timeXhx/ JXh4 JslackXh@  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu333@}AƇ+Aw7@@A=А=@N>> @oC?P?/?[?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhV? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhƇ+A; J arrival timeXhx/ JXh4 JslackXh@ -g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu333@}AƇ+Aw7@@A=А=@N>> @oC?P?/?[?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhV? g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5 Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)v D@g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh B>g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhƇ+A; J arrival timeXhx/ JXh4 JslackXh@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu2,@}As+AsEw7@@A=А=@N>n>^@oC?P?/??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhu? fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf+> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh? TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhs+A; J arrival timeXhU/ JXh4 JslackXh@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR""RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1*X1Y42"RCLK_DSP_L_X27Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_34 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_34 rise@0.000nsu2,@}As+AsEw7@@A=А=@N>n>^@oC?P?/??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_34 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_34!gtwiz_userclk_rx_srcclk_out[0]_34#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhu? fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf+> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh? YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_34 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhx?X1Y4 (CLOCK_ROOT) WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhs+A; J arrival timeXhU/ JXh4 JslackXh@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35!)y@1y @9Ay@Iy @eK‰@hq}=d rise - rise rise - rise  73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuM>}iNb~=?Nb?=ED=>v>(?R>~J?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh>d 2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXhE{ .*SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[32]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXh?/ JXh4 JslackXh=473SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuM>}iNb~=?Nb?=ED=>v>(?R>~J?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh>d 2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXhE| .*SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[34]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXh?/ JXh4 JslackXh=473SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuM>}iNb~=?Nb?=ED=>v>(?R>~J?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh>d 2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXhE{ .*SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[36]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXh?/ JXh4 JslackXh=473SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuM>}iNb~=?Nb?=ED=>v>(?R>~J?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh>d 2.SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)b 0,SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr> Jclock pessimismXhE| .*SFP_GEN[33].ngCCM_gbt/RX_Word_rx40_reg[38]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhi; J arrival timeXh?/ JXh4 JslackXh=4d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsux>}<ƨ=I ??R>R9H=F>v>+'?R>J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhF> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X1Y4 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXhR g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh<; J arrival timeXh&?/ JXh4 JslackXhR>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsux>}<ƨ=I ??R>R9H=F>v>+'?R>J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhF> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X1Y4 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXhR g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh<; J arrival timeXh&?/ JXh4 JslackXhR>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsux>}<ƨ=I ??R>R9H=F>v>+'?R>J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhF> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X1Y4 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXhR g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh<; J arrival timeXh&?/ JXh4 JslackXhR>R73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuSc>}2%3=?%?P1>nCD=-2>v>(?R>K?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[33].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh-2>` .*SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y4 (CLOCK_ROOT)i 73SFP_GEN[33].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[33].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhi?X1Y4 (CLOCK_ROOT)^ ,(SFP_GEN[33].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhnCw *&SFP_GEN[33].ngCCM_gbt/pwr_good_pre_regRemov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh2; J arrival timeXh*\?/ JXh4 JslackXhP1>4d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuI>}3|X:=I ?|?WG>g9H=fff>v>+'?R>9H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhfff> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X1Y4 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh1?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXhg g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh3; J arrival timeXh?/ JXh4 JslackXhWG>Rd`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZj_gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuI>}3|X:=I ?|?WG>g9H=fff>v>+'?R>9H?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35(DCD - SCD - CPR) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhfff> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh33?X1Y4 (CLOCK_ROOT) d`g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh1?X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXhg g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh3; J arrival timeXh?/ JXh4 JslackXhWG>Rg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuJ z@}Ae1A*YU<6@*@A=А=K‰@ X>>g@yF?F?-2?I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh 0@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/C JFDCEXhzr> Jclock pessimismXh X>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhe1A; J arrival timeXhj/ JXh4 JslackXhK‰@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuJ z@}Ae1A*YU<6@*@A=А=K‰@ X>>g@yF?F?-2?I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh 0@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)Xh @X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/C JFDCEXhzr> Jclock pessimismXh X>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhe1A; J arrival timeXhj/ JXh4 JslackXhK‰@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuy@}A41A*<6@*@A=А=A@ X>>(\g@yF?F?-2?2?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh 0@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)Xh\@X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/C JFDCEXhzr> Jclock pessimismXh X>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh41A; J arrival timeXh'1/ JXh4 JslackXhA@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuy@}A41A*<6@*@A=А=A@ X>>(\g@yF?F?-2?2?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh 0@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)Xh\@X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/C JFDCEXhzr> Jclock pessimismXh X>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh41A; J arrival timeXh'1/ JXh4 JslackXhA@ :g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuv@}A41A*<6@*@A=А=K@ X>>d@yF?F?-2?2?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh 0@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)Xh\@X1Y4 (CLOCK_ROOT)y GCg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/C JFDCEXhzr> Jclock pessimismXh X>@ Jclock uncertaintyXh EAg_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh41A; J arrival timeXh/ JXh4 JslackXhK@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuv@}A41A*<6@*@A=А=K@ X>>d@yF?F?-2?2?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh 0@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)Xh\@X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/C JFDCEXhzr> Jclock pessimismXh X>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh41A; J arrival timeXh/ JXh4 JslackXhK@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuOo@}A0AM*<6@M*@A=А=pȎ@ X>X>NbX@yF?F?-2?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xht8@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32/OProp_D6LUT_SLICEL_I0_O JLUT2XhzfZd> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xhv> TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhq=@X1Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh X>@ Jclock uncertaintyXh PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh+/ JXh4 JslackXhpȎ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsuOo@}A0AM*<6@M*@A=А=pȎ@ X>X>NbX@yF?F?-2?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xht8@ fbg_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32/I0 JXhzr eag_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32/OProp_D6LUT_SLICEL_I0_O JLUT2XhzfZd> WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xhv> YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhq=@X1Y4 (CLOCK_ROOT) WSg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh X>@ Jclock uncertaintyXh UQg_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh+/ JXh4 JslackXhpȎ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsulg@}A>0A)L4<6@)@A=А=ܯ@ X>>/U@yF?F?-2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh 0@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/C JFDCEXhzr> Jclock pessimismXh X>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh>0A; J arrival timeXh/ JXh4 JslackXhܯ@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR"#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1*X1Y42#RCLK_BRAM_L_X30Y329/CLK_VDISTR_BOT1:X1Y4BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_35 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_35 rise@0.000nsulg@}A>0A)L4<6@)@A=А=ܯ@ X>>/U@yF?F?-2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_35 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_35!gtwiz_userclk_rx_srcclk_out[0]_35#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh 0@ g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/I0 JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)Xhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_35 rise edge)XhzrA g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> A=g_gbt_bank[2].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6 Jnet (fo=674, routed)Xh@X1Y4 (CLOCK_ROOT)n <8g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/C JFDCEXhzr> Jclock pessimismXh X>@ Jclock uncertaintyXh :6g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh>0A; J arrival timeXh/ JXh4 JslackXhܯ@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36!)y@1y @9Ay@Iy @eW@hq}s=d rise - rise rise - rise  73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu:A>}pAXa=%?A?s=y#D=Nb>%> #?>)1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhNb>d 2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh̜?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXhy#{ .*SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[32]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXhL7?/ JXh4 JslackXhs=473SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu:A>}pAXa=%?A?s=y#D=Nb>%> #?>)1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhNb>d 2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh̜?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXhy#| .*SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[34]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXhL7?/ JXh4 JslackXhs=473SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu:A>}pAXa=%?A?s=y#D=Nb>%> #?>)1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhNb>d 2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh̜?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXhy#{ .*SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[36]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXhL7?/ JXh4 JslackXhs=473SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu:A>}pAXa=%?A?s=y#D=Nb>%> #?>)1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhNb>d 2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh̜?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr> Jclock pessimismXhy#| .*SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[38]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhp; J arrival timeXhL7?/ JXh4 JslackXhs=473SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuJs>}Ӝף=%?ף?AO><#D=\B>%> #?>H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh\B>d 2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[24]/C JFDCEXhzr> Jclock pessimismXh<#{ .*SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[24]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhӜ; J arrival timeXh|?/ JXh4 JslackXhAO>473SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuJs>}Ӝף=%?ף?AO><#D=\B>%> #?>H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh\B>d 2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzr> Jclock pessimismXh<#| .*SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[25]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhӜ; J arrival timeXh|?/ JXh4 JslackXhAO>473SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuJs>}Ӝף=%?ף?AO><#D=\B>%> #?>H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh\B>d 2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[26]/C JFDCEXhzr> Jclock pessimismXh<#{ .*SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[26]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhӜ; J arrival timeXh|?/ JXh4 JslackXhAO>473SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuJs>}Ӝף=%?ף?AO><#D=\B>%> #?>H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh\B>d 2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzr> Jclock pessimismXh<#| .*SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[27]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhӜ; J arrival timeXh|?/ JXh4 JslackXhAO>473SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuJs>}Ӝף=%?ף?AO><#D=\B>%> #?>H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh\B>d 2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXh<#{ .*SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[28]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhӜ; J arrival timeXh|?/ JXh4 JslackXhAO>473SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuJs>}Ӝף=%?ף?AO><#D=\B>%> #?>H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36(DCD - SCD - CPR) 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[36].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh\B>d 2.SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh-?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[36].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[36].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[29]/C JFDCEXhzr> Jclock pessimismXh<#| .*SFP_GEN[36].ngCCM_gbt/RX_Word_rx40_reg[29]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhӜ; J arrival timeXh|?/ JXh4 JslackXhAO>4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu+@}Ay+AV1ܰ89@V@A=А=W@zQ>>@CK?? ?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh:@ fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__35/I0 JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__35/OProp_A6LUT_SLICEM_I0_O JLUT2Xhzfx> WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 Jnet (fo=2, routed)XhP? TPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhC?X1Y7 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhzQ>@ Jclock uncertaintyXh PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhy+A; J arrival timeXh/ JXh4 JslackXhW@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu+@}Ay+AV1ܰ89@V@A=А=W@zQ>>@CK?? ?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh:@ fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__35/I0 JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__35/OProp_A6LUT_SLICEM_I0_O JLUT2Xhzfx> WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_1 Jnet (fo=2, routed)XhP? YUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhC?X1Y7 (CLOCK_ROOT) WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhzQ>@ Jclock uncertaintyXh UQg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhy+A; J arrival timeXh/ JXh4 JslackXhW@ 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsun@}A0A&)W589@&)@A=А=ed|@ϺX>>~jt@CK?? ?5?K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^:@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfx> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh33/ JXh4 JslackXhed|@ 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsun@}A0A&)W589@&)@A=А=ed|@ϺX>>~jt@CK?? ?5?K?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^:@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfx> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh33/ JXh4 JslackXhed|@ 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu:o@}A0A^)@89@^)@A=А=@ϺX>>lW@CK?? ?5?r?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^:@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfx> @x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh9/ JXh4 JslackXh@ 'g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuo@}A0A) 89@)@A=А=@ϺX>>|W@CK?? ?5?t?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^:@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfx> @x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^@X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhj/ JXh4 JslackXh@ (g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuo@}A0A) 89@)@A=А=@ϺX>>|W@CK?? ?5?t?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^:@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfx> @x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh^@X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhj/ JXh4 JslackXh@ (g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsu:o@}A0A^)@89@^)@A=А=@ϺX>>lW@CK?? ?5?r?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^:@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfx> @x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]Recov_AFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh9/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuKo@}Ax0A)89@)@A=А=q<@ϺX>>V@CK?? ?5?Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh5^:@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2/OProp_B6LUT_SLICEM_I0_O JLUT3Xhzfx> @p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 84g_gbt_bank[3].gbtbank/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/C JFDCEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhx0A; J arrival timeXhj/ JXh4 JslackXhq<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Cd`g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/shiftPsAddr_reg_inv/PRE"$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT*X1Y72$RCLK_CLEL_R_L_X29Y509/CLK_VDISTR_BOT:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_36 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_36 rise@0.000nsuZl@}A0A)989@)@A=А=k@ϺX>V>tc@CK?? ?5?+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_36 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_36!gtwiz_userclk_rx_srcclk_out[0]_36#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> \Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/bitslip_reset_0 Jnet (fo=32, routed)Xhtc@ d`g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/shiftPsAddr_reg_inv/PRE JFDPEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_36 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/CLK Jnet (fo=674, routed)Xh%@X1Y7 (CLOCK_ROOT) b^g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/shiftPsAddr_reg_inv/C JFDPEXhzr> Jclock pessimismXhϺX>@ Jclock uncertaintyXh `\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].patternSearch/shiftPsAddr_reg_invRecov_DFF_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhk@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37!)y@1y @9Ay@Iy @e'@hq}f>d rise - rise rise - rise  eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuS>}Eݫ 4=%? ?f>:'9H=ˡ>V>-?+?-R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhˡ> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh:' g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhEݫ; J arrival timeXh:?/ JXh4 JslackXhf>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuS>}Eݫ 4=%? ?f>:'9H=ˡ>V>-?+?-R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhˡ> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh:' g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhEݫ; J arrival timeXh:?/ JXh4 JslackXhf>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuS>}Eݫ 4=%? ?f>:'9H=ˡ>V>-?+?-R?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhˡ> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXh:' g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhEݫ; J arrival timeXh:?/ JXh4 JslackXhf>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuA5>}<߿v=%?<߿?g>?'9H=>V>-?+?Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXh?' g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhu?/ JXh4 JslackXhg>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuA5>}<߿v=%?<߿?g>?'9H=>V>-?+?Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXh?' g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhu?/ JXh4 JslackXhg>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuA5>}<߿v=%?<߿?g>?'9H=>V>-?+?Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh?' g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhu?/ JXh4 JslackXhg>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuA5>}<߿v=%?<߿?g>?'9H=>V>-?+?Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXh?' g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhu?/ JXh4 JslackXhg>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuG>}<߿v=%?<߿?m>?'9H='1>V>-?+?Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh'1> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh?' g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhX?/ JXh4 JslackXhm>RSOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsur>}cף`I=?ף?!}>'9H=)\>V>/?+?43S?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh)\> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xho?X1Y8 (CLOCK_ROOT) SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/?X1Y8 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh' d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhc; J arrival timeXh2?/ JXh4 JslackXh!}>eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsu?>}aףz=%?ף?yч>:0'9H=(>V>-?+?43S?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh(> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[10].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXh:0' g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[10].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXha; J arrival timeXhV?/ JXh4 JslackXhyч>R\g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CKGg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuO@}A 4AO=rK@O=@A=А='@>~j>X9@5^?+?l{?C?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%i@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh?} KGg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhr0@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh}?%@X1Y8 (CLOCK_ROOT){ IEg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh 4A; J arrival timeXh / JXh4 JslackXh'@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@~j>!@5^?+?l{??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%i@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh:?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhr0@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)XhT%@X1Y8 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh4A; J arrival timeXh / JXh4 JslackXh+@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@~j>!@5^?+?l{??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%i@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh:?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhr0@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)XhT%@X1Y8 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh4A; J arrival timeXh / JXh4 JslackXh+@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@~j>!@5^?+?l{??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%i@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh:?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhr0@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)XhT%@X1Y8 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh4A; J arrival timeXh / JXh4 JslackXh+@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@~j>!@5^?+?l{??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%i@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xh:?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhr0@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)XhT%@X1Y8 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh4A; J arrival timeXh / JXh4 JslackXh+@ Pg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuh@}Ad6A'1@@H=K@'1@@A=А=,@Ri>~j>q=@5^?+?l{?M?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%i@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhy?z HDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhr0@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh (@X1Y8 (CLOCK_ROOT)x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/C JFDCEXhzr> Jclock pessimismXhRi>@ Jclock uncertaintyXh D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhd6A; J arrival timeXh- / JXh4 JslackXh,@ Pg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuh@}Ad6A'1@@H=K@'1@@A=А=,@Ri>~j>q=@5^?+?l{?M?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%i@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhy?z HDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhr0@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh (@X1Y8 (CLOCK_ROOT)x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/C JFDCEXhzr> Jclock pessimismXhRi>@ Jclock uncertaintyXh D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhd6A; J arrival timeXh- / JXh4 JslackXh,@ Qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuh@}Ad6A'1@@H=K@'1@@A=А=,@Ri>~j>q=@5^?+?l{?M?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%i@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhy?z HDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhr0@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh (@X1Y8 (CLOCK_ROOT)x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/C JFDCEXhzr> Jclock pessimismXhRi>@ Jclock uncertaintyXh D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhd6A; J arrival timeXh- / JXh4 JslackXh,@ Qg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuh@}Ad6A'1@@H=K@'1@@A=А=,@Ri>~j>q=@5^?+?l{?M?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%i@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhy?z HDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhr0@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh (@X1Y8 (CLOCK_ROOT)x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/C JFDCEXhzr> Jclock pessimismXhRi>@ Jclock uncertaintyXh D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]Recov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhd6A; J arrival timeXh- / JXh4 JslackXh,@ Pg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR"$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X16Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_37 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_37 rise@0.000nsuh@}Ad6A'1@@H=K@'1@@A=А=,@Ri>~j>q=@5^?+?l{?M?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_37 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_37!gtwiz_userclk_rx_srcclk_out[0]_37#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh%i@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10]0 Jnet (fo=15, routed)Xhy?z HDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhr0@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_37 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_7[0] Jnet (fo=674, routed)Xh (@X1Y8 (CLOCK_ROOT)x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/C JFDCEXhzr> Jclock pessimismXhRi>@ Jclock uncertaintyXh D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhd6A; J arrival timeXh- / JXh4 JslackXh,@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38!)y@1y @9Ay@Iy @e?hq}I>d rise - rise rise - rise  SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuw>}/=V?/?I> 9H=ˡE>>S?G>B?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhˡE> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= D@g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh~?X1Y9 (CLOCK_ROOT) SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh_?X1Y9 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh  d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/firstOut_regRemov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhO?/ JXh4 JslackXhI> 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[47].ngCCM_gbt/pwr_good_pre_reg/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu+>}&ٮ=8?ٮ?b>:DD=/]>>%?G>$F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[47].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh/]>` .*SFP_GEN[47].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh!?X1Y9 (CLOCK_ROOT)i 73SFP_GEN[47].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[47].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZd?X1Y9 (CLOCK_ROOT)^ ,(SFP_GEN[47].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh:Dw *&SFP_GEN[47].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh&; J arrival timeXhS?/ JXh4 JslackXhb>4eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuV>}}WwD=rh?w?TNt>V 9H=̌>>/$?G>G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xȟ> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhI?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXhV  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}W; J arrival timeXhH?/ JXh4 JslackXhTNt>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuV>}}WwD=rh?w?TNt>V 9H=̌>>/$?G>G?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xȟ> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhI?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXhV  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh}W; J arrival timeXhH?/ JXh4 JslackXhTNt>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuТ>} v5 =rh?v?|~x>n 9H=_>>/$?G>B`E?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh_> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXhn  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXh?/ JXh4 JslackXh|~x>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuТ>} v5 =rh?v?|~x>n 9H=_>>/$?G>B`E?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh_> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXhn  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXh?/ JXh4 JslackXh|~x>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuТ>} v5 =rh?v?|~x>n 9H=_>>/$?G>B`E?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh_> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C JFDCEXhzr> Jclock pessimismXhn  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[19]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXh?/ JXh4 JslackXh|~x>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuТ>} v5 =rh?v?|~x>n 9H=_>>/$?G>B`E?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh_> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXhn  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXh?/ JXh4 JslackXh|~x>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuТ>} v5 =rh?v?|~x>n 9H=_>>/$?G>B`E?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh_> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXhn  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXh?/ JXh4 JslackXh|~x>Reag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsuТ>} v5 =rh?v?|~x>n 9H=_>>/$?G>B`E?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38(DCD - SCD - CPR) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh_> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= [Wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[11].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXhn  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[11].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXh?/ JXh4 JslackXh|~x>R.g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@㥛>&1@^I??4??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh}?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhU@r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhQ@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/C JFDCEXhzr> Jclock pessimismXhLU>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhg0A; J arrival timeXh / JXh4 JslackXh? .g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@㥛>&1@^I??4??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh}?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)XhU@r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhQ@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh @X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/C JFDCEXhzr> Jclock pessimismXhLU>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhg0A; J arrival timeXh / JXh4 JslackXh? .g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@㥛>@^I??4??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh}?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xhp@r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhQ@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/C JFDCEXhzr> Jclock pessimismXhLU>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhX_0A; J arrival timeXh^/ JXh4 JslackXh'? Ng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu@}AN0A'A<3@'@A=А= @LU>㥛>@^I??4??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh}?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xhl?z HDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhQ@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xhw@X1Y9 (CLOCK_ROOT)x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/C JFDCEXhzr> Jclock pessimismXhLU>@ Jclock uncertaintyXh D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhN0A; J arrival timeXhK/ JXh4 JslackXh @ Og_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu@}AN0A'A<3@'@A=А= @LU>㥛>@^I??4??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh}?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xhl?z HDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhQ@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xhw@X1Y9 (CLOCK_ROOT)x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/C JFDCEXhzr> Jclock pessimismXhLU>@ Jclock uncertaintyXh D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhN0A; J arrival timeXhK/ JXh4 JslackXh @ Ng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu@}AN0A'A<3@'@A=А= @LU>㥛>@^I??4??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh}?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xhl?z HDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhQ@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xhw@X1Y9 (CLOCK_ROOT)x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/C JFDCEXhzr> Jclock pessimismXhLU>@ Jclock uncertaintyXh D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhN0A; J arrival timeXhK/ JXh4 JslackXh @ Ng_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CHDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1*X1Y92#RCLK_BRAM_L_X30Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_38 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_38 rise@0.000nsu@}AN0A'A<3@'@A=А= @LU>㥛>@^I??4??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh}?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xhl?z HDg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhQ@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xhw@X1Y9 (CLOCK_ROOT)x FBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/C JFDCEXhzr> Jclock pessimismXhLU>@ Jclock uncertaintyXh D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhN0A; J arrival timeXhK/ JXh4 JslackXh @ .g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@㥛>$@^I??4?T?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh}?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhQ@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/C JFDCEXhzr> Jclock pessimismXhLU>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhk0A; J arrival timeXhA/ JXh4 JslackXhd@ .g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@㥛>$@^I??4?T?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh}?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhQ@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xh'1@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/C JFDCEXhzr> Jclock pessimismXhLU>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhk0A; J arrival timeXhA/ JXh4 JslackXhd@ .g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C@㥛≯@^I??4?ˡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_38 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_38!gtwiz_userclk_rx_srcclk_out[0]_38#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh}?@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11]0 Jnet (fo=15, routed)Xh@5?r @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhQ@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_38 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_8[0] Jnet (fo=674, routed)Xhc@X1Y9 (CLOCK_ROOT)p >:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/C JFDCEXhzr> Jclock pessimismXhLU>@ Jclock uncertaintyXh <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhqc0A; J arrival timeXh$/ JXh4 JslackXhN@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39!)y@1y @9Ay@Iy @eP@hq}+>d rise - rise rise - rise  73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[37].ngCCM_gbt/pwr_good_pre_reg/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsurh>}ꋌ?5P=??5?+>[iD=K7>>o?G>/$?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[37].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhK7>` .*SFP_GEN[37].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhSc?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[37].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[37].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)^ ,(SFP_GEN[37].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh[iw *&SFP_GEN[37].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhꋌ; J arrival timeXhi?/ JXh4 JslackXh+>4RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu>5^>}nƛ=أ?ƛ?>9H=1,>>S?G> ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh1,> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhc?X1Y7 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhQ?X1Y7 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhn; J arrival timeXhj?/ JXh4 JslackXh>d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu>}rĎNbP=Ђ?Nb?*> D=Y>>?G>L7)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhY> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhg?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhrĎ; J arrival timeXh?/ JXh4 JslackXh*>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu>}rĎNbP=Ђ?Nb?*> D=Y>>?G>L7)?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhY> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhg?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhrĎ; J arrival timeXh?/ JXh4 JslackXh*>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu9>}8j8=Ђ??O>8,4D=Q>>?G>&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhQ> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhg?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh䥋?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzr> Jclock pessimismXh8,4 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh8; J arrival timeXh43?/ JXh4 JslackXhO>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu9>}8j8=Ђ??O>8,4D=Q>>?G>&?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhQ> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhg?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh䥋?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh8,4 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh8; J arrival timeXh43?/ JXh4 JslackXhO>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu >}w=Ђ?w?|>D=>>?G>'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhg?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhI?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh.?/ JXh4 JslackXh|>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu >}w=Ђ?w?|>D=>>?G>'?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhg?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhI?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh.?/ JXh4 JslackXh|>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsur>}Vݓ=Ђ?V?>.:D=;ߏ>>?G>%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh;ߏ> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhg?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhH?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh.: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsur>}Vݓ=Ђ?V?>.:D=;ߏ>>?G>%?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh;ߏ> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhg?X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhH?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh.: g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh>Rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu]@}A+A}?v<7@}?@A=А=P@O>#۹>F@I?Z?}?5?w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh@ fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__36/I0 JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__36/OProp_A6LUT_SLICEM_I0_O JLUT2XhzfA`e> WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh? TPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh5^?X1Y7 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhO>@ Jclock uncertaintyXh PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhP@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsu]@}A+A}?v<7@}?@A=А=P@O>#۹>F@I?Z?}?5?w?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh@ fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__36/I0 JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__36/OProp_A6LUT_SLICEM_I0_O JLUT2XhzfA`e> WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh? YUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh5^?X1Y7 (CLOCK_ROOT) WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhO>@ Jclock uncertaintyXh UQg_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh/ JXh4 JslackXhP@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuxY@}AS,AAH<7@A@A=А=&@IO>(>E@I?Z?}?5?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh\@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh'1@X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/C JFDCEXhzr> Jclock pessimismXhIO>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhS,A; J arrival timeXh/ JXh4 JslackXh&@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuxY@}AS,AAH<7@A@A=А=&@IO>(>E@I?Z?}?5?¥?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh\@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh'1@X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/C JFDCEXhzr> Jclock pessimismXhIO>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhS,A; J arrival timeXh/ JXh4 JslackXh&@ ;g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuqhY@}AO,A'1mʕ<7@'1@A=А=;@qLO>(>TE@I?Z?}?5?ʡ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh\@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh @X1Y7 (CLOCK_ROOT)y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/C JFDCEXhzr> Jclock pessimismXhqLO>@ Jclock uncertaintyXh EAg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhO,A; J arrival timeXh֣/ JXh4 JslackXh;@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuX@}AmG,Ab͖<7@b@A=А=[$@QO>(>pE@I?Z?}?5?A`?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh\@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/C JFDCEXhzr> Jclock pessimismXhQO>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhmG,A; J arrival timeXhj/ JXh4 JslackXh[$@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuX@}AmG,Ab͖<7@b@A=А=[$@QO>(>pE@I?Z?}?5?A`?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh\@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/C JFDCEXhzr> Jclock pessimismXhQO>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]Recov_GFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhmG,A; J arrival timeXhj/ JXh4 JslackXh[$@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuX@}AmG,Ab͖<7@b@A=А=[$@QO>(>pE@I?Z?}?5?A`?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh\@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/C JFDCEXhzr> Jclock pessimismXhQO>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]Recov_FFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhmG,A; J arrival timeXhj/ JXh4 JslackXh[$@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuX@}AzK,A 3L<7@ @A=А=<@OO>(>OE@I?Z?}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh\@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xhb@X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/C JFDCEXhzr> Jclock pessimismXhOO>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhzK,A; J arrival timeXhZ/ JXh4 JslackXh<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR"#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1*X1Y72#RCLK_BRAM_L_X30Y509/CLK_VDISTR_BOT1:X1Y7BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_39 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_39 rise@0.000nsuX@}AzK,A 3L<7@ @A=А=<@OO>(>OE@I?Z?}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_39 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_39!gtwiz_userclk_rx_srcclk_out[0]_39#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh\@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_39 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> B>g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0][0] Jnet (fo=674, routed)Xhb@X1Y7 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/C JFDCEXhzr> Jclock pessimismXhOO>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhzK,A; J arrival timeXhZ/ JXh4 JslackXh<@ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4!)y@1y @9Ay@Iy @e^@hq}1>d rise - rise rise - rise  RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[88]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuMb>}!vw=Mb?w?1>ja/9H= 0>Yd?+?/?$&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh 0> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[88]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhG?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[88]/C JFDCEXhzr> Jclock pessimismXhja/ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[88]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh!v; J arrival timeXh?/ JXh4 JslackXh1>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[91]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuMb>}!vw=Mb?w?1>ja/9H= 0>Yd?+?/?$&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh 0> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[91]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhG?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[91]/C JFDCEXhzr> Jclock pessimismXhja/ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[91]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh!v; J arrival timeXh?/ JXh4 JslackXh1>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[97]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuMb>}!vw=Mb?w?1>ja/9H= 0>Yd?+?/?$&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh 0> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[97]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhG?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[97]/C JFDCEXhzr> Jclock pessimismXhja/ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[97]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh!v; J arrival timeXh?/ JXh4 JslackXh1>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[98]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuMb>}!vw=Mb?w?1>ja/9H= 0>Yd?+?/?$&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh 0> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[98]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhG?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[98]/C JFDCEXhzr> Jclock pessimismXhja/ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[98]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh!v; J arrival timeXh?/ JXh4 JslackXh1>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[88]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuMb>}!vw=Mb?w?1>ja/9H= 0>Yd?+?/?$&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh 0> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[88]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhG?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[88]/C JFDCEXhzr> Jclock pessimismXhja/ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[88]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh!v; J arrival timeXh?/ JXh4 JslackXh1>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[91]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuMb>}!vw=Mb?w?1>ja/9H= 0>Yd?+?/?$&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh 0> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[91]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhG?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[91]/C JFDCEXhzr> Jclock pessimismXhja/ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[91]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh!v; J arrival timeXh?/ JXh4 JslackXh1>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[97]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuMb>}!vw=Mb?w?1>ja/9H= 0>Yd?+?/?$&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh 0> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[97]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhG?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[97]/C JFDCEXhzr> Jclock pessimismXhja/ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[97]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh!v; J arrival timeXh?/ JXh4 JslackXh1>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[98]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuMb>}!vw=Mb?w?1>ja/9H= 0>Yd?+?/?$&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh 0> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[98]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhG?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[98]/C JFDCEXhzr> Jclock pessimismXhja/ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[98]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh!v; J arrival timeXh?/ JXh4 JslackXh1>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[11]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuD`e>}=Mb??>^/9H=333>Yd?+?/?&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh333> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[11]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhG?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhH?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[11]/C JFDCEXhzr> Jclock pessimismXh^/ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[11]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhV?/ JXh4 JslackXh>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[17]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZj]gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuD`e>}=Mb??>^/9H=333>Yd?+?/?&?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh333> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[17]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhG?X3Y0 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhH?X3Y0 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[17]/C JFDCEXhzr> Jclock pessimismXh^/ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[17]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhV?/ JXh4 JslackXh>g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu|@}Al7A>q@?u@?-?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhT]@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xhff&@X3Y0 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhl7A; J arrival timeXh/ JXh4 JslackXh^@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuj|@}A8AxAJ!I|@xA@A=А= g@=>>~j@?u@?B`?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhT]@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh(@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C JFDCEXhzr> Jclock pessimismXh=>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh8A; J arrival timeXh/ JXh4 JslackXh g@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuj|@}A8AxAJ!I|@xA@A=А= g@=>>~j@?u@?B`?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhT]@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh(@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/C JFDCEXhzr> Jclock pessimismXh=>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh8A; J arrival timeXh/ JXh4 JslackXh g@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuj|@}A8AxAJ!I|@xA@A=А= g@=>>~j@?u@?B`?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhT]@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh(@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C JFDCEXhzr> Jclock pessimismXh=>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh8A; J arrival timeXh/ JXh4 JslackXh g@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu|@}A7AXA!I|@XA@A=А=qg@>>#i@?u@??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhT]@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh<'@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh7A; J arrival timeXh(1/ JXh4 JslackXhqg@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuy@}Aj7A%A#I|@%A@A=А=Xi@k>>wg@?u@?z?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhT]@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)XhP'@X3Y0 (CLOCK_ROOT)y GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/C JFDCEXhzr> Jclock pessimismXhk>@ Jclock uncertaintyXh EAg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhj7A; J arrival timeXh"/ JXh4 JslackXhXi@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu:y@}AM7A`@#I|@`@@A=А=Ai@ >>Kg@?u@?W9?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhT]@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xhl'@X3Y0 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/C JFDCEXhzr> Jclock pessimismXh >@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhM7A; J arrival timeXhz/ JXh4 JslackXhAi@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsu1t@}A\7A@R#I|@@@A=А=fn@>>b@?u@?Z?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhT]@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xh|'@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh\7A; J arrival timeXhv/ JXh4 JslackXhfn@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuxo@}Aݾ7ANb@%I|@Nb@@A=А=@r@>>]@?u@?43?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhT]@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xhy&@X3Y0 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhݾ7A; J arrival timeXh/ JXh4 JslackXh@r@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR"!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1*X3Y02!RCLK_DSP_L_X59Y89/CLK_VDISTR_BOT1:X3Y0BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_4 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_4 rise@0.000nsuxo@}Aݾ7ANb@%I|@Nb@@A=А=@r@>>]@?u@?43?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_4 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_4 gtwiz_userclk_rx_srcclk_out[0]_4#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh)\7@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhT]@X3Y0 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_4 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[2] Jnet (fo=674, routed)Xhy&@X3Y0 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhݾ7A; J arrival timeXh/ JXh4 JslackXh@r@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40!)y@1y @9Ay@Iy @e綱@hq}>d rise - rise rise - rise  RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuX9>}F^j{<.}?^?>ʺ89H=+>>8? >?5?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh+> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh`?X1Y7 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhE?X1Y7 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXhʺ8 c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhF; J arrival timeXh?/ JXh4 JslackXh>73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu k>}Zʑ=$y??>D=5^:>>[d> >?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh5^:>d 2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(\?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[25]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[25]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhZ; J arrival timeXh6^?/ JXh4 JslackXh>473SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu k>}Zʑ=$y??>D=5^:>>[d> >?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh5^:>d 2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(\?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[30]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[30]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhZ; J arrival timeXh6^?/ JXh4 JslackXh>473SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuK >}Zu.9=$y?u?ZP>.D=R>>[d> >n?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(\?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr> Jclock pessimismXh.{ .*SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhZ; J arrival timeXhp?/ JXh4 JslackXhZP>473SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuK >}Zu.9=$y?u?ZP>.D=R>>[d> >n?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(\?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr> Jclock pessimismXh.| .*SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[23]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhZ; J arrival timeXhp?/ JXh4 JslackXhZP>473SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuK >}Zu.9=$y?u?ZP>.D=R>>[d> >n?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(\?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXh.{ .*SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[32]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhZ; J arrival timeXhp?/ JXh4 JslackXhZP>473SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuK >}Zu.9=$y?u?ZP>.D=R>>[d> >n?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(\?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXh.| .*SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[34]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhZ; J arrival timeXhp?/ JXh4 JslackXhZP>473SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuK >}Zu.9=$y?u?ZP>.D=R>>[d> >n?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(\?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXh.{ .*SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[36]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhZ; J arrival timeXhp?/ JXh4 JslackXhZP>473SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsuK >}Zu.9=$y?u?ZP>.D=R>>[d> >n?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhR>d 2.SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(\?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT)b 0,SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr> Jclock pessimismXh.| .*SFP_GEN[38].ngCCM_gbt/RX_Word_rx40_reg[38]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhZ; J arrival timeXhp?/ JXh4 JslackXhZP>473SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[38].ngCCM_gbt/pwr_good_pre_reg/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu>}_Ԙ~A=$y?Ԙ?Q>.D=V>>[d> >j?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40(DCD - SCD - CPR) 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[38].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhV>` .*SFP_GEN[38].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh(\?X1Y7 (CLOCK_ROOT)i 73SFP_GEN[38].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[38].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhB`?X1Y7 (CLOCK_ROOT)^ ,(SFP_GEN[38].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXh.w *&SFP_GEN[38].ngCCM_gbt/pwr_good_pre_regRemov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh_; J arrival timeXhҝ?/ JXh4 JslackXhQ>4d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsux!@}A+Av2潵*@v@A=А=綱@avO>V>u@ffF?䥻?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhu@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl@X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXhavO>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhJ / JXh4 JslackXh綱@Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsux!@}A+Av2潵*@v@A=А=綱@avO>V>u@ffF?䥻?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhu@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl@X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXhavO>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[14]Recov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhJ / JXh4 JslackXh綱@Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsux!@}A+Av2潵*@v@A=А=綱@avO>V>u@ffF?䥻?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhu@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl@X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXhavO>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhJ / JXh4 JslackXh綱@Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsux!@}A+Av2潵*@v@A=А=綱@avO>V>u@ffF?䥻?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhu@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl@X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C JFDCEXhzr> Jclock pessimismXhavO>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[0]Recov_BFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhJ / JXh4 JslackXh綱@Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsux!@}A+Av2潵*@v@A=А=綱@avO>V>u@ffF?䥻?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhu@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl@X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXhavO>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhJ / JXh4 JslackXh綱@Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsux!@}A+Av2潵*@v@A=А=綱@avO>V>u@ffF?䥻?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhu@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl@X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXhavO>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhJ / JXh4 JslackXh綱@Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsux!@}A+Av2潵*@v@A=А=綱@avO>V>u@ffF?䥻?n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhu@ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhl@X1Y7 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y7 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXhavO>@ Jclock uncertaintyXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhJ / JXh4 JslackXh綱@RRNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu@}AH+A-F+@-@A=А=z@kO>)\>% @ffF?ҽ?n2?I ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh% @ gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhC?X1Y7 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]/C JFDCEXhzr> Jclock pessimismXhkO>@ Jclock uncertaintyXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhH+A; J arrival timeXhٞ/ JXh4 JslackXhz@RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[79]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu@}AH+A-F+@-@A=А=z@kO>)\>% @ffF?ҽ?n2?I ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh% @ gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[79]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhC?X1Y7 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[79]/C JFDCEXhzr> Jclock pessimismXhkO>@ Jclock uncertaintyXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[79]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhH+A; J arrival timeXhٞ/ JXh4 JslackXhz@RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[100]/CLR""RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1*X1Y72"RCLK_DSP_L_X27Y509/CLK_VDISTR_BOT1:X1Y7BJZj_gtwiz_userclk_rx_srcclk_out[0]_40 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_40 rise@0.000nsu@}AH+A-F+@-@A=А=z@kO>)\>% @ffF?ҽ?n2?I ?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_40 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_40!gtwiz_userclk_rx_srcclk_out[0]_40#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh% @ hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[100]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y7 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_40 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhC?X1Y7 (CLOCK_ROOT) fbg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[100]/C JFDCEXhzr> Jclock pessimismXhkO>@ Jclock uncertaintyXh d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[100]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhH+A; J arrival timeXhٞ/ JXh4 JslackXhz@D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41!)y@1y @9Ay@Iy @e,@hq}B'>d rise - rise rise - rise  73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuq>}e;_=?e;?B'>B'D=@>V>/?+?ObP?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@>d 2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƫ?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[16]/C JFDCEXhzr> Jclock pessimismXhB'{ .*SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[16]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh<߿?/ JXh4 JslackXhB'>473SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuq>}e;_=?e;?B'>B'D=@>V>/?+?ObP?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@>d 2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƫ?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr> Jclock pessimismXhB'| .*SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh<߿?/ JXh4 JslackXhB'>473SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuq>}e;_=?e;?B'>B'D=@>V>/?+?ObP?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@>d 2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƫ?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[22]/C JFDCEXhzr> Jclock pessimismXhB'{ .*SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[22]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh<߿?/ JXh4 JslackXhB'>473SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuq>}e;_=?e;?B'>B'D=@>V>/?+?ObP?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@>d 2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƫ?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr> Jclock pessimismXhB'| .*SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[23]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh<߿?/ JXh4 JslackXhB'>473SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuq>}e;_=?e;?B'>B'D=@>V>/?+?ObP?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@>d 2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƫ?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[24]/C JFDCEXhzr> Jclock pessimismXhB'{ .*SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[24]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh<߿?/ JXh4 JslackXhB'>473SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuq>}e;_=?e;?B'>B'D=@>V>/?+?ObP?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@>d 2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƫ?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[26]/C JFDCEXhzr> Jclock pessimismXhB'| .*SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[26]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh<߿?/ JXh4 JslackXhB'>473SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuq>}e;_=?e;?B'>B'D=@>V>/?+?ObP?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@>d 2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƫ?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXhB'{ .*SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[28]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh<߿?/ JXh4 JslackXhB'>473SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuq>}e;_=?e;?B'>B'D=@>V>/?+?ObP?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@>d 2.SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhƫ?X1Y6 (CLOCK_ROOT)b 0,SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[30]/C JFDCEXhzr> Jclock pessimismXhB'| .*SFP_GEN[39].ngCCM_gbt/RX_Word_rx40_reg[30]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh<߿?/ JXh4 JslackXhB'>473SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[39].ngCCM_gbt/pwr_good_pre_reg/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuD`e>}Z GW=?G?UE*>YFD=X94>V>/?+?zT?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[39].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhX94>` .*SFP_GEN[39].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhВ?X1Y6 (CLOCK_ROOT)i 73SFP_GEN[39].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[39].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhҭ?X1Y6 (CLOCK_ROOT)^ ,(SFP_GEN[39].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhYFw *&SFP_GEN[39].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhZ ; J arrival timeXhV?/ JXh4 JslackXhUE*>4RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[47]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZj_gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu$>}󭿭K=I ??"=>9H=Z>V>;?+?-?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhZ> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[47]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh33?X1Y6 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh~?X1Y6 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[47]/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[47]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh"=>g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu-5@}A1Ak,pI@k,@A=А=,@b>㥛>q="@5^?o?l{?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhE? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhR.@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT)y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh EAg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhο/ JXh4 JslackXh,@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsu-5@}A1Ak,pI@k,@A=А=,@b>㥛>q="@5^?o?l{?Zd?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhE? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhR.@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhο/ JXh4 JslackXh,@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuV5@}Ag1A,rI@,@A=А=@b>㥛>!@5^?o?l{?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhE? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhR.@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)XhD@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhg1A; J arrival timeXh|/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuV5@}Ag1A,rI@,@A=А=@b>㥛>!@5^?o?l{?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhE? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhR.@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)XhD@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhg1A; J arrival timeXh|/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuV5@}Ag1A,rI@,@A=А=@b>㥛>!@5^?o?l{?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhE? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhR.@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)XhD@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]Recov_FFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhg1A; J arrival timeXh|/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuV5@}Ag1A,rI@,@A=А=@b>㥛>!@5^?o?l{?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhE? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhR.@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)XhD@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhg1A; J arrival timeXh|/ JXh4 JslackXh@  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuV5@}Ag1A,rI@,@A=А=@b>㥛>!@5^?o?l{?"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhE? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhR.@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)XhD@X1Y6 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhg1A; J arrival timeXh|/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuף0@}A1AW-(>@5^?o?l{?1?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh9@ fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__38/I0 JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__38/OProp_D6LUT_SLICEL_I0_O JLUT2Xhzf)> WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhS> TPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhR.@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh b>@ Jclock uncertaintyXh PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhG/ JXh4 JslackXh[@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT2=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuף0@}A1AW-(>@5^?o?l{?1?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh9@ fbg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__38/I0 JXhzr eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__38/OProp_D6LUT_SLICEL_I0_O JLUT2Xhzf)> WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhS> YUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhR.@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh@X1Y6 (CLOCK_ROOT) WSg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh b>@ Jclock uncertaintyXh UQg_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhG/ JXh4 JslackXh[@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR"$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT*X1Y62$RCLK_CLEL_R_L_X16Y449/CLK_VDISTR_BOT:X1Y6BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_41 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_41 rise@0.000nsuO/@}A1A,UmI@,@A=А=֦@b>㥛>@5^?o?l{?ƫ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_41 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_41!gtwiz_userclk_rx_srcclk_out[0]_41#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhE? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf(> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhR.@X1Y6 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_41 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&>v g_gbt_bank[3].gbtbank/CLK Jnet (fo=674, routed)Xh/@X1Y6 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C JFDCEXhzr> Jclock pessimismXhb>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXhj/ JXh4 JslackXh֦@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42!)y@1y @9Ay@Iy @e+@hq}޽=d rise - rise rise - rise  d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu@>}t<߯=A?<߯?޽=x 9H=V>>Z$? >~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhV> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhsh?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXhx  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXht; J arrival timeXhQ?/ JXh4 JslackXh޽=Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu@>}t<߯=A?<߯?޽=x 9H=V>>Z$? >~J?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhV> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhsh?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXhx  g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXht; J arrival timeXhQ?/ JXh4 JslackXh޽=RRNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuD`e>}@.Ι=?.?Z>e 9H=433>> #? >$F?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh433> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh&?X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhq=?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXhe  c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh@; J arrival timeXh?/ JXh4 JslackXhZ>73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu>}gٮ =?ٮ?f$>ǧ D== W>>!? >rH?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh= W>d 2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZd?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[22]/C JFDCEXhzr> Jclock pessimismXhǧ { .*SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[22]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhg; J arrival timeXh?/ JXh4 JslackXhf$>473SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu>}gٮ =?ٮ?f$>ǧ D== W>>!? >rH?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh= W>d 2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[80]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZd?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[80]/C JFDCEXhzr> Jclock pessimismXhǧ | .*SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[80]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhg; J arrival timeXh?/ JXh4 JslackXhf$>473SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu>}gٮ =?ٮ?f$>ǧ D== W>>!? >rH?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh= W>d 2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhZd?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[83]/C JFDCEXhzr> Jclock pessimismXhǧ { .*SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[83]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhg; J arrival timeXh?/ JXh4 JslackXhf$>473SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu>}YQRtv=?R?oD>}V@D=V>>!? >'1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhV>d 2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[72]/C JFDCEXhzr> Jclock pessimismXh}V@{ .*SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[72]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhYQ; J arrival timeXh=߯?/ JXh4 JslackXhoD>473SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu>}YQRtv=?R?oD>}V@D=V>>!? >'1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhV>d 2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[74]/C JFDCEXhzr> Jclock pessimismXh}V@| .*SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[74]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhYQ; J arrival timeXh=߯?/ JXh4 JslackXhoD>473SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu>}YQRtv=?R?oD>}V@D=V>>!? >'1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhV>d 2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[76]/C JFDCEXhzr> Jclock pessimismXh}V@{ .*SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[76]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhYQ; J arrival timeXh=߯?/ JXh4 JslackXhoD>473SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu>}YQRtv=?R?oD>}V@D=V>>!? >'1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42(DCD - SCD - CPR) 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=n *&SFP_GEN[40].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhV>d 2.SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh ?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[40].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[40].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhC?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[78]/C JFDCEXhzr> Jclock pessimismXh}V@| .*SFP_GEN[40].ngCCM_gbt/RX_Word_rx40_reg[78]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhYQ; J arrival timeXh=߯?/ JXh4 JslackXhoD>4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu$v@}A0A^)~<5@^)@A=А=+@U>>\b@ffF??n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh"@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/C JFDCEXhzr> Jclock pessimismXhU>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh+@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu.u@}A0A)M<5@)@A=А=Qϋ@U>>b@ffF??n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh"@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/C JFDCEXhzr> Jclock pessimismXhU>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh_/ JXh4 JslackXhQϋ@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuXq@}A0A^)~<5@^)@A=А=@U>>]@ffF??n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh"@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C JFDCEXhzr> Jclock pessimismXhU>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhP/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuXq@}A0A^)~<5@^)@A=А=@U>>]@ffF??n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh"@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C JFDCEXhzr> Jclock pessimismXhU>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhP/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu_p@}A0A)M<5@)@A=А=5@U>>O]@ffF??n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh"@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C JFDCEXhzr> Jclock pessimismXhU>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhS/ JXh4 JslackXh5@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu_p@}A0A)M<5@)@A=А=5@U>>O]@ffF??n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh"@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/C JFDCEXhzr> Jclock pessimismXhU>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhS/ JXh4 JslackXh5@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu_p@}A0A)M<5@)@A=А=5@U>>O]@ffF??n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh"@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/C JFDCEXhzr> Jclock pessimismXhU>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]Recov_FFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhS/ JXh4 JslackXh5@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsu_p@}A0A)M<5@)@A=А=5@U>>O]@ffF??n2??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh"@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf +> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/C JFDCEXhzr> Jclock pessimismXhU>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhS/ JXh4 JslackXh5@ ;g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuq=j@}Ag0A9(;5@9(@A=А=@U>>V@ffF??n2?b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh"@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf +> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xhף@X1Y8 (CLOCK_ROOT)y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C JFDCEXhzr> Jclock pessimismXhU>@ Jclock uncertaintyXh EAg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhg0A; J arrival timeXh/ JXh4 JslackXh@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_42 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_42 rise@0.000nsuq=j@}Ag0A9(;5@9(@A=А=@U>>V@ffF??n2?b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_42 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_42!gtwiz_userclk_rx_srcclk_out[0]_42#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh"@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2/OProp_A6LUT_SLICEM_I0_O JLUT3Xhzf +> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh\@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_42 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_1[0] Jnet (fo=674, routed)Xhף@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/C JFDCEXhzr> Jclock pessimismXhU>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]Recov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhg0A; J arrival timeXh/ JXh4 JslackXh@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43!)y@1y @9Ay@Iy @ey7@hq}}c>d rise - rise rise - rise  73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C.*SFP_GEN[41].ngCCM_gbt/pwr_good_pre_reg/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu$>}уL7V=p}?L7?}c>J0D="[>j>8?/>?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh"[>` .*SFP_GEN[41].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw_?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh…?X1Y8 (CLOCK_ROOT)^ ,(SFP_GEN[41].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhJ0w *&SFP_GEN[41].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhу; J arrival timeXhA?/ JXh4 JslackXh}c>473SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuv>}m盿ʩ=p}?m?Nd>D=+>j>8?/>M"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh+>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw_?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[16]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhNd>473SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuv>}m盿ʩ=p}?m?Nd>D=+>j>8?/>M"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh+>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw_?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[17]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhNd>473SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuv>}m盿ʩ=p}?m?Nd>D=+>j>8?/>M"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh+>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw_?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[19]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[19]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhNd>473SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuv>}m盿ʩ=p}?m?Nd>D=+>j>8?/>M"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh+>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw_?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[21]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhNd>473SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuv>}m盿ʩ=p}?m?Nd>D=+>j>8?/>M"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh+>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[22]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw_?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[22]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[22]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhNd>473SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuv>}m盿ʩ=p}?m?Nd>D=+>j>8?/>M"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh+>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw_?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[23]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhNd>473SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuv>}m盿ʩ=p}?m?Nd>D=+>j>8?/>M"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh+>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[27]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw_?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[27]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[27]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhNd>473SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuv>}m盿ʩ=p}?m?Nd>D=+>j>8?/>M"?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[41].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh+>d 2.SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhw_?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[41].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[41].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhr?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[31]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[41].ngCCM_gbt/RX_Word_rx40_reg[31]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhNd>4d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuN7>} ^=p}?^?.g>2D=Ga>j>8?/>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhGa> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhw_?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhE?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C JFDCEXhzr> Jclock pessimismXh2 g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[5].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[9]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXh&?/ JXh4 JslackXh.g>Rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuD@}Aj+ATDV6@T@A=А=y7@ N>t>S@ʡE?t?sh1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C JFDCEXhzr> Jclock pessimismXh N>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhj+A; J arrival timeXhF/ JXh4 JslackXhy7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuD@}Aj+ATDV6@T@A=А=y7@ N>t>S@ʡE?t?sh1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/C JFDCEXhzr> Jclock pessimismXh N>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhj+A; J arrival timeXhF/ JXh4 JslackXhy7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuD@}Aj+ATDV6@T@A=А=y7@ N>t>S@ʡE?t?sh1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/C JFDCEXhzr> Jclock pessimismXh N>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhj+A; J arrival timeXhF/ JXh4 JslackXhy7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuX9@}AN+A HV6@@A=А=7@NN>t> @ʡE?t?sh1? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)XhYd?X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/C JFDCEXhzr> Jclock pessimismXhNN>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhN+A; J arrival timeXh[d/ JXh4 JslackXh7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsuX9@}AN+A HV6@@A=А=7@NN>t> @ʡE?t?sh1? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)XhYd?X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/C JFDCEXhzr> Jclock pessimismXhNN>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]Recov_GFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhN+A; J arrival timeXh[d/ JXh4 JslackXh7@ /g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A5`+Az9kV6@z@A=А=9@N>t>B`@ʡE?t?sh1? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh5`+A; J arrival timeXh/ JXh4 JslackXh9@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A5`+Az9kV6@z@A=А=9@N>t>B`@ʡE?t?sh1? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh5`+A; J arrival timeXh/ JXh4 JslackXh9@ /g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A5`+Az9kV6@z@A=А=9@N>t>B`@ʡE?t?sh1? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh5`+A; J arrival timeXh/ JXh4 JslackXh9@ /g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu@}A5`+Az9kV6@z@A=А=9@N>t>B`@ʡE?t?sh1? ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C JFDCEXhzr> Jclock pessimismXhN>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh5`+A; J arrival timeXh/ JXh4 JslackXh9@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0*X1Y82"RCLK_DSP_L_X27Y569/CLK_VDISTR_BOT0:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_43 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_43 rise@0.000nsu㥛@}AQh+AgV6@@A=А=w?@|N>t>n@ʡE?t?sh1?Nb?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_43 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_43!gtwiz_userclk_rx_srcclk_out[0]_43#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh(<@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzfu> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh"@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_43 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_2[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C JFDCEXhzr> Jclock pessimismXh|N>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhQh+A; J arrival timeXh/ JXh4 JslackXhw?@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44!)y@1y @9Ay@Iy @e/8@hq}=d rise - rise rise - rise  RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsuϡE>}+=R??=~#9H=t>%>d;?>ˡE?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xht> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xhw?X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh~# c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/firstOut_regRemov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhl?/ JXh4 JslackXh=d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsus>}?N={??H>$9H=~>%>?>ˡE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh~> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv~?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh?; J arrival timeXhX9?/ JXh4 JslackXhH>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsus>}?N={??H>$9H=~>%>?>ˡE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh~> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv~?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXh$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh?; J arrival timeXhX9?/ JXh4 JslackXhH>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsus>}?N={??H>$9H=~>%>?>ˡE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh~> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv~?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXh$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh?; J arrival timeXhX9?/ JXh4 JslackXhH>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsus>}?N={??H>$9H=~>%>?>ˡE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh~> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv~?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzr> Jclock pessimismXh$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[10]Remov_BFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh?; J arrival timeXhX9?/ JXh4 JslackXhH>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsus>}?N={??H>$9H=~>%>?>ˡE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh~> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv~?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXh$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[12]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh?; J arrival timeXhX9?/ JXh4 JslackXhH>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsus>}?N={??H>$9H=~>%>?>ˡE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh~> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv~?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_CFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh?; J arrival timeXhX9?/ JXh4 JslackXhH>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsus>}?N={??H>$9H=~>%>?>ˡE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh~> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv~?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXh$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh?; J arrival timeXhX9?/ JXh4 JslackXhH>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsus>}?N={??H>$9H=~>%>?>ˡE?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh~> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv~?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh?; J arrival timeXhX9?/ JXh4 JslackXhH>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu>} ;={??pZ>*$9H=>%>?>8A?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_DFF2_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhv~?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhx?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXh*$ g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXhZ?/ JXh4 JslackXhpZ>Rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu$@}A 1A~*.;7@~*@A=А=/8@Y>|>-@CK?S?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhCc@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhn@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 1A; J arrival timeXh/ JXh4 JslackXh/8@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu$@}A 1A~*.;7@~*@A=А=/8@Y>|>-@CK?S?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhCc@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhn@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 1A; J arrival timeXh/ JXh4 JslackXh/8@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu$@}A 1A~*.;7@~*@A=А=/8@Y>|>-@CK?S?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhCc@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhn@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 1A; J arrival timeXh/ JXh4 JslackXh/8@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu$@}A 1A~*.;7@~*@A=А=/8@Y>|>-@CK?S?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhCc@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhn@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 1A; J arrival timeXh/ JXh4 JslackXh/8@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu@}A0AM*>@;7@M*@A=А= B@Y>|>&@CK?S?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhCc@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhq=@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhz/ JXh4 JslackXh B@ 4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu@}A0AM*>@;7@M*@A=А= B@Y>|>&@CK?S?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhCc@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhq=@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhz/ JXh4 JslackXh B@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu@}A0AM*>@;7@M*@A=А= B@Y>|>&@CK?S?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhCc@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhq=@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhz/ JXh4 JslackXh B@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu@}A0AM*>@;7@M*@A=А= B@Y>|>&@CK?S?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhCc@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhq=@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhz/ JXh4 JslackXh B@ 4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsu@}A0AM*>@;7@M*@A=А= B@Y>|>&@CK?S?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhCc@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xhq=@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5]Recov_EFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhz/ JXh4 JslackXh B@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT*X1Y82$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_BOT:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_44 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_44 rise@0.000nsua@}A0A֣(輼7@֣(@A=А=}B@Y>|>@CK?S?5?E?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_44 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_44!gtwiz_userclk_rx_srcclk_out[0]_44#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhCc@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2/OProp_C6LUT_SLICEL_I0_O JLUT3Xhzf֣p> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhz@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_44 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_3[0] Jnet (fo=674, routed)Xht@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/C JFDCEXhzr> Jclock pessimismXhY>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhl/ JXh4 JslackXh}B@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45!)y@1y @9Ay@Iy @eÉ?hq}0>d rise - rise rise - rise  d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsun>}:;İP=G?İ?0>i!9H=j<>>$?G>I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhj<> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXhi! g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh:;; J arrival timeXh?/ JXh4 JslackXh0>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsun>}:;İP=G?İ?0>i!9H=j<>>$?G>I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhj<> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXhi! g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh:;; J arrival timeXh?/ JXh4 JslackXh0>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsun>}:;İP=G?İ?0>i!9H=j<>>$?G>I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhj<> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C JFDCEXhzr> Jclock pessimismXhi! g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh:;; J arrival timeXh?/ JXh4 JslackXh0>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsun>}:;İP=G?İ?0>i!9H=j<>>$?G>I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhj<> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhO?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXhi! g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh:;; J arrival timeXh?/ JXh4 JslackXh0>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsunm>} Aذ=G??>o!9H=Zd;>>$?G>xI?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZd;> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXho! g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXh?/ JXh4 JslackXh>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsunm>} Aذ=G??>o!9H=Zd;>>$?G>xI?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZd;> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhn?X1Y8 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhV?X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXho! g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[7].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXh?/ JXh4 JslackXh>RRNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu~j>}5=d;??_>8!9H=Q8>> ?G>A?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhQ8> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)XhNb?X1Y8 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> uqg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhL7?X1Y8 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh8! c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[7].gbt_rxgearbox_inst/firstOut_regRemov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhD?/ JXh4 JslackXh_>73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuCl>}U<߯B=M?<߯? K>i!D=Zd;>>&?G>'1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd;>d 2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[28]/C JFDCEXhzr> Jclock pessimismXhi!{ .*SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[28]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhU; J arrival timeXh<߯?/ JXh4 JslackXh K>473SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuCl>}U<߯B=M?<߯? K>i!D=Zd;>>&?G>'1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd;>d 2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[29]/C JFDCEXhzr> Jclock pessimismXhi!| .*SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[29]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhU; J arrival timeXh<߯?/ JXh4 JslackXh K>473SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZj_gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuCl>}U<߯B=M?<߯? K>i!D=Zd;>>&?G>'1H?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45(DCD - SCD - CPR) 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[43].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd;>d 2.SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xht?X1Y8 (CLOCK_ROOT)i 73SFP_GEN[43].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[43].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhj?X1Y8 (CLOCK_ROOT)b 0,SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXhi!{ .*SFP_GEN[43].ngCCM_gbt/RX_Word_rx40_reg[36]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhU; J arrival timeXh<߯?/ JXh4 JslackXh K>4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsuhf@}A0AM*<A8@M*@A=А=É?4V>X>@I??}?5?#?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhL7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xhq=@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhC/ JXh4 JslackXhÉ? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsun@}A0A5^*C컵A8@5^*@A=А=É?4V>X>@I??}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhL7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhM@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhG/ JXh4 JslackXhÉ? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsun@}A0A5^*C컵A8@5^*@A=А=É?4V>X>@I??}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhL7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhM@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhG/ JXh4 JslackXhÉ? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsun@}A0A5^*C컵A8@5^*@A=А=É?4V>X>@I??}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhL7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhM@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhG/ JXh4 JslackXhÉ? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsun@}A0A5^*C컵A8@5^*@A=А=É?4V>X>@I??}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhL7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)XhM@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXhG/ JXh4 JslackXhÉ? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu-@}A0A-*G'A8@-*@A=А=-?4V>X>@I??}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhL7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh&/ JXh4 JslackXh-? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu-@}A0A-*G'A8@-*@A=А=-?4V>X>@I??}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhL7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh&/ JXh4 JslackXh-? 2g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu-@}A0A-*G'A8@-*@A=А=-?4V>X>@I??}?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhL7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh&/ JXh4 JslackXh-? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu@}A0Ap=*A8@p=*@A=А=揾?4V>X>,@I??}?5?]?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhL7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xh-@X1Y8 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh揾? 1g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR"#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1*X1Y82#RCLK_BRAM_L_X30Y569/CLK_VDISTR_BOT1:X1Y8BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_45 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_45 rise@0.000nsu/@}AP0A֣(! A8@֣(@A=А=?4V>X>@I??}?5?*?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_45 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_45!gtwiz_userclk_rx_srcclk_out[0]_45#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhL7@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2/OProp_D6LUT_SLICEL_I0_O JLUT3XhzfZd> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhV@X1Y8 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_45 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_4[0] Jnet (fo=674, routed)Xht@X1Y8 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C JFDCEXhzr> Jclock pessimismXh4V>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhP0A; J arrival timeXh/ JXh4 JslackXh? D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46!)y@1y @9Ay@Iy @e(5@hq}H >d rise - rise rise - rise  d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuw>}we;=?e;?H >""9H=ˡE>%>.?>$F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhˡE> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@5~?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhƛ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C JFDCEXhzr> Jclock pessimismXh"" g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[10]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhw; J arrival timeXh?/ JXh4 JslackXhH >Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuw>}we;=?e;?H >""9H=ˡE>%>.?>$F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhˡE> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@5~?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhƛ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXh"" g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhw; J arrival timeXh?/ JXh4 JslackXhH >Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuw>}we;=?e;?H >""9H=ˡE>%>.?>$F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhˡE> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@5~?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhƛ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]/C JFDCEXhzr> Jclock pessimismXh"" g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[13]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhw; J arrival timeXh?/ JXh4 JslackXhH >Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuw>}we;=?e;?H >""9H=ˡE>%>.?>$F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhˡE> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@5~?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhƛ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXh"" g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_FFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhw; J arrival timeXh?/ JXh4 JslackXhH >Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuw>}we;=?e;?H >""9H=ˡE>%>.?>$F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhˡE> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@5~?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhƛ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh"" g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhw; J arrival timeXh?/ JXh4 JslackXhH >Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuw>}we;=?e;?H >""9H=ˡE>%>.?>$F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhˡE> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@5~?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhƛ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXh"" g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhw; J arrival timeXh?/ JXh4 JslackXhH >Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuw>}we;=?e;?H >""9H=ˡE>%>.?>$F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhˡE> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@5~?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhƛ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C JFDCEXhzr> Jclock pessimismXh"" g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhw; J arrival timeXh?/ JXh4 JslackXhH >Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsuw>}we;=?e;?H >""9H=ˡE>%>.?>$F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhˡE> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@5~?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhƛ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh"" g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhw; J arrival timeXh?/ JXh4 JslackXhH >Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsux>}we;=?e;?N >""9H=F>%>.?>$F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhF> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@5~?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhƛ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXh"" g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhw; J arrival timeXhW?/ JXh4 JslackXhN >Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsux>}we;=?e;?N >""9H=F>%>.?>$F?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhF> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh@5~?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[8].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhƛ?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXh"" g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[8].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhw; J arrival timeXhW?/ JXh4 JslackXhN >R3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsud;@}An0A$)k:v6@$)@A=А=(5@'W>>@ K?%?5?+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh-]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/C JFDCEXhzr> Jclock pessimismXh'W>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhn0A; J arrival timeXhd;/ JXh4 JslackXh(5@ 4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsud;@}An0A$)k:v6@$)@A=А=(5@'W>>@ K?%?5?+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh-]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/C JFDCEXhzr> Jclock pessimismXh'W>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhn0A; J arrival timeXhd;/ JXh4 JslackXh(5@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsud;@}An0A$)k:v6@$)@A=А=(5@'W>>@ K?%?5?+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh-]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/C JFDCEXhzr> Jclock pessimismXh'W>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhn0A; J arrival timeXhd;/ JXh4 JslackXh(5@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsud;@}An0A$)k:v6@$)@A=А=(5@'W>>@ K?%?5?+?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh-]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xh@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/C JFDCEXhzr> Jclock pessimismXh'W>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhn0A; J arrival timeXhd;/ JXh4 JslackXh(5@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu@}A0Ax)zn<v6@x)@A=А=3\B@'W>>@ K?%?5?b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh-]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xhrh@X1Y9 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/C JFDCEXhzr> Jclock pessimismXh'W>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh-/ JXh4 JslackXh3\B@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu@}A0Ax)zn<v6@x)@A=А=3\B@'W>>@ K?%?5?b?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh-]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)Xhrh@X1Y9 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/C JFDCEXhzr> Jclock pessimismXh'W>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh-/ JXh4 JslackXh3\B@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu/ݤ@}Aѷ0AG)匠;v6@G)@A=А=B@'W>>w@ K?%?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh-]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)XhK7@X1Y9 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/C JFDCEXhzr> Jclock pessimismXh'W>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]Recov_BFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhѷ0A; J arrival timeXhJ / JXh4 JslackXhB@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsu/ݤ@}Aѷ0AG)匠;v6@G)@A=А=B@'W>>w@ K?%?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh-]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)XhK7@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]/C JFDCEXhzr> Jclock pessimismXh'W>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhѷ0A; J arrival timeXhJ / JXh4 JslackXhB@ ?g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsṳ@}A0AX)@R;v6@X)@A=А=EB@'W>>@ K?%?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh-]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)XhG@X1Y9 (CLOCK_ROOT)y GCg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/C JFDCEXhzr> Jclock pessimismXh'W>@ Jclock uncertaintyXh EAg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhEB@ 3g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR"$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP*X1Y92$RCLK_CLEL_R_L_X29Y569/CLK_VDISTR_TOP:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_46 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_46 rise@0.000nsṳ@}A0AX)@R;v6@X)@A=А=EB@'W>>@ K?%?5??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_46 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_46!gtwiz_userclk_rx_srcclk_out[0]_46#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh-]@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhC@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_46 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_5[0] Jnet (fo=674, routed)XhG@X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/C JFDCEXhzr> Jclock pessimismXh'W>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXhEB@ D **async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47!)y@1y @9Ay@Iy @e[@hq}].>d rise - rise rise - rise  RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/firstOut_reg/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu? W>}ǂ6=[d{??].>].9H=/$>j>>(>I?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh/$> gcg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= C?g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/CLK Jnet (fo=674, routed)Xh.]?X1Y9 (CLOCK_ROOT) RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhz?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh]. c_g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/firstOut_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhǂ; J arrival timeXhu?/ JXh4 JslackXh].>73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu>}  =Iz? ?m4>D=Zd>j>>(>$!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) 73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[45].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd>d 2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/]?X1Y9 (CLOCK_ROOT)i 73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhP?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXh{ .*SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[32]Remov_DFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXh ?/ JXh4 JslackXhm4>473SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu>}  =Iz? ?m4>D=Zd>j>>(>$!?z(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) 73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=n *&SFP_GEN[45].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhZd>d 2.SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= FBSFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh/]?X1Y9 (CLOCK_ROOT)i 73SFP_GEN[45].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr e J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 84SFP_GEN[45].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhP?X1Y9 (CLOCK_ROOT)b 0,SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXh| .*SFP_GEN[45].ngCCM_gbt/RX_Word_rx40_reg[34]Remov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh ; J arrival timeXh ?/ JXh4 JslackXhm4>4g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/Cgcg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/RX_HEADER_LOCKED_O_reg/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu$>}Q߆Q}t=/}?Q? J>9H=Z>j>G?(>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzr9H= \Xg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/bitslip_reset_9 Jnet (fo=32, routed)XhZ> gcg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/RX_HEADER_LOCKED_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh|_?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> PLg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/CLK Jnet (fo=674, routed)Xh/݄?X1Y9 (CLOCK_ROOT) eag_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/RX_HEADER_LOCKED_O_reg/C JFDCEXhzr> Jclock pessimismXh c_g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].patternSearch/RX_HEADER_LOCKED_O_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhQ߆; J arrival timeXh ?/ JXh4 JslackXh J> +d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Ctpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu*\>}c\=z?c?+kT>D=im>j>p>(>"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xhim> tpg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) rng_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXh plg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh&?/ JXh4 JslackXh+kT>RPd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C}yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu*\>}c\=z?c?+kT>D=im>j>p>(>"?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= jfg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)Xhim> }yg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) {wg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C JFDCEXhzr> Jclock pessimismXh yug_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_regRemov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh&?/ JXh4 JslackXh+kT>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuz>}= s=z?= ?f>D=w>j>p>(>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhw> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[15]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhn?/ JXh4 JslackXhf>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuth>}KQ+=z?Q?r>O-D=q>j>p>(>?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhq> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh/݄?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXhO- g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhK; J arrival timeXh?/ JXh4 JslackXhr>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuS>}xP=z??)t>D=$>j>p>(>I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh$> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhz?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXh?/ JXh4 JslackXh)t>Rd`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZj_gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuS>}xP=z??)t>D=$>j>p>(>I?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})w(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47(DCD - SCD - CPR) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh$> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xho< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh\?X1Y9 (CLOCK_ROOT) d`g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[9].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhX9< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xhz?X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXh g_gbt_bank[3].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[9].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_EFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXh?/ JXh4 JslackXh)t>Rg_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu+?@}A%=+A1a#o+@1@A=А=[@BM>>&@TE?̼?1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh;@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/C JFDCEXhzr> Jclock pessimismXhBM>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh%=+A; J arrival timeXh/ JXh4 JslackXh[@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsu+?@}A%=+A1a#o+@1@A=А=[@BM>>&@TE?̼?1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh;@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/C JFDCEXhzr> Jclock pessimismXhBM>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh%=+A; J arrival timeXh/ JXh4 JslackXh[@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuQ>@}A 5+Al0h%o+@l@A=А=@GM>>?5&@TE?̼?1?Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh;@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/C JFDCEXhzr> Jclock pessimismXhGM>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 5+A; J arrival timeXh`/ JXh4 JslackXh@ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuQ>@}A 5+Al0h%o+@l@A=А=@GM>>?5&@TE?̼?1?Q?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @:g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR JFDCEXhzfe J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)Xhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh'= g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh;@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)n <8g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/C JFDCEXhzr> Jclock pessimismXhGM>@ Jclock uncertaintyXh :6g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh 5+A; J arrival timeXh`/ JXh4 JslackXh@ /g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsux9@}A+AS܇.o+@S@A=А=pۣ@_M>> @TE?̼?1?h?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh;@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh+?X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]/C JFDCEXhzr> Jclock pessimismXh_M>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXhE/ JXh4 JslackXhpۣ@ /g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuMb0@}A3A+A]"o+@@A=А=Ȩ@#@M>>;@TE?̼?1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh;@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xhb?X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/C JFDCEXhzr> Jclock pessimismXh#@M>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh3A+A; J arrival timeXh^/ JXh4 JslackXhȨ@ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuMb0@}A3A+A]"o+@@A=А=Ȩ@#@M>>;@TE?̼?1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh;@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xhb?X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/C JFDCEXhzr> Jclock pessimismXh#@M>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh3A+A; J arrival timeXh^/ JXh4 JslackXhȨ@ /g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuMb0@}A3A+A]"o+@@A=А=Ȩ@#@M>>;@TE?̼?1??z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh;@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xhb?X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/C JFDCEXhzr> Jclock pessimismXh#@M>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh3A+A; J arrival timeXh^/ JXh4 JslackXhȨ@ /g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuv/@}A9+Ad$o+@@A=А= @`EM>>d;@TE?̼?1?ٞ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh;@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/C JFDCEXhzr> Jclock pessimismXh`EM>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh9+A; J arrival timeXhsh/ JXh4 JslackXh @ 0g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR""RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1*X1Y92"RCLK_DSP_L_X27Y569/CLK_VDISTR_TOP1:X1Y9BJZ(LUT3=1)j_gtwiz_userclk_rx_srcclk_out[0]_47 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_47 rise@0.000nsuv/@}A9+Ad$o+@@A=А= @`EM>>d;@TE?̼?1?ٞ?z(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})x(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_47 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default**!gtwiz_userclk_rx_srcclk_out[0]_47!gtwiz_userclk_rx_srcclk_out[0]_47#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEM_C_Q JFDCEXhzrV> g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh? g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/I0 JXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2/OProp_D6LUT_SLICEM_I0_O JLUT3Xhzf"y> @ g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xh;@X1Y9 (CLOCK_ROOT) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzre J3(clock gtwiz_userclk_rx_srcclk_out[0]_47 rise edge)XhzrA g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh< g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> D@g_gbt_bank[3].gbtbank/bbstub_gtwiz_userclk_rx_usrclk_out[0]_6[0] Jnet (fo=674, routed)Xh?X1Y9 (CLOCK_ROOT)v D@g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/C JFDCEXhzr> Jclock pessimismXh`EM>@ Jclock uncertaintyXh B>g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]Recov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh9+A; J arrival timeXhsh/ JXh4 JslackXh @ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5!)y@1y @9Ay@Iy @ehx@hq}"W8>d rise - rise rise - rise  d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuˡ>} p=-? ?"W8>DD=Z>&>?r?S#?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZ> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/}?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C JFDCEXhzr> Jclock pessimismXhD g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[16]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh"W8>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuˡ>} p=-? ?"W8>DD=Z>&>?r?S#?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZ> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/}?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C JFDCEXhzr> Jclock pessimismXhD g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]Remov_AFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh"W8>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuˡ>} p=-? ?"W8>DD=Z>&>?r?S#?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZ> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/}?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C JFDCEXhzr> Jclock pessimismXhD g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[1]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh"W8>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuˡ>} p=-? ?"W8>DD=Z>&>?r?S#?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZ> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/}?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C JFDCEXhzr> Jclock pessimismXhD g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]Remov_BFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh"W8>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuˡ>} p=-? ?"W8>DD=Z>&>?r?S#?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZ> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/}?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C JFDCEXhzr> Jclock pessimismXhD g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[5]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh"W8>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuˡ>} p=-? ?"W8>DD=Z>&>?r?S#?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/QProp_HFF2_SLICEM_C_Q JFDCEXhzrD= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)XhZ> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh/}?X3Y1 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C JFDCEXhzr> Jclock pessimismXhD g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]Remov_CFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXh"W8>R62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu>} Jh=S? ?j?>D=Y>&>?r?S#?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhY>c 1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[32]/C JFDCEXhzr> Jclock pessimismXhz -)SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[32]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhj?>462SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu>} Jh=S? ?j?>D=Y>&>?r?S#?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhY>c 1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[34]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[34]/C JFDCEXhzr> Jclock pessimismXh{ -)SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[34]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhj?>462SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu>} Jh=S? ?j?>D=Y>&>?r?S#?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhY>c 1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[36]/C JFDCEXhzr> Jclock pessimismXhz -)SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[36]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhj?>462SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZj]gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu>} Jh=S? ?j?>D=Y>&>?r?S#?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5(DCD - SCD - CPR) 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[3].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhY>c 1-SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhe;?X3Y1 (CLOCK_ROOT)h 62SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[3].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhU?X3Y1 (CLOCK_ROOT)a /+SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[38]/C JFDCEXhzr> Jclock pessimismXh{ -)SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[38]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh?/ JXh4 JslackXhj?>4g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu0l@}Ad2At+rSc@t+@A=А=hx@>n>^Y@/? ?Nb??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhp-@ eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__2/I0 JXhzr d`g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__2/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf+> WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh&1? TPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhd2A; J arrival timeXh/ JXh4 JslackXhhx@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu0l@}Ad2At+rSc@t+@A=А=hx@>n>^Y@/? ?Nb??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xhp-@ eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__2/I0 JXhzr d`g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__2/OProp_B6LUT_SLICEL_I0_O JLUT2Xhzf+> WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)Xh&1? YUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT) WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh UQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhd2A; J arrival timeXh/ JXh4 JslackXhhx@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuj@}Ad2At+rSc@t+@A=А=y@>(>lW@/? ?Nb??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh֣? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)y GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh EAg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhd2A; J arrival timeXh"/ JXh4 JslackXhy@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsuj@}Ad2At+rSc@t+@A=А=y@>(>lW@/? ?Nb??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh֣? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhd2A; J arrival timeXh"/ JXh4 JslackXhy@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsua@}A1A"+Sc@"+@A=А=LN@>(>vN@/? ?Nb??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh֣? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhLN@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsua@}A1A"+Sc@"+@A=А=LN@>(>vN@/? ?Nb??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh֣? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1A; J arrival timeXh/ JXh4 JslackXhLN@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu]@}A2A+Sc@+@A=А=׫@>(>p=J@/? ?Nb??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh֣? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh-@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXhC/ JXh4 JslackXh׫@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu]@}A2A+Sc@+@A=А=׫@>(>p=J@/? ?Nb??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh֣? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh-@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXhC/ JXh4 JslackXh׫@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu]@}A2A+Sc@+@A=А=׫@>(>p=J@/? ?Nb??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh֣? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh-@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXhC/ JXh4 JslackXh׫@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR""RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0*X3Y12"RCLK_DSP_L_X59Y149/CLK_VDISTR_BOT0:X3Y1BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_5 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_5 rise@0.000nsu]@}A2A+Sc@+@A=А=׫@>(>p=J@/? ?Nb??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_5 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_5 gtwiz_userclk_rx_srcclk_out[0]_5#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh֣? g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2/OProp_A6LUT_SLICEL_I0_O JLUT3Xhzf)> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhD@X3Y1 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_5 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[3] Jnet (fo=674, routed)Xh-@X3Y1 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/C JFDCEXhzr> Jclock pessimismXh>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh2A; J arrival timeXhC/ JXh4 JslackXh׫@ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6!)y@1y @9Ay@Iy @eg&@hq}W^>d rise - rise rise - rise  RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[80]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuA5>}㍔KP=Ԉ?K?W^> 9H=>">S%? >IL?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[80]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhts?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[80]/C JFDCEXhzr> Jclock pessimismXh  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[80]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh㍔; J arrival timeXhNb?/ JXh4 JslackXhW^>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[89]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuA5>}㍔KP=Ԉ?K?W^> 9H=>">S%? >IL?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[89]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhts?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[89]/C JFDCEXhzr> Jclock pessimismXh  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[89]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh㍔; J arrival timeXhNb?/ JXh4 JslackXhW^>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[91]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuA5>}㍔KP=Ԉ?K?W^> 9H=>">S%? >IL?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[91]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhts?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[91]/C JFDCEXhzr> Jclock pessimismXh  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[91]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh㍔; J arrival timeXhNb?/ JXh4 JslackXhW^>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[96]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuA5>}㍔KP=Ԉ?K?W^> 9H=>">S%? >IL?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[96]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhts?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[96]/C JFDCEXhzr> Jclock pessimismXh  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[96]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh㍔; J arrival timeXhNb?/ JXh4 JslackXhW^>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[80]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuA5>}㍔KP=Ԉ?K?W^> 9H=>">S%? >IL?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[80]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhts?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[80]/C JFDCEXhzr> Jclock pessimismXh  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[80]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh㍔; J arrival timeXhNb?/ JXh4 JslackXhW^>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[89]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuA5>}㍔KP=Ԉ?K?W^> 9H=>">S%? >IL?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[89]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhts?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[89]/C JFDCEXhzr> Jclock pessimismXh  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[89]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh㍔; J arrival timeXhNb?/ JXh4 JslackXhW^>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[91]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuA5>}㍔KP=Ԉ?K?W^> 9H=>">S%? >IL?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[91]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhts?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[91]/C JFDCEXhzr> Jclock pessimismXh  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[91]Remov_FFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh㍔; J arrival timeXhNb?/ JXh4 JslackXhW^>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[96]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuA5>}㍔KP=Ԉ?K?W^> 9H=>">S%? >IL?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[96]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhts?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh-?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[96]/C JFDCEXhzr> Jclock pessimismXh  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[96]Remov_EFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh㍔; J arrival timeXhNb?/ JXh4 JslackXhW^>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[40]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuv>}ϔPn=Ԉ?P?ܦ_>8 9H=>">S%? >L?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[40]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhts?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhn?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[40]/C JFDCEXhzr> Jclock pessimismXh8  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[40]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhϔ; J arrival timeXhİ?/ JXh4 JslackXhܦ_>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[49]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuv>}ϔPn=Ԉ?P?ܦ_>8 9H=>">S%? >L?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[49]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xhts?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhn?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[49]/C JFDCEXhzr> Jclock pessimismXh8  c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[49]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhϔ; J arrival timeXhİ?/ JXh4 JslackXhܦ_>g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu23K@}A(0AE&4<"3@E&@A=А=g&@Od>5^>l3@*???I?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZd@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/C JFDCEXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh(0A; J arrival timeXh+/ JXh4 JslackXhg&@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu23K@}A(0AE&4<"3@E&@A=А=g&@Od>5^>l3@*???I?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZd@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/C JFDCEXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]Recov_DFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh(0A; J arrival timeXh+/ JXh4 JslackXhg&@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu23K@}A(0AE&4<"3@E&@A=А=g&@Od>5^>l3@*???I?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZd@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/C JFDCEXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]Recov_AFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh(0A; J arrival timeXh+/ JXh4 JslackXhg&@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu23K@}A(0AE&4<"3@E&@A=А=g&@Od>5^>l3@*???I?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZd@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/C JFDCEXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh(0A; J arrival timeXh+/ JXh4 JslackXhg&@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu+F@}A(0AE&4<"3@E&@A=А=k|@Od>5^>e;/@*???I?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZd@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/C JFDCEXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh(0A; J arrival timeXhԼ/ JXh4 JslackXhk|@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu+F@}A(0AE&4<"3@E&@A=А=k|@Od>5^>e;/@*???I?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZd@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/C JFDCEXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh(0A; J arrival timeXhԼ/ JXh4 JslackXhk|@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu+F@}A(0AE&4<"3@E&@A=А=k|@Od>5^>e;/@*???I?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZd@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/C JFDCEXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh(0A; J arrival timeXhԼ/ JXh4 JslackXhk|@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CTPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu~jD@}A/Aj$滵"3@j$@A=А=0@Od>~j>5@*???u?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh= @ eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__3/I0 JXhzr d`g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__3/OProp_D6LUT_SLICEL_I0_O JLUT2XhzfQ= WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhH? TPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/C JFDCEXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhƻ/ JXh4 JslackXh0@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CYUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT2=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsu~jD@}A/Aj$滵"3@j$@A=А=0@Od>~j>5@*???u?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> ieg_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh= @ eag_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__3/I0 JXhzr d`g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__3/OProp_D6LUT_SLICEL_I0_O JLUT2XhzfQ= WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 Jnet (fo=2, routed)XhH? YUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT) WSg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh UQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh/A; J arrival timeXhƻ/ JXh4 JslackXh0@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR""RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0*X4Y22"RCLK_DSP_L_X75Y209/CLK_VDISTR_BOT0:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_6 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_6 rise@0.000nsuTE@}A 0A$&<"3@$&@A=А=@Od>5^>.@*???2?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_6 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_6 gtwiz_userclk_rx_srcclk_out[0]_6#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhZd@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfgff> @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhk@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_6 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[4] Jnet (fo=674, routed)Xh @X4Y2 (CLOCK_ROOT)y GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/C JFDCEXhzr> Jclock pessimismXhOd>@ Jclock uncertaintyXh EAg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh 0A; J arrival timeXh/ JXh4 JslackXh@ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7!)y@1y @9Ay@Iy @e;}@hq}N-;>d rise - rise rise - rise  RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuSc>}ёԨ =̌?Ԩ?N-;>9=9H=&1>>.? >)\O?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh&1> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhF?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_reg/C JFDCEXhzr> Jclock pessimismXh9= c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/firstOut_regRemov_DFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhё; J arrival timeXhL7?/ JXh4 JslackXhN-;>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[20]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsud;>}ۅioS=̌?i?ZP>%{9H=$>>.? >X?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh$> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[20]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[20]/C JFDCEXhzr> Jclock pessimismXh%{ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[20]Remov_FFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhۅ; J arrival timeXh?/ JXh4 JslackXhZP>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsud;>}ۅioS=̌?i?ZP>%{9H=$>>.? >X?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh$> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]/C JFDCEXhzr> Jclock pessimismXh%{ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[21]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhۅ; J arrival timeXh?/ JXh4 JslackXhZP>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[22]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsud;>}ۅioS=̌?i?ZP>%{9H=$>>.? >X?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh$> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[22]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[22]/C JFDCEXhzr> Jclock pessimismXh%{ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[22]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhۅ; J arrival timeXh?/ JXh4 JslackXhZP>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsud;>}ۅioS=̌?i?ZP>%{9H=$>>.? >X?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh$> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]/C JFDCEXhzr> Jclock pessimismXh%{ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[21]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhۅ; J arrival timeXh?/ JXh4 JslackXhZP>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[22]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsud;>}ۅioS=̌?i?ZP>%{9H=$>>.? >X?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh$> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[22]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhr?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[22]/C JFDCEXhzr> Jclock pessimismXh%{ c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg1_reg[22]Remov_GFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhۅ; J arrival timeXh?/ JXh4 JslackXhZP>62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsut>}xƫ=?ƫ?sP>>D=u>>a0? >~?U?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhu>c 1-SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzr> Jclock pessimismXh>z -)SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[40]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXhв?/ JXh4 JslackXhsP>462SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsut>}xƫ=?ƫ?sP>>D=u>>a0? >~?U?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_GFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[5].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhu>c 1-SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh.}?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[5].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]/C JFDCEXhzr> Jclock pessimismXh>{ -)SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[42]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhx; J arrival timeXhв?/ JXh4 JslackXhsP>4RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuĠ>}ǚҭAq=̌?ҭ?߱Q>x9H=>>.? >XY?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh:?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]/C JFDCEXhzr> Jclock pessimismXhx c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[60]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhǚ; J arrival timeXh?/ JXh4 JslackXh߱Q>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[78]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuĠ>}ǚҭAq=̌?ҭ?߱Q>x9H=>>.? >XY?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_EFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)Xh> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[78]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh:?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[78]/C JFDCEXhzr> Jclock pessimismXhx c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[5].gbt_rxgearbox_inst/reg0_reg[78]Remov_CFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhǚ; J arrival timeXh?/ JXh4 JslackXh߱Q>g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuG@}A0A)g\=F3@)@A=А=;}@a>xi>{@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh C@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_A6LUT_SLICEM_I0_O JLUT3XhzfE= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh"/ JXh4 JslackXh;}@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuG@}A0A)g\=F3@)@A=А=;}@a>xi>{@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh C@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_A6LUT_SLICEM_I0_O JLUT3XhzfE= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh"/ JXh4 JslackXh;}@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuG@}A0A)g\=F3@)@A=А=;}@a>xi>{@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh C@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_A6LUT_SLICEM_I0_O JLUT3XhzfE= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh"/ JXh4 JslackXh;}@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsuG@}A0A)g\=F3@)@A=А=;}@a>xi>{@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh C@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_A6LUT_SLICEM_I0_O JLUT3XhzfE= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh"/ JXh4 JslackXh;}@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CIEg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsu@}A0A)=F3@)@A=А=@a>xi>s@q=*???o?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh C@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_A6LUT_SLICEM_I0_O JLUT3XhzfE= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)Xh'1@X4Y2 (CLOCK_ROOT)y GCg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh EAg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]Recov_DFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsua@}A0A8) y=F3@8)@A=А=@a>xi>33s@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh C@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_A6LUT_SLICEM_I0_O JLUT3XhzfE= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)Xhc@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]Recov_HFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsua@}A0A8) y=F3@8)@A=А=@a>xi>33s@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh C@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_A6LUT_SLICEM_I0_O JLUT3XhzfE= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)Xhc@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]Recov_GFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsua@}A0A8) y=F3@8)@A=А=@a>xi>33s@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh C@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_A6LUT_SLICEM_I0_O JLUT3XhzfE= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)Xhc@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]Recov_FFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsua@}A0A8) y=F3@8)@A=А=@a>xi>33s@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh C@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_A6LUT_SLICEM_I0_O JLUT3XhzfE= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)Xhc@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]Recov_HFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/CLR"#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1*X4Y22#RCLK_BRAM_L_X78Y209/CLK_VDISTR_BOT1:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_7 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_7 rise@0.000nsua@}A0A8) y=F3@8)@A=А=@a>xi>33s@q=*????y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_7 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_7 gtwiz_userclk_rx_srcclk_out[0]_7#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)Xh C@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2/OProp_A6LUT_SLICEM_I0_O JLUT3XhzfE= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)XhO@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_7 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[5] Jnet (fo=674, routed)Xhc@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]/C JFDCEXhzr> Jclock pessimismXha>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5]Recov_GFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh0A; J arrival timeXh/ JXh4 JslackXh@ B **async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8!)y@1y @9Ay@Iy @e@hq}^0>d rise - rise rise - rise  62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C-)SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu>}oE =Q?E?^0>TD=Y>>B`%?>J?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfD=m )%SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhY>_ -)SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhnr?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh&?X4Y2 (CLOCK_ROOT)] +'SFP_GEN[6].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhTv )%SFP_GEN[6].ngCCM_gbt/pwr_good_pre_regRemov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXho; J arrival timeXh?/ JXh4 JslackXh^0>4d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuO>}TI=n??{\;>##9H=rh>>?>B`%?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xhrh> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)Xh|?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C JFDCEXhzr> Jclock pessimismXh## g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]Remov_EFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhT; J arrival timeXh?/ JXh4 JslackXh{\;>RRNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[93]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuo>}3mVp=o??D>i9H=S>> ?>?5?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[93]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhaP?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhu?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[93]/C JFDCEXhzr> Jclock pessimismXhi c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[93]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh3m; J arrival timeXhQ?/ JXh4 JslackXhD>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[93]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuo>}3mVp=o??D>i9H=S>> ?>?5?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhS> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[93]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhaP?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xhu?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[93]/C JFDCEXhzr> Jclock pessimismXhi c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[93]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh3m; J arrival timeXhQ?/ JXh4 JslackXhD>$d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Ctpg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuq=>}e|nPRD=n?n?G^>&9H=Mb>>?>o#?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= jfg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/AR[0] Jnet (fo=82, routed)XhMb> tpg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/CLK Jnet (fo=674, routed)Xhz?X4Y2 (CLOCK_ROOT) rng_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_reg/C JFDCEXhzr> Jclock pessimismXh& plg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/READY_O_regRemov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhe|; J arrival timeXh?/ JXh4 JslackXhG^>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuP>}|Đqdž=n?Đ?,f>\9H=|>>?>x?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh|> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhKw?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C JFDCEXhzr> Jclock pessimismXh\ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh|; J arrival timeXhO?/ JXh4 JslackXh,f>Rd`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/Cg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuP>}|Đqdž=n?Đ?,f>\9H=|>>?>x?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzr9H= g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] Jnet (fo=82, routed)Xh|> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)XhףP?X4Y2 (CLOCK_ROOT) d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/READY_O_reg/C JFDCEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK Jnet (fo=674, routed)XhKw?X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C JFDCEXhzr> Jclock pessimismXh\ g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxdatapath_multilink_gen[6].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh|; J arrival timeXhO?/ JXh4 JslackXh,f>RRNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[61]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuq=>}9qzВ =o?В? g>19H=Mb>> ?> #?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[61]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhaP?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[61]/C JFDCEXhzr> Jclock pessimismXh1 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[61]Remov_HFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh9qz; J arrival timeXh?/ JXh4 JslackXh g>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Cgcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[63]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuq=>}9qzВ =o?В? g>19H=Mb>> ?> #?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[63]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhaP?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT) eag_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[63]/C JFDCEXhzr> Jclock pessimismXh1 c_g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg0_reg[63]Remov_GFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh9qz; J arrival timeXh?/ JXh4 JslackXh g>RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/Chdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[103]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsuq=>}9qzВ =o?В? g>19H=Mb>> ?> #?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8(DCD - SCD - CPR) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/QProp_AFF_SLICEL_C_Q JFDPEXhzf9H= gcg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/gbt_rxreset_s[0] Jnet (fo=225, routed)XhMb> hdg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[103]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= MIg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/RX_FRAMECLK_I Jnet (fo=674, routed)XhaP?X4Y2 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/C JFDPEXhzrd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> ZVg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/CLK Jnet (fo=674, routed)Xh[d{?X4Y2 (CLOCK_ROOT) fbg_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[103]/C JFDCEXhzr> Jclock pessimismXh1 d`g_gbt_bank[0].gbtbank/i_gbt_bank/gbt_rxgearbox_multilink_gen[6].gbt_rxgearbox_inst/reg1_reg[103]Remov_HFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh9qz; J arrival timeXh?/ JXh4 JslackXh g>l62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu #@}A+A#N>@#@A=А=@W/f>V>@)???F?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>m )%SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@c 1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> EASFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA @X4Y2 (CLOCK_ROOT)h 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]/C JFDCEXhzr> Jclock pessimismXhW/f>@ Jclock uncertaintyXhz -)SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh}?/ JXh4 JslackXh@4m62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu #@}A+A#N>@#@A=А=@W/f>V>@)???F?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>m )%SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@c 1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> EASFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA @X4Y2 (CLOCK_ROOT)h 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]/C JFDCEXhzr> Jclock pessimismXhW/f>@ Jclock uncertaintyXh{ -)SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh}?/ JXh4 JslackXh@4l62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu #@}A+A#N>@#@A=А=@W/f>V>@)???F?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>m )%SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@c 1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> EASFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA @X4Y2 (CLOCK_ROOT)h 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[60]/C JFDCEXhzr> Jclock pessimismXhW/f>@ Jclock uncertaintyXhz -)SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[60]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh}?/ JXh4 JslackXh@4m62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu #@}A+A#N>@#@A=А=@W/f>V>@)???F?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>m )%SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@c 1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> EASFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA @X4Y2 (CLOCK_ROOT)h 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[62]/C JFDCEXhzr> Jclock pessimismXhW/f>@ Jclock uncertaintyXh{ -)SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[62]Recov_CFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh}?/ JXh4 JslackXh@4l62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu #@}A+A#N>@#@A=А=@W/f>V>@)???F?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>m )%SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@c 1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> EASFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA @X4Y2 (CLOCK_ROOT)h 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]/C JFDCEXhzr> Jclock pessimismXhW/f>@ Jclock uncertaintyXhz -)SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh}?/ JXh4 JslackXh@4m62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu #@}A+A#N>@#@A=А=@W/f>V>@)???F?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>m )%SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@c 1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> EASFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA @X4Y2 (CLOCK_ROOT)h 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]/C JFDCEXhzr> Jclock pessimismXhW/f>@ Jclock uncertaintyXh{ -)SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]Recov_BFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh}?/ JXh4 JslackXh@4l62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu #@}A+A#N>@#@A=А=@W/f>V>@)???F?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>m )%SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@c 1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> EASFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA @X4Y2 (CLOCK_ROOT)h 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]/C JFDCEXhzr> Jclock pessimismXhW/f>@ Jclock uncertaintyXhz -)SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh}?/ JXh4 JslackXh@4m62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu #@}A+A#N>@#@A=А=@W/f>V>@)???F?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>m )%SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@c 1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> EASFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA @X4Y2 (CLOCK_ROOT)h 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]/C JFDCEXhzr> Jclock pessimismXhW/f>@ Jclock uncertaintyXh{ -)SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]Recov_AFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh+A; J arrival timeXh}?/ JXh4 JslackXh@4l62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu\@}A1+AMaﾵ>@M@A=А=Fȩ@f>V>@)????y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>m )%SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@c 1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[56]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> EASFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA @X4Y2 (CLOCK_ROOT)h 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[56]/C JFDCEXhzr> Jclock pessimismXhf>@ Jclock uncertaintyXhz -)SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[56]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1+A; J arrival timeXh/ JXh4 JslackXhFȩ@4m62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR"#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT*X4Y22#RCLK_CLE_M_L_X75Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_8 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_8 rise@0.000nsu\@}A1+AMaﾵ>@M@A=А=Fȩ@f>V>@)????y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_8 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_8 gtwiz_userclk_rx_srcclk_out[0]_8#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR) 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEL_C_Q JFDPEXhzfV>m )%SFP_GEN[6].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh@c 1-SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> EASFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhA @X4Y2 (CLOCK_ROOT)h 62SFP_GEN[6].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_8 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> 73SFP_GEN[6].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]/C JFDCEXhzr> Jclock pessimismXhf>@ Jclock uncertaintyXh{ -)SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[58]Recov_DFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh1+A; J arrival timeXh/ JXh4 JslackXhFȩ@4B **async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9!)y@1y @9Ay@Iy @eʇ@hq}Y >d rise - rise rise - rise  62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C0,SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu(\>}O=?O?Y >uD= +>>t3?X9>EV?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh +>b 0,SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1?X4Y2 (CLOCK_ROOT)` .*SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[0]/C JFDCEXhzr> Jclock pessimismXhuy ,(SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[0]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh ?/ JXh4 JslackXhY >462SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C0,SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu(\>}O=?O?Y >uD= +>>t3?X9>EV?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh +>b 0,SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1?X4Y2 (CLOCK_ROOT)` .*SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[2]/C JFDCEXhzr> Jclock pessimismXhuz ,(SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[2]Remov_HFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh ?/ JXh4 JslackXhY >462SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C0,SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu(\>}O=?O?Y >uD= +>>t3?X9>EV?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh +>b 0,SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1?X4Y2 (CLOCK_ROOT)` .*SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[4]/C JFDCEXhzr> Jclock pessimismXhuy ,(SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[4]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh ?/ JXh4 JslackXhY >462SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C0,SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu(\>}O=?O?Y >uD= +>>t3?X9>EV?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh +>b 0,SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh'1?X4Y2 (CLOCK_ROOT)` .*SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[6]/C JFDCEXhzr> Jclock pessimismXhuz ,(SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[6]Remov_GFF2_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXh ?/ JXh4 JslackXhY >462SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsun>};󭿭2f=??E>jD=p=>>t3?X9>PW?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhp=>c 1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[40]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhԘ?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[40]/C JFDCEXhzr> Jclock pessimismXhjz -)SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[40]Remov_DFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh;; J arrival timeXhҭ?/ JXh4 JslackXhE>462SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsun>};󭿭2f=??E>jD=p=>>t3?X9>PW?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xhp=>c 1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[42]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)XhԘ?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[42]/C JFDCEXhzr> Jclock pessimismXhj{ -)SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[42]Remov_DFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh;; J arrival timeXhҭ?/ JXh4 JslackXhE>462SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C-)SFP_GEN[7].ngCCM_gbt/pwr_good_pre_reg/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsumt>}m욿@5P=?@5? Y>TeD=C>>t3?X9>dX?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)XhC>_ -)SFP_GEN[7].ngCCM_gbt/pwr_good_pre_reg/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xh?X4Y2 (CLOCK_ROOT)] +'SFP_GEN[7].ngCCM_gbt/pwr_good_pre_reg/C JFDCEXhzr> Jclock pessimismXhTev )%SFP_GEN[7].ngCCM_gbt/pwr_good_pre_regRemov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXhm욿; J arrival timeXh?/ JXh4 JslackXh Y>462SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu>}㙿/ =?/?ϹT>LzD=!r>>t3?X9>V?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh!r>c 1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]/C JFDCEXhzr> Jclock pessimismXhLzz -)SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]Remov_AFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh㙿; J arrival timeXhz?/ JXh4 JslackXhϹT>462SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu>}㙿/ =?/?ϹT>LzD=!r>>t3?X9>V?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh!r>c 1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/C JFDCEXhzr> Jclock pessimismXhLz{ -)SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]Remov_AFF2_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh㙿; J arrival timeXhz?/ JXh4 JslackXhϹT>462SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZj]gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu>}㙿/ =?/?ϹT>LzD=!r>>t3?X9>V?y(rising edge-triggered cell FDPE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})v(removal check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9(DCD - SCD - CPR) 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/QProp_CFF2_SLICEM_C_Q JFDPEXhzfD=m )%SFP_GEN[7].ngCCM_gbt/sync_m_reg[3][0] Jnet (fo=52, routed)Xh!r>c 1-SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xht< g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr= EASFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xha?X4Y2 (CLOCK_ROOT)h 62SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_m_reg[3]/C JFDPEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh)\= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> 73SFP_GEN[7].ngCCM_gbt/gtwiz_userclk_rx_usrclk_out[0] Jnet (fo=674, routed)Xhc?X4Y2 (CLOCK_ROOT)a /+SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]/C JFDCEXhzr> Jclock pessimismXhLzz -)SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]Remov_BFF_SLICEM_C_CLR JFDCEXh ף;/ JXh< J required timeXh㙿; J arrival timeXhz?/ JXh4 JslackXhϹT>4g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu+~@}AI1A*I=> 7@*@A=А=ʇ@ c>~j> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)XhX@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhI1A; J arrival timeXh/ JXh4 JslackXhʇ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu+~@}AI1A*I=> 7@*@A=А=ʇ@ c>~j> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)XhX@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhI1A; J arrival timeXh/ JXh4 JslackXhʇ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu+~@}AI1A*I=> 7@*@A=А=ʇ@ c>~j> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)XhX@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhI1A; J arrival timeXh/ JXh4 JslackXhʇ@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuT}@}ArA1A!*<> 7@!*@A=А= @ c>~j>e;o@.?#?v?23?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)XhK7@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhrA1A; J arrival timeXhv/ JXh4 JslackXh @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuT}@}ArA1A!*<> 7@!*@A=А= @ c>~j>e;o@.?#?v?23?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)XhK7@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhrA1A; J arrival timeXhv/ JXh4 JslackXh @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C>:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsuT}@}ArA1A!*<> 7@!*@A=А= @ c>~j>e;o@.?#?v?23?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @:g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR JFDCEXhzfd J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)Xhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)Xh5^= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)XhK7@X4Y2 (CLOCK_ROOT)n <8g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXh :6g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhrA1A; J arrival timeXhv/ JXh4 JslackXh @  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu[b@}ArA1A!*<> 7@!*@A=А=@ c>~j>lS@.?#?v?23?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)XhK7@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]Recov_CFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhrA1A; J arrival timeXh/ JXh4 JslackXh@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu[b@}ArA1A!*<> 7@!*@A=А=@ c>~j>lS@.?#?v?23?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)XhK7@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]Recov_CFF2_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhrA1A; J arrival timeXh/ JXh4 JslackXh@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsu[b@}ArA1A!*<> 7@!*@A=А=@ c>~j>lS@.?#?v?23?y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)XhK7@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]Recov_BFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXhrA1A; J arrival timeXh/ JXh4 JslackXh@  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/CFBg_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR"$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT*X4Y22$RCLK_CLEL_R_L_X76Y209/CLK_VDISTR_BOT:X4Y2BJZ(LUT3=1)j]gtwiz_userclk_rx_srcclk_out[0]_9 rise@8.317ns - gtwiz_userclk_rx_srcclk_out[0]_9 rise@0.000nsub@}A@91A\*G<> 7@\*@A=А= ߕ@ c>~j>tS@.?#?v??y(rising edge-triggered cell FDCE clocked by gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})w(recovery check against rising-edge clock gtwiz_userclk_rx_srcclk_out[0]_9 {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** gtwiz_userclk_rx_srcclk_out[0]_9 gtwiz_userclk_rx_srcclk_out[0]_9#((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE(DCD - SCD + CPR)  g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/QProp_EFF_SLICEL_C_Q JFDCEXhzrV> g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gtwiz_reset_rx_done_out[0] Jnet (fo=32, routed)XhF@ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/I0 JXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2/OProp_C6LUT_SLICEM_I0_O JLUT3XhzfQ= @ g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/gtwiz_userclk_rx_usrclk2_out[0] Jnet (fo=674, routed)Xhף@X4Y2 (CLOCK_ROOT) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_rx_done_inst/rst_in_out_reg/C JFDCEXhzr d J2(clock gtwiz_userclk_rx_srcclk_out[0]_9 rise edge)XhzrA g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK J GTHE3_CHANNELXhzr g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_srcclk_out[0] Jnet (fo=2, routed)XhT= g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/I JXh g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/OProp_BUFG_GT_I_O JBUFG_GTXhzr&> )%g_gbt_bank[0].gbtbank/RX_WORDCLK_O[7] Jnet (fo=674, routed)Xh@X4Y2 (CLOCK_ROOT)v D@g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/C JFDCEXhzr> Jclock pessimismXh c>@ Jclock uncertaintyXh B>g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]Recov_EFF_SLICEM_C_CLR JFDCEXhv/ JXh< J required timeXh@91A; J arrival timeXhu/ JXh4 JslackXh ߕ@  **async_default**ipb_clkipb_clk!)/@1?@9A/@I?@e{Ahq}",E?"d rise - rise rise - rise  ] i_pwrup_rst/CLKtimer_reg[4]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsufff?}~Kǿ^d=$?K?,E? x>'1(?(?gff>~?d(rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default**ipb_clkipb_clk(DCD - SCD - CPR)d  i_pwrup_rst/QProp_A6LUT_SLICEM_CLK_Q JSRL16EXhzf`P>P  pwrup_rst Jnet (fo=1, routed)Xh><  rst_i_2/I0 JXhzf]  rst_i_2/OProp_H5LUT_SLICEL_I0_O JLUT2Xhzfw=P rst_dbl0 Jnet (fo=34, routed)Xh/]>F timer_reg[4]/CLR JFDCEXhzfK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh$?X2Y4 (CLOCK_ROOT)G i_pwrup_rst/CLK JSRL16EXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)XhK?X2Y4 (CLOCK_ROOT)D timer_reg[4]/C JFDCEXhzr> Jclock pessimismXh ]  timer_reg[4]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh~; J arrival timeXh @/ JXh4 JslackXh,E?"] i_pwrup_rst/CLKtimer_reg[5]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsufff?}~Kǿ^d=$?K?,E? x>'1(?(?gff>~?d(rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default**ipb_clkipb_clk(DCD - SCD - CPR)d  i_pwrup_rst/QProp_A6LUT_SLICEM_CLK_Q JSRL16EXhzf`P>P  pwrup_rst Jnet (fo=1, routed)Xh><  rst_i_2/I0 JXhzf]  rst_i_2/OProp_H5LUT_SLICEL_I0_O JLUT2Xhzfw=P rst_dbl0 Jnet (fo=34, routed)Xh/]>F timer_reg[5]/CLR JFDCEXhzfK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh$?X2Y4 (CLOCK_ROOT)G i_pwrup_rst/CLK JSRL16EXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)XhK?X2Y4 (CLOCK_ROOT)D timer_reg[5]/C JFDCEXhzr> Jclock pessimismXh ]  timer_reg[5]Remov_FFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh~; J arrival timeXh @/ JXh4 JslackXh,E?"] i_pwrup_rst/CLKtimer_reg[6]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsufff?}~Kǿ^d=$?K?,E? x>'1(?(?gff>~?d(rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default**ipb_clkipb_clk(DCD - SCD - CPR)d  i_pwrup_rst/QProp_A6LUT_SLICEM_CLK_Q JSRL16EXhzf`P>P  pwrup_rst Jnet (fo=1, routed)Xh><  rst_i_2/I0 JXhzf]  rst_i_2/OProp_H5LUT_SLICEL_I0_O JLUT2Xhzfw=P rst_dbl0 Jnet (fo=34, routed)Xh/]>F timer_reg[6]/CLR JFDCEXhzfK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh$?X2Y4 (CLOCK_ROOT)G i_pwrup_rst/CLK JSRL16EXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)XhK?X2Y4 (CLOCK_ROOT)D timer_reg[6]/C JFDCEXhzr> Jclock pessimismXh ]  timer_reg[6]Remov_GFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh~; J arrival timeXh @/ JXh4 JslackXh,E?"] i_pwrup_rst/CLKtimer_reg[7]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsufff?}~Kǿ^d=$?K?,E? x>'1(?(?gff>~?d(rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default**ipb_clkipb_clk(DCD - SCD - CPR)d  i_pwrup_rst/QProp_A6LUT_SLICEM_CLK_Q JSRL16EXhzf`P>P  pwrup_rst Jnet (fo=1, routed)Xh><  rst_i_2/I0 JXhzf]  rst_i_2/OProp_H5LUT_SLICEL_I0_O JLUT2Xhzfw=P rst_dbl0 Jnet (fo=34, routed)Xh/]>F timer_reg[7]/CLR JFDCEXhzfK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh$?X2Y4 (CLOCK_ROOT)G i_pwrup_rst/CLK JSRL16EXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)XhK?X2Y4 (CLOCK_ROOT)D timer_reg[7]/C JFDCEXhzr> Jclock pessimismXh ]  timer_reg[7]Remov_HFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh~; J arrival timeXh @/ JXh4 JslackXh,E?"] i_pwrup_rst/CLKtimer_reg[0]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsug?}ᶿǿ>$??wuF? x>^)?(?gff>H?d(rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default**ipb_clkipb_clk(DCD - SCD - CPR)d  i_pwrup_rst/QProp_A6LUT_SLICEM_CLK_Q JSRL16EXhzf`P>P  pwrup_rst Jnet (fo=1, routed)Xh><  rst_i_2/I0 JXhzf]  rst_i_2/OProp_H5LUT_SLICEL_I0_O JLUT2Xhzfw=P rst_dbl0 Jnet (fo=34, routed)XhSc>F timer_reg[0]/CLR JFDCEXhzfK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh$?X2Y4 (CLOCK_ROOT)G i_pwrup_rst/CLK JSRL16EXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh?X2Y4 (CLOCK_ROOT)D timer_reg[0]/C JFDCEXhzr> Jclock pessimismXh ]  timer_reg[0]Remov_AFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhᶿ; J arrival timeXhU @/ JXh4 JslackXhwuF?"] i_pwrup_rst/CLKtimer_reg[1]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsug?}ᶿǿ>$??wuF? x>^)?(?gff>H?d(rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default**ipb_clkipb_clk(DCD - SCD - CPR)d  i_pwrup_rst/QProp_A6LUT_SLICEM_CLK_Q JSRL16EXhzf`P>P  pwrup_rst Jnet (fo=1, routed)Xh><  rst_i_2/I0 JXhzf]  rst_i_2/OProp_H5LUT_SLICEL_I0_O JLUT2Xhzfw=P rst_dbl0 Jnet (fo=34, routed)XhSc>F timer_reg[1]/CLR JFDCEXhzfK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh$?X2Y4 (CLOCK_ROOT)G i_pwrup_rst/CLK JSRL16EXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh?X2Y4 (CLOCK_ROOT)D timer_reg[1]/C JFDCEXhzr> Jclock pessimismXh ]  timer_reg[1]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhᶿ; J arrival timeXhU @/ JXh4 JslackXhwuF?"] i_pwrup_rst/CLKtimer_reg[2]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsug?}ᶿǿ>$??wuF? x>^)?(?gff>H?d(rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default**ipb_clkipb_clk(DCD - SCD - CPR)d  i_pwrup_rst/QProp_A6LUT_SLICEM_CLK_Q JSRL16EXhzf`P>P  pwrup_rst Jnet (fo=1, routed)Xh><  rst_i_2/I0 JXhzf]  rst_i_2/OProp_H5LUT_SLICEL_I0_O JLUT2Xhzfw=P rst_dbl0 Jnet (fo=34, routed)XhSc>F timer_reg[2]/CLR JFDCEXhzfK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh$?X2Y4 (CLOCK_ROOT)G i_pwrup_rst/CLK JSRL16EXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh?X2Y4 (CLOCK_ROOT)D timer_reg[2]/C JFDCEXhzr> Jclock pessimismXh ]  timer_reg[2]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhᶿ; J arrival timeXhU @/ JXh4 JslackXhwuF?"] i_pwrup_rst/CLKtimer_reg[3]/PRE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsug?}ᶿǿ>$??wuF? x>^)?(?gff>H?d(rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default**ipb_clkipb_clk(DCD - SCD - CPR)d  i_pwrup_rst/QProp_A6LUT_SLICEM_CLK_Q JSRL16EXhzf`P>P  pwrup_rst Jnet (fo=1, routed)Xh><  rst_i_2/I0 JXhzf]  rst_i_2/OProp_H5LUT_SLICEL_I0_O JLUT2Xhzfw=P rst_dbl0 Jnet (fo=34, routed)XhSc>F timer_reg[3]/PRE JFDPEXhzfK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh$?X2Y4 (CLOCK_ROOT)G i_pwrup_rst/CLK JSRL16EXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh?X2Y4 (CLOCK_ROOT)D timer_reg[3]/C JFDPEXhzr> Jclock pessimismXh ]  timer_reg[3]Remov_DFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhᶿ; J arrival timeXhU @/ JXh4 JslackXhwuF?"a i_pwrup_rst/CLKtimer_reg[12]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsu(\o?}QȿN>$?Q?gL?$p x>&1?(?gff>?d(rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default**ipb_clkipb_clk(DCD - SCD - CPR)d  i_pwrup_rst/QProp_A6LUT_SLICEM_CLK_Q JSRL16EXhzf`P>P  pwrup_rst Jnet (fo=1, routed)Xh><  rst_i_2/I0 JXhzf]  rst_i_2/OProp_H5LUT_SLICEL_I0_O JLUT2Xhzfw=P rst_dbl0 Jnet (fo=34, routed)Xh>G timer_reg[12]/CLR JFDCEXhzfK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh$?X2Y4 (CLOCK_ROOT)G i_pwrup_rst/CLK JSRL16EXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)XhQ?X2Y4 (CLOCK_ROOT)E timer_reg[12]/C JFDCEXhzr> Jclock pessimismXh$p ^  timer_reg[12]Remov_EFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXh; J arrival timeXhy@/ JXh4 JslackXhgL?"a i_pwrup_rst/CLKtimer_reg[13]/PRE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j+ipb_clk rise@0.000ns - ipb_clk rise@0.000nsu(\o?}QȿN>$?Q?gL?$p x>&1?(?gff>?d(rising edge-triggered cell SRL16E clocked by ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})_(removal check against rising-edge clock ipb_clk {rise@0.000ns fall@16.000ns period=32.000ns})Fast**async_default**ipb_clkipb_clk(DCD - SCD - CPR)d  i_pwrup_rst/QProp_A6LUT_SLICEM_CLK_Q JSRL16EXhzf`P>P  pwrup_rst Jnet (fo=1, routed)Xh><  rst_i_2/I0 JXhzf]  rst_i_2/OProp_H5LUT_SLICEL_I0_O JLUT2Xhzfw=P rst_dbl0 Jnet (fo=34, routed)Xh>G timer_reg[13]/PRE JFDPEXhzfK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)Xh$?X2Y4 (CLOCK_ROOT)G i_pwrup_rst/CLK JSRL16EXhzrK J(clock ipb_clk rise edge)XhzrN i_ipb_clk_bufg/O JBUFGCEXhzrc CLK Jnet (fo=204776, routed)XhQ?X2Y4 (CLOCK_ROOT)E timer_reg[13]/C JFDPEXhzr> Jclock pessimismXh$p ^  timer_reg[13]Remov_FFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh; J arrival timeXhy@/ JXh4 JslackXhgL?" i_pwrup_rst/CLK rst_reg/PRE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuC#@}B,h BnRGTe@nR@Bڭ=А=>{A@kw>lG??c? Jclock pessimismXh@kw>@ Jclock uncertaintyXhڭY rst_regRecov_AFF2_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh,h B; J arrival timeXht/ JXh4 JslackXh{A" i_pwrup_rst/CLKtimer_reg[24]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuw@}B!e Bq=R2օTe@q=R@Bڭ=А=>0Asw>lG??c? Jclock pessimismXhsw>@ Jclock uncertaintyXhڭ^  timer_reg[24]Recov_AFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh!e B; J arrival timeXhff/ JXh4 JslackXh0A" i_pwrup_rst/CLKtimer_reg[25]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuw@}B!e Bq=R2օTe@q=R@Bڭ=А=>0Asw>lG??c? Jclock pessimismXhsw>@ Jclock uncertaintyXhڭ^  timer_reg[25]Recov_BFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh!e B; J arrival timeXhff/ JXh4 JslackXh0A" i_pwrup_rst/CLKtimer_reg[26]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuw@}B!e Bq=R2օTe@q=R@Bڭ=А=>0Asw>lG??c? Jclock pessimismXhsw>@ Jclock uncertaintyXhڭ^  timer_reg[26]Recov_CFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh!e B; J arrival timeXhff/ JXh4 JslackXh0A" i_pwrup_rst/CLKtimer_reg[27]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuw@}B!e Bq=R2օTe@q=R@Bڭ=А=>0Asw>lG??c? Jclock pessimismXhsw>@ Jclock uncertaintyXhڭ^  timer_reg[27]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh!e B; J arrival timeXhff/ JXh4 JslackXh0A" i_pwrup_rst/CLKtimer_reg[28]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuE@}Bc BRc䉽Te@R@Bڭ=А=>AAXxw>lG??c? Jclock pessimismXhXxw>@ Jclock uncertaintyXhڭ^  timer_reg[28]Recov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhc B; J arrival timeXh{/ JXh4 JslackXhAA" i_pwrup_rst/CLKtimer_reg[29]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuE@}Bc BRc䉽Te@R@Bڭ=А=>AAXxw>lG??c? Jclock pessimismXhXxw>@ Jclock uncertaintyXhڭ^  timer_reg[29]Recov_FFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhc B; J arrival timeXh{/ JXh4 JslackXhAA" i_pwrup_rst/CLKtimer_reg[30]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuE@}Bc BRc䉽Te@R@Bڭ=А=>AAXxw>lG??c? Jclock pessimismXhXxw>@ Jclock uncertaintyXhڭ^  timer_reg[30]Recov_GFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhc B; J arrival timeXh{/ JXh4 JslackXhAA" i_pwrup_rst/CLKtimer_reg[31]/CLR"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsuE@}Bc BRc䉽Te@R@Bڭ=А=>AAXxw>lG??c? Jclock pessimismXhXxw>@ Jclock uncertaintyXhڭ^  timer_reg[31]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhc B; J arrival timeXh{/ JXh4 JslackXhAA" i_pwrup_rst/CLKtimer_reg[16]/PRE"$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X38Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j,ipb_clk rise@32.000ns - ipb_clk rise@0.000nsux@}B!e Bq=R2օTe@q=R@Bڭ=А=>Asw>lG?e;?c? Jclock pessimismXhsw>@ Jclock uncertaintyXhڭ^  timer_reg[16]Recov_AFF_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXh!e B; J arrival timeXh/ JXh4 JslackXhA" **async_default** tx_wordclk tx_wordclk!)M@1M @9AM@IM @e?hq}V=Vd rise - rise rise - rise  e YUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/CTPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu>}pͿ}?տn>~?}??=+o=M>>?n>ף?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) YUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/QProp_EFF2_SLICEM_C_Q JFDPEXhzfD= SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRstMgtClk_sync_s Jnet (fo=1, routed)Xht=~ PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0/I0 JXhzf OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfo< PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0__0 Jnet (fo=1, routed)Xh(> TPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE JFDPEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh~?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh}??X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr> Jclock pessimismXh+ PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_regRemov_EFF_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhpͿ; J arrival timeXhj?/ JXh4 JslackXh= [Wg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/CTPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu!Zd>}gʿr{<??@>>o=">>v~?n>?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) [Wg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/QProp_AFF2_SLICEM_C_Q JFDPEXhzf9H= UQg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s Jnet (fo=1, routed)Xh+=~ PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0/I1 JXhzf OKg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0/OProp_C6LUT_SLICEM_I1_O JLUT3Xhzfu< PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0__0 Jnet (fo=1, routed)Xh%> TPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE JFDPEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh?X2Y4 (CLOCK_ROOT) [Wg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr> Jclock pessimismXh> PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_regRemov_EFF_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhg; J arrival timeXh ?/ JXh4 JslackXh@>e YUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/CTPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu`>}#aŊ=?a?-H> %=R>>m?n>I?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) YUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/QProp_EFF2_SLICEL_C_Q JFDPEXhzfD= SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s Jnet (fo=1, routed)Xh<~ PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0/I0 JXhzf OKg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0/OProp_G6LUT_SLICEL_I0_O JLUT3Xhzfu< PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0__0 Jnet (fo=1, routed)Xh333> TPg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE JFDPEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xha?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr> Jclock pessimismXh  PLg_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_regRemov_AFF_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXh#; J arrival timeXh?/ JXh4 JslackXh-H>e YUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/CTPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu~j>}rȿAп)>\?A?UI>+=L7>>Ђ?n>䥛?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) YUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/QProp_EFF2_SLICEL_C_Q JFDPEXhzfD= SOg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRstMgtClk_sync_s Jnet (fo=1, routed)Xh=~ PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0/I0 JXhzf OKg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0/OProp_H6LUT_SLICEL_I0_O JLUT3XhzfT= PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0__0 Jnet (fo=1, routed)Xh> TPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE JFDPEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh\?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] YUg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)XhA?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr> Jclock pessimismXh+ PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_regRemov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhrȿ; J arrival timeXh?/ JXh4 JslackXhUI> YUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/CTPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuC>}Фk4K=1?k?BP>5|o=T>>vX?n> ?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) YUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/QProp_EFF2_SLICEM_C_Q JFDPEXhzfD= SOg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s Jnet (fo=1, routed)Xht=~ PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0/I0 JXhzf OKg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0/OProp_H6LUT_SLICEM_I0_O JLUT3Xhzfo< PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0__0 Jnet (fo=1, routed)Xh 0> TPg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE JFDPEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh1?X2Y4 (CLOCK_ROOT) YUg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xhk?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr> Jclock pessimismXh5| PLg_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_regRemov_EFF_SLICEM_C_PRE JFDPEXh ף;/ JXh< J required timeXhФ; J arrival timeXhپ?/ JXh4 JslackXhBP> RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[10]/PRE"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsul>}AB`!>Zd?B`?[P>Q89H=Т>>KW?n>Ā?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/gbt_txreset_s[0] Jnet (fo=227, routed)XhТ> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[10]/PRE JFDPEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)XhZd?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)XhB`?X2Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[10]/C JFDPEXhzr> Jclock pessimismXhQ8 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[10]Remov_HFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXhA; J arrival timeXh5^?/ JXh4 JslackXh[P> RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[12]/CLR"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu>}ףµ/$>Zd?µ?V>Q89H=y>>KW?n>&?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/gbt_txreset_s[0] Jnet (fo=227, routed)Xhy> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[12]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)XhZd?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xhµ?X2Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[12]/C JFDCEXhzr> Jclock pessimismXhQ8 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[12]Remov_CFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhף; J arrival timeXhZd?/ JXh4 JslackXhV> RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[14]/CLR"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsu>}ףµ/$>Zd?µ?V>Q89H=y>>KW?n>&?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf9H= g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/gbt_txreset_s[0] Jnet (fo=227, routed)Xhy> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[14]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)XhZd?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xhµ?X2Y4 (CLOCK_ROOT) g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[14]/C JFDCEXhzr> Jclock pessimismXhQ8 g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[3].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[3].gbtTxScrambler21bit/feedbackRegister_reg[14]Remov_BFF_SLICEL_C_CLR JFDCEXh ף;/ JXh< J required timeXhף; J arrival timeXhZd?/ JXh4 JslackXhV>m [Wg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/CTPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuP>}|(i=?(?Z> %=n>>hff?n>P?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) [Wg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/QProp_EFF2_SLICEL_C_Q JFDPEXhzfD= UQg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s Jnet (fo=1, routed)Xh<~ PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0/I1 JXhzf OKg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0/OProp_G6LUT_SLICEL_I1_O JLUT3Xhzfu< PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0__0 Jnet (fo=1, routed)XhN> TPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE JFDPEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] [Wg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh(?X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr> Jclock pessimismXh  PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_regRemov_AFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh|; J arrival timeXh?/ JXh4 JslackXhZ> YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/CTPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT3=1)j1tx_wordclk rise@0.000ns - tx_wordclk rise@0.000nsuK >}"WͿ=%?W?15[>|<= #>>G?n>r?c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})`(removal check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Fast**async_default** tx_wordclk tx_wordclk(DCD - SCD - CPR) YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/QProp_AFF2_SLICEL_C_Q JFDPEXhzf9H= SOg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s Jnet (fo=1, routed)XhC =~ PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0/I0 JXhzf OKg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0/OProp_G6LUT_SLICEL_I0_O JLUT3XhzfQ8= PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0__0 Jnet (fo=1, routed)Xh%> TPg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE JFDPEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh%?X2Y4 (CLOCK_ROOT) YUg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRstMgtClk_sync_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)XhW?X2Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/C JFDPEXhzr> Jclock pessimismXh|< PLg_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_regRemov_EFF_SLICEL_C_PRE JFDPEXh ף;/ JXh< J required timeXh"; J arrival timeXh8?/ JXh4 JslackXh15[>B[Wg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/CTPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZ(LUT2=1)j1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuQ@}oAH!.A?ҡU@?@oA=А=$WN>?=l>#۱@~j|?S@+g?@c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) Ѡ%?@-+g?5 [Wg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/QProp_EFF2_SLICEM_C_Q JFDPEXhzfO > UQg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s Jnet (fo=1, routed)XhZd@D JXhSLR Crossing[0->1] VRg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1__2/I1 JXhzf UQg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1__2/OProp_G5LUT_SLICEL_I1_O JLUT2Xhzf7A> MIg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s0 Jnet (fo=1, routed)Xhl> TPg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE JFDPEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)XhU@X2Y4 (CLOCK_ROOT) [Wg_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh?@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/C JFDPEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhѠ@ Jclock uncertaintyXhڽ PLg_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_regRecov_EFF_SLICEL_C_PRE JFDPEXhv/ JXh< J required timeXhH!.A; J arrival timeXh/ JXh4 JslackXh? RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C~zg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[108]/CLR"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuI@}oA4A-Eڣ0+w@-E@oA=А=$WN>7@=)\>Χ@~j|?c8@+g?l @c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)XhΧ@ ~zg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[108]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh+w@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27439, routed)Xh-E@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[108]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽ zvg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[108]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh4A; J arrival timeXh/ JXh4 JslackXh7@| RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/Ckgg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/TX_WORD_O_reg[3]/CLR"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu@}oAz4AhE&1+w@hE@oA=А=$WN>EG@=)\>|@~j|?c8@+g? @c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xh|@ kgg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/TX_WORD_O_reg[3]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh+w@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27439, routed)XhhE@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] ieg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/TX_WORD_O_reg[3]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽ gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/TX_WORD_O_reg[3]Recov_HFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhz4A; J arrival timeXh/ JXh4 JslackXhEG@ RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C}yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[23]/CLR"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu@}oAz4AhE&1+w@hE@oA=А=$WN>EG@=)\>|@~j|?c8@+g? @c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xh|@ }yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[23]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh+w@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27439, routed)XhhE@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[23]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽ yug_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[23]Recov_HFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhz4A; J arrival timeXh/ JXh4 JslackXhEG@ RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C}yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[63]/CLR"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu@}oAz4AhE&1+w@hE@oA=А=$WN>EG@=)\>|@~j|?c8@+g? @c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xh|@ }yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[63]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh+w@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27439, routed)XhhE@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[63]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽ yug_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[63]Recov_GFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhz4A; J arrival timeXh/ JXh4 JslackXhEG@nRNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/Cg_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[2]/CLR"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu\@}oA4Aw_; >-R@w_@oA=А=$WN>^@=V>@~j|?o@+g?%@c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) s$Ǿ%w_@-+g?5 RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_EFF_SLICEM_C_Q JFDPEXhzfV> g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/gbt_txreset_s[0] Jnet (fo=227, routed)Xh@D JXhSLR Crossing[0->1] g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[2]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh-R@X2Y4 (CLOCK_ROOT) RNg_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/tx_wordclk Jnet (fo=27439, routed)Xhw_@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[2]/C JFDCEXhzr> Jclock pessimismXh=E Jinter-SLR compensationXhs$Ǿ@ Jclock uncertaintyXhڽ g_gbt_bank[2].gbtbank/i_gbt_bank/gbt_txdatapath_multilink_gen[0].gbt_txdatapath_inst/scrambler/gbtTxScrambler84bit_gen[1].gbtTxScrambler21bit/feedbackRegister_reg[2]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh4A; J arrival timeXh/ JXh4 JslackXh^@ RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C~zg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[118]/CLR"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsu#@}oA [4AD4+w@D@oA=А=$WN>4@=)\>C@~j|?c8@+g? @c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)XhC@ ~zg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[118]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh+w@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27439, routed)XhD@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] |xg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[118]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽ zvg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[118]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh [4A; J arrival timeXhM/ JXh4 JslackXh4@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_aligned_o_reg/CUQg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuS@}oA>4ADOm)\@D@oA=А=$WN>f@$=O >x@~j|?G@+g?" @c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_aligned_o_reg/QProp_HFF_SLICEL_C_Q JFDREXhzrO > XTg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg_0 Jnet (fo=15, routed)Xhx@ UQg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_wordclk Jnet (fo=27439, routed)Xh)\@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_aligned_o_reg/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr KGg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)XhD@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] SOg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_s_reg/C JFDCEXhzr> Jclock pessimismXh$=@ Jclock uncertaintyXhڽ QMg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_s_regRecov_EFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh>4A; J arrival timeXh/ JXh4 JslackXhf@ g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_aligned_o_reg/CZVg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuS@}oA>4ADOm)\@D@oA=А=$WN>f@$=O >x@~j|?G@+g?" @c(rising edge-triggered cell FDRE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_aligned_o_reg/QProp_HFF_SLICEL_C_Q JFDREXhzrO > XTg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg_0 Jnet (fo=15, routed)Xhx@ ZVg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_wordclk Jnet (fo=27439, routed)Xh)\@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/tx_aligned_o_reg/C JFDREXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr KGg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)XhD@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] XTg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/C JFDCEXhzr> Jclock pessimismXh$=@ Jclock uncertaintyXhڽ VRg_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtTxReady_sync_s_regRecov_EFF2_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXh>4A; J arrival timeXh/ JXh4 JslackXhf@ RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C}yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[92]/CLR"$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT*X2Y42$RCLK_CLEL_R_L_X46Y329/CLK_VDISTR_BOT:X2Y4BJZj1tx_wordclk rise@8.317ns - tx_wordclk rise@0.000nsuX@}oAz4AhE&1+w@hE@oA=А=$WN>Æ@=)\>/ݤ@~j|?c8@+g? @c(rising edge-triggered cell FDPE clocked by tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})a(recovery check against rising-edge clock tx_wordclk {rise@0.000ns fall@4.159ns period=8.317ns})Slow**async_default** tx_wordclk tx_wordclk((TSJ^2 + DJ^2)^1/2) / 2 + PE(DCD - SCD + CPR) RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/QProp_AFF_SLICEM_C_Q JFDPEXhzf)\> gcg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/gbt_txreset_s[0] Jnet (fo=227, routed)Xh/ݤ@ }yg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[92]/CLR JFDCEXhzfN J(clock tx_wordclk rise edge)XhzrO tx_wordclk_bufg/O JBUFGCEXhzr JFg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/tx_wordclk Jnet (fo=27439, routed)Xh+w@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] RNg_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/C JFDPEXhzrN J(clock tx_wordclk rise edge)XhzroAO tx_wordclk_bufg/O JBUFGCEXhzr a]g_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/tx_wordclk Jnet (fo=27439, routed)XhhE@X2Y4 (CLOCK_ROOT)D JXhSLR Crossing[0->1] {wg_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[92]/C JFDCEXhzr> Jclock pessimismXh=@ Jclock uncertaintyXhڽ yug_gbt_bank[1].gbtbank/i_gbt_bank/gbt_txgearbox_multilink_gen[8].gbt_txgearbox_inst/txFrame_from_frameInverter_reg[92]Recov_DFF_SLICEL_C_CLR JFDCEXhv/ JXh< J required timeXhz4A; J arrival timeXhv/ JXh4 JslackXhÆ@#FF_RX_PRESENTn[0]FF_RX_PRESENTn[1]FF_RX_PRESENTn[2]FF_RX_PRESENTn[3] FF_RX_SCL[0] FF_RX_SCL[1] FF_RX_SCL[2] FF_RX_SCL[3] FF_RX_SDA[0] FF_RX_SDA[1] FF_RX_SDA[2] FF_RX_SDA[3]FF_TX_PRESENTn[0]FF_TX_PRESENTn[1]FF_TX_PRESENTn[2]FF_TX_PRESENTn[3] FF_TX_SCL[0] FF_TX_SCL[1] FF_TX_SCL[2] FF_TX_SCL[3] FF_TX_SDA[0] FF_TX_SDA[1] FF_TX_SDA[2] FF_TX_SDA[3] Si_LOLb Si_SCL Si_SDA board_id[0] board_id[1] board_id[2] board_id[3] board_id[4] board_id[5] board_id[6] rarp_enFF_RX_RESETn[0]FF_RX_RESETn[1]FF_RX_RESETn[2]FF_RX_RESETn[3] FF_RX_SCL[0] FF_RX_SCL[1] FF_RX_SCL[2] FF_RX_SCL[3] FF_RX_SDA[0] FF_RX_SDA[1] FF_RX_SDA[2] FF_RX_SDA[3]FF_TX_RESETn[0]FF_TX_RESETn[1]FF_TX_RESETn[2]FF_TX_RESETn[3] FF_TX_SCL[0] FF_TX_SCL[1] FF_TX_SCL[2] FF_TX_SCL[3] FF_TX_SDA[0] FF_TX_SDA[1] FF_TX_SDA[2] FF_TX_SDA[3] Si_IN_SEL[0] Si_IN_SEL[1] Si_SCL Si_SDA